Robert W. Brodersen EECS140 Analog Circuit Design
|
|
- Hester Stewart
- 5 years ago
- Views:
Transcription
1 INTRODUCTION University of California Berkeley College of Engineering Department of Electrical Engineering and Computer Science Robert. Brodersen EECS40 Analog Circuit Design ROBERT. BRODERSEN LECTURE
2 EECS 40 ANALOG INTEGRATED CIRCUITS INTRODUCTION I Robert. Brodersen, 779, 40 Cory Hall, rb@eecs.berkeley.edu This course will focus on the design of MOS analog integrated circuits with extensive use of Spice for the simulations. In addition, some applications of analog integrated circuits will be covered which will include RF amplification and discrete and continuous time filtering. Though the focus will be on MOS implementations, comparison with bipolar circuits will be given. Required Text Analysis and Design of Analog Integrated Circuits, 4th Edition, P.R. Gray, P. Hurst, S. Lewis and R.G. Meyer, John iley and Sons, 00 Supplemental Texts B. Razavi, Design of Analog CMOS Integrated Circuits, McGrawHill, 00. Thomas Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press, 998 The SPICE Book, Andre Vladimirescu, John iley and Sons, 994 EECS 05: Microelectronic Devices and Circuits Prerequisites ROBERT. BRODERSEN LECTURE
3 IC Design Course Structure at Berkeley EE40 INTRODUCTION I EE05 EE40 Linear/Analog EE4 NonLinear EE4 Digital Linear Design Sensors, Transducers Interface Circuits Digital Processing Amplifiers, Filters, A/D & D/A s ROBERT. BRODERSEN LECTURE
4 University of California Berkeley College of Engineering Department of Electrical Engineering and Computer Science Robert. Brodersen EECS40 Analog Circuit Design Lectures on MOS DEVICE MODELS ROBERT. BRODERSEN LECTURE
5 Assumed Knowledge M a) KCL, KVL Kirchoff Laws b) Voltage, Current Dividers c) Thevenin, Norton Equivalents d) Port Equivalents e) Phasors, Frequency Response ROBERT. BRODERSEN LECTURE
6 V s i in R s + + ν in + a ν ν in Port Equivalent Circuit (Voltage in Voltage out) R in R out + ν out i out RL R in R out A ν ν in i in ν out i out ν out ν in R L i out 0 R L R S ν in 0 M i in i out V s + + ν in + a ν ν in R in R out + ν out + ν in R in + R out + a ν ν in ν out ν out a ν ν in a ν ν out a ν a ν ν R in in + R out R in ROBERT. BRODERSEN LECTURE
7 MOS Large Signal Equations M3 nchannel D I DS V DSAT G B V GS I DS Saturation S NMOS Linear Cutoff S G L D V DS n p n B ROBERT. BRODERSEN LECTURE
8 Cutoff : V GS < V T MOS Large Signal Equations (Cont.) M4 Linear : V GS > V T V DS < V DSAT V GS V T I DS k' Saturated : V GS V DS I DS > V T V DS L V V V GS T DS > V DSAT V GS V T k' ( V GS V T ) ( + λ V DS ) L ROBERT. BRODERSEN LECTURE
9 MOS Large Signal Equations (Cont.) M5 V T V To + γ [( φ f + V SB ) ( φ f ) ] V To Threshold V SB 0 φ f Fermi Potential 0.3 γ λ L Body Effect Factor Short Channel Effect idth of Device Length k' µ C ox ( V SB > 0) µ ν ε E V DS /L mobility Oxide Capacitance E ROBERT. BRODERSEN LECTURE
10 MOS Large Signal Equations (Cont.) M6 Body Effect : V To + γ V SB V T S G D n n γ q ε N A C ox V To 0 V BS ROBERT. BRODERSEN LECTURE
11 MOS Large Signal Equations (Cont.) M7 Short Channel Effect (λ): S G D X D X J Junction Depth L drawn L D Lateral Diffusion ~ 0.75 X J L L drawn L D L EFF L X D X D fv ( DS ) ROBERT. BRODERSEN LECTURE
12 MOS Large Signal Equations (Cont.) M8 I k' ( A ) D I k' ( B ) D ( B) I D V DS λ ( V GS V T ) L EFF Modeled as ( V GS V T ) ( + λ V DS ) L I DS ( A) I D V DS k' ( V GS V T ) dv DS L EFF dl EFF ( A) I D V DS dx D λ I D I D L EFF dv DS ROBERT. BRODERSEN LECTURE 3
13 MOS Large Signal Equations (Cont.) λ L EFF dx D L dv DS dx D dv DS eak function of V DS ε ( V X DS V DSAT ) D q N A Fixed ε Dielectric constant of silicon N A Substrate doping dx D dv DS ε q N A V DS V DSAT ROBERT. BRODERSEN LECTURE 3
14 MOS Large Signal Equations (Cont.) M9 G I DS Ideal λi DS Longer Channel (Increasing L) S L D V DS /L is the parameter of interest C G L C OX ROBERT. BRODERSEN LECTURE 3
15 MOS Small Signal Model (Low Frequency) M0 M I DS G + g m ν gs D V GS r o g mbs ν bs S + V SB B I DS di DS ν gs + dv GS dv BS di DS di ν bs + DS dv DS ν ds g m g mbs /r o ROBERT. BRODERSEN LECTURE 3
16 MOS Small Signal Model (Cont.) M In Saturation : g m di DS k' ( V dv GS V T ) ( + λ V DS ) GS L g m + k' ( V GS V T ) L hat is V DSAT? G S V GS V T + V DSAT I DS g m V DSAT k' V DSAT k' I DS L L k' ( V GS V T ) L k' V DSAT so, L I DS k' L k' V DSAT L and from above, ROBERT. BRODERSEN LECTURE 3
17 MOS Small Signal Model (Cont.) M3 g mbs calculation : di DS g mbs g mb dv BS k' ( V GS V T ) ( + λ V DS ) L dv T dv BS dv T dv BS γ χ ( φ f + V SB ) 0.5 g mbs k' ( V GS V T ) ( + λ V DS ) χ L g m g mbs χ g m χ γ ( φ f + V SB ) 0.5 ROBERT. BRODERSEN LECTURE 3
18 MOS Small Signal Model (Cont.) M4 C ox 0.3 G g mbs χ g m 0. S n C js n D 5V 0V V BS γ 0.5 φ f 0.3 k 90e6 λ 0.0 V To 0.7 Qchannel duetovgs C ox ν gs Qchannel duetovbs C js ν bs χ C js C ox ROBERT. BRODERSEN LECTURE 3
19 MOS Small Signal Model (Cont.) M5 r o calculation : di DS g r mds o dv DS d d V DS k' ( V GS V T ) ( + λ V DS ) L k' r o ( V GS V T ) λ L λ I r DS o r 0 λ I DS ROBERT. BRODERSEN LECTURE 3
20 MOS Small Signal Model (Cont.) Comparison with Spice Level : M6 VTO V To 0.5.0V PHI φ f 0.6 GAMMA γ LAMBDA λ KP k' µ C ox nmos 50 00µ A V pmos nmos 3 ROBERT. BRODERSEN LECTURE 3
21 LECTURES ON SPICE Summary: g m k' I DS L g mbs χ g γ χ ( φ f + V SB ) 0.5 r 0 λ I DS g m I DS I V DS DSAT k' L m V GS V T MOS Small Signal Model (Cont.) V DSAT k' V DSAT L I DS V DSAT V DSAT V GS V T I V GS V DS T + k' L I DS k' ( V GS V T ) L V T V To + γ [( φ f + V SB ) ( φ f ) ] ROBERT. BRODERSEN LECTURE 4
22 LECTURES ON SPICE University of California Berkeley College of Engineering Department of Electrical Engineering and Computer Science Robert. Brodersen EECS40 Analog Circuit Design Lectures on SPICE ROBERT. BRODERSEN LECTURE 4
23 Spice Transistor Model : LECTURES ON SPICE SP M 3 4 nch Lµ 0µ AD( ) AS( ) PD( ) PS( ) NRD( ) parasitic resistors G area of drain S L D 3 4 ROBERT. BRODERSEN LECTURE 4
24 SPICE LECTURES ON SPICE SP Initial Operationg Point DC currents and Voltages Linearize Around OP Point Solve Eqn. New Operating Point No DC Converge? Yes Increment Time Analysis Types : DC op point.op DC sweeps AC & Transient No End of Time Interval Yes STOP ROBERT. BRODERSEN LECTURE 4
25 LECTURES ON SPICE 4 V A SP3 + V B R 4 I + R R R 3 I 4 3 G i /R i Node : ( G + G 4 ) V G V G 4 V 4 + I 0 Node : G V + ( G + G + G 3 ) V G 3 V 3 0 Node 3 : G 3 V + G 3 V 3 I 4 0 Node 4 : G 4 V G 4 V 4 + I 4 0 V V B V 3 V 4 V A ROBERT. BRODERSEN LECTURE 4
26 LECTURES ON SPICE SP4 G +G 4 G 0 G 4 0 V 0 G G +G +G 3 G V 0 0 G 3 G V 3 0 G G 4 0 V I V B I 4 V A Current src G F V C B R I E Votlage src Total # of EQNS Nn + n v + n l n # of circuit nodes n v # of independent voltage srcs n l # of inductors ROBERT. BRODERSEN LECTURE 4
27 Matrix Solution LECTURES ON SPICE SP5 A x b we need Solve by Gaussian Elimination (0) denotes iteration step e e e 3 a a a 3 a a a 3 a 3 a 3 a 33 x x x 3 b b b 3 Eliminate a,a 3 ( ) e e ( ) e e 0 ( ) a e a ( ) e 3 e 3 0 ( ) a 3 e a xxx 0 xx 0 xx ROBERT. BRODERSEN LECTURE 4
28 LECTURES ON SPICE SP6 Then eliminate a 3 () ( ) e ( ) e ( ) e 3 ( ) e ( ) e e 3 ( ) ( ) a 3 ( ) e ( ) a xxx 0 xx 00x Upper triangular matrix can be solved ( ) a ( ) a ( ) 0 a ( ) a 3 ( ) a 3 x x b ( ) b ( ) 0 0 a 33 x 3 ( ) b 3 ( ) b x 3 3 ( ) a 33 b ( ) ( x a ( ) 3 x 3 ) ( ) a b ( 0 ) x a ( 0 ) ( 3 x 3 a x ) a Solution ROBERT. BRODERSEN LECTURE 4
29 Accuracy LECTURES ON SPICE SP7 A Can t divide by 0 or small numbers, so pivoting is used to reorder eqn s (Basically renumbering nodes). Puts maximum values on diagonal. R Ω R 0kΩ.000 V V 0 G 0k + G If the computer only has 4 digits of precision then we get, Actually, V V 000V, 0000V, V V 0 V V V + V 0 V, V ROBERT. BRODERSEN LECTURE 4
30 To control accuracy LECTURES ON SPICE SP8.options PIVTOL <values> (0 8 ) This sets the allowable range of conductance values. *ERROR* : Maximum entry...at STEP... is less than PIVTOL Probably means you have an incorrect element or floating node ROBERT. BRODERSEN LECTURE 4
31 Solution of the DC equations with nonlinear models LECTURES ON SPICE SP9 I D I S e I G G V V D V TH + I A I G Need to find this point I A G I G V D I D I D,G I D ROBERT. BRODERSEN LECTURE 4
32 NewtonRaphson Iteration : LECTURES ON SPICE SP0 Make guess of next operation point in iteration Start at initial guess and linearize diode eqn. + I A G G D0 V D (0) I D0 ROBERT. BRODERSEN LECTURE 4
33 LECTURES ON SPICE SP Current value I D0 Solution finds this point Slope of G D0 I D V D Solve for V D, becomes V D () Linearize at this point Find new point ROBERT. BRODERSEN LECTURE 4
34 LECTURES ON SPICE Convergence SP Keep iterating until all voltages and currents are within a a tolerance value. () i V n ε Vn node voltage n at iteration i REL( V) max V ( i + ) () i ( n, V n ) + ABS( V) The convergence check is : ( i + ) V n () i V n ε Vn REL( V) 0 4 (Default 0 3 ROBERT. BRODERSEN LECTURE 4 ) ABS( V) 0 6 (Default 50µV ) ABS(V) should be at least two orders of magnitude below required accuracy. These values would give part in 0 4 accuracy down to 00µV resolution
35 SP3 Current convergence is broken into two types; MOS and NOT MOS MOS 6 ABSMOS ABSOLUTE( 0 ) RELMOS RELATIVE( 0.5) NOTMOS 9 ABSI ABSOLUTE( 0 ) RELI RELATIVE( 0.0) ITL # of steps in iteration (00) hen you get *ERROR* no convergence in DC analysis and the last node voltages Then it hasn t converged in 00 times something is probably wrong with your netlist ROBERT. BRODERSEN LECTURE
MOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationLecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:
Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationThe Devices. Devices
The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors
More informationIntroduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationMOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor
MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste
More information6.012 Electronic Devices and Circuits Spring 2005
6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):
More informationCircuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >
More informationECEN474/704: (Analog) VLSI Circuit Design Spring 2018
ECEN474/704: (Analog) SI Circuit Design Spring 2018 ecture 2: MOS ransistor Modeling Sam Palermo Analog & Mixed-Signal Center exas A&M University Announcements If you haven t already, turn in your 0.18um
More informationLecture 12: MOSFET Devices
Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationEE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania
1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationEE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR
EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3
More informationChapter 13 Small-Signal Modeling and Linear Amplification
Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors
More informationUniversity of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA
University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @
More informationCMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor
CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1
More informationN Channel MOSFET level 3
N Channel MOSFET level 3 mosn3 NSource NBulk NSource NBulk NSource NBulk NSource (a) (b) (c) (d) NBulk Figure 1: MOSFET Types Form: mosn3: instance name n 1 n n 3 n n 1 is the drain node, n is the gate
More informationEE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits
EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationII III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing
II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band
More informationEE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationE2.2 Analogue Electronics
E2.2 Analogue Electronics Instructor : Christos Papavassiliou Office, email : EE 915, c.papavas@imperial.ac.uk Lectures : Monday 2pm, room 408 (weeks 2-11) Thursday 3pm, room 509 (weeks 4-11) Problem,
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationEE5311- Digital IC Design
EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM
More informationLecture 12 CMOS Delay & Transient Response
EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology
More informationLECTURE 3 MOSFETS II. MOS SCALING What is Scaling?
LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and
More informationEEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring
More informationSECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University
NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing
EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics
More informationLecture 10 MOSFET (III) MOSFET Equivalent Circuit Models
Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationOperation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS
Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2
More informationMOSFET Capacitance Model
MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small
More informationLecture 210 Physical Aspects of ICs (12/15/01) Page 210-1
Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences PROBLEM SET #3 (SOLUTION)
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences R. W. Brodersen EECS 140 Fall 2004 PROBLEM SET #3 (SOLUTION) 3) In the above circuit, use V DD
More informationECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationEECS 141: FALL 05 MIDTERM 1
University of California College of Engineering Department of Electrical Engineering and Computer Sciences D. Markovic TuTh 11-1:3 Thursday, October 6, 6:3-8:pm EECS 141: FALL 5 MIDTERM 1 NAME Last SOLUTION
More informationMOSFET Physics: The Long Channel Approximation
MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The
More informationEKV MOS Transistor Modelling & RF Application
HP-RF MOS Modelling Workshop, Munich, February 15-16, 1999 EKV MOS Transistor Modelling & RF Application Matthias Bucher, Wladek Grabinski Electronics Laboratory (LEG) Swiss Federal Institute of Technology,
More informationToday s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationEE 560 MOS TRANSISTOR THEORY
1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!
More informationChapter 2 MOS Transistor theory
Chapter MOS Transistor theory.1 Introduction An MOS transistor is a majority-carrier device, which the current a conductg channel between the source and the dra is modulated by a voltage applied to the
More informationECE 438: Digital Integrated Circuits Assignment #4 Solution The Inverter
ECE 438: Digital Integrated Circuits Assignment #4 The Inverter Text: Chapter 5, Digital Integrated Circuits 2 nd Ed, Rabaey 1) Consider the CMOS inverter circuit in Figure P1 with the following parameters.
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal
More informationSection 12: Intro to Devices
Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si
More informationLecture 12: MOS Capacitors, transistors. Context
Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those
More informationEE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET
EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically
More informationEEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,
More informationCMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance
CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More information1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012
/3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F
More informationLEVEL 61 RPI a-si TFT Model
LEVEL 61 RPI a-si TFT Model Star-Hspice LEVEL 61 is an AIM-SPICE MOS15 amorphous silicon (a-si) thin-film transistor (TFT) model. Model Features AIM-SPICE MOS15 a-si TFT model features include: Modified
More informationMicroelectronics Main CMOS design rules & basic circuits
GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September
More informationElectronic Circuits Summary
Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent
More information6.012 Electronic Devices and Circuits
Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationChapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,
More informationLecture 23: Negative Resistance Osc, Differential Osc, and VCOs
EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationBipolar Junction Transistor (BJT) - Introduction
Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification
More informationEECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology
EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor
More informationLecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation
Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open
More informationLecture 37: Frequency response. Context
EECS 05 Spring 004, Lecture 37 Lecture 37: Frequency response Prof J. S. Smith EECS 05 Spring 004, Lecture 37 Context We will figure out more of the design parameters for the amplifier we looked at in
More informationNanoscale CMOS Design Issues
Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI-1 Class Transistor I-V Review Agenda Non-ideal
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationLecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-1 Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 Contents: 1. Non-ideal and second-order
More informationMicroelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -
6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large
More informationLecture 14: Electrical Noise
EECS 142 Lecture 14: Electrical Noise Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2008 by Ali M. Niknejad A.M.Niknejad University of California, Berkeley EECS 142 Lecture 14 p.1/20
More informationECE 546 Lecture 16 MNA and SPICE
ECE 546 Lecture 16 MNA and SPICE Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Nodal Analysis The Node oltage method
More informationECE321 Electronics I
EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman Zarkesh-Ha Office: EE Bldg. 3B Office hours: Tuesday :-3:PM or by appointment E-mail: payman@ece.unm.edu Slide: 1
More informationStudio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS )
Studio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS ) 1 Simulation Review: Circuit Fixed V GS, Sweep V DS I
More informationFig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)
1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed
More information! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible
More informationThe Physical Structure (NMOS)
The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two
More informationCMOS Cross Section. EECS240 Spring Today s Lecture. Dimensions. CMOS Process. Devices. Lecture 2: CMOS Technology and Passive Devices
EECS240 Spring 2008 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS echnology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 oday s Lecture
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationSOME USEFUL NETWORK THEOREMS
APPENDIX D SOME USEFUL NETWORK THEOREMS Introduction In this appendix we review three network theorems that are useful in simplifying the analysis of electronic circuits: Thévenin s theorem Norton s theorem
More information