IBIS Modeling Using Latency Insertion Method (LIM)

Transcription

1 IBIS Modeling Using Latency Insertion Method (LIM) José E. Schutt Ainé University of Illinois at Urbana- Champaign Jilin Tan, Ping Liu, Feras Al Hawari, Ambrish arma Cadence Design Systems European IBIS Summit May 16, 2012 Sorrento, Italy

2 Nonlinear Circuit How do we solve a simple diode circuit problem? Graphical method... solve transcendental equations s /R I D Diode characteristics Load line (external characteristics) D out S I I e D D / T 1 RI RI ( ) S D D D D D out S D ECE-Illinois IBIS Summit Sorrento, Italy May 16,

3 Diode Circuit Iterative Method or use the Newton Raphson method 1 Use: xk1 xk f '( xk) f ( xk) out D ( k1) ( k) ( k) 1 ( k) x x f '( x ) f( x ) D 1 IS D / T S D / T f( D) ISe 10 f '( D ) e R R T ( k1) ( k) D D ( k ) D R 1 R S I I S T S e e ( k ) D ( k ) D / / T T 1 ( Where k ) is the value of D at the kth iteration D Procedure is repeated until convergence to final (true) value of D which is the solution. Rate of convergence is quadratic. ECE-Illinois IBIS Summit Sorrento, Italy May 16,

4 Newton Raphson Method (Graphical Interpretation) solution ECE-Illinois IBIS Summit Sorrento, Italy May 16,

5 Newton Raphson Method If initial guess is not close enough, NR will lock into oscillations and solution will not converge ECE-Illinois IBIS Summit Sorrento, Italy May 16,

6 IBIS data can be unpredictable Transient response requires solution of nonlinear system Most simulators use Newton Raphson (NR) technique combined with modified nodal analysis (MNA) NR may not converge Limitations NR may slow down simulation ECE-Illinois IBIS Summit Sorrento, Italy May 16,

7 Why LIM? LIM does not iterate on nonlinear problems There is no convergence issue MNA has super linear numerical complexity LIM has linear numerical complexity LIM uses no matrix formulation LIM has no matrix ill conditioning problems LIM is much faster than MNA for large circuits ECE-Illinois IBIS Summit Sorrento, Italy May 16,

8 Latency Insertion Method** Each branch must have an inductor* Each node must have a shunt capacitor* Express branch current in terms of history of adjacent node voltages Express node voltage in terms of history of adjacent branch currents * If branch or node has no inductor or capacitor, insert one with very small value ** J. E. Schutt-Ainé, "Latency Insertion Method for the Fast Transient Simulation of Large Networks," IEEE Trans. Circuit Syst., vol. 48, pp , January ECE-Illinois IBIS Summit Sorrento, Italy May 16,

9 LIM: Leapfrog Method n n1 n2 ij ij ij I I I n1/2 n3/2 n5/2 i i i n: time C N a n1/2 i i n Hi n1/2 t k 1 i Ci G i t I n ik t I I R I n1 n n1/2 n1/2 n ij ij i j ij ij Lij Leapfrog method achieves second-order accuracy, i.e., error is proportional to t 2 ECE-Illinois IBIS Summit Sorrento, Italy May 16,

10 LIM Algorithm Represents network as a grid of nodes and branches Discretizes Kirchhoff's current and voltage equations C Branch structure Node structure N a n1/2 i i n Hi n1/2 t k1 i Ci G i t I n ik t I I R I Uses leapfrog scheme to solve for node voltages and branch currents Presence of reactive elements is required to generate latency n1 n n1/2 n1/2 n ij ij i j ij ij Lij ECE-Illinois IBIS Summit Sorrento, Italy May 16,

11 LIM is Easy to Code For time=1, N t time loop branch loop For branch =1, N b Update current as per Equation: t I I R I E n1 n n1/2 n1/2 n n1/2 ij ij i j ij ij ij Lij Next branch; For node=1, N n Update voltage as per Equation node loop n1/2 i C i t n1/2 i M i N n n n i ik q k1 q1 H I J Ci t G i Next node; Next time; ECE-Illinois IBIS Summit Sorrento, Italy May 16,

12 LIM is Fast Comparison of runtime for LIM and SPICE per 100 time steps. Circuit # nodes # MOSFET SPICE LIM ADDER s s OTER s s RAM CKT s 0.184s ECE-Illinois IBIS Summit Sorrento, Italy May 16,

13 and gets faster as circuit size increases 140 LIM v.s. SPICE 120 Speedup Factor Log Size (normalized to 2,000 nodes) ECE-Illinois IBIS Summit Sorrento, Italy May 16,

14 LIM has NO Convergence Issues Introduce latency in diode circuit through a small inductor L then use colocation and leapfrog: n n1 n2 D D, D, D,... n n I I n1/2 n1/2 n3/2 ID ID, ID, ID,... with L L t and if time steps are sufficiently small, Current solution oltage solution n1/2 ID IS e or n D / T 1 n1/2 n1 I D D T ln 1 IS 1/2 n1/2 Explicit! ECE-Illinois IBIS Summit Sorrento, Italy May 16,

15 LIM Suffers from Stability Issues Stable simulation Unstable simulation ECE-Illinois IBIS Summit Sorrento, Italy May 16,

16 but they can be controlled The LIM algorithm is conditionally stable No faster than speed of light propagation The Amplification Matrix [5] Eigenvalues must be less than unity for the system to be stable A-matrix provides the exact limit on the size of the time step n1/2 n1/2 v v n1 A n i i Stable simulation Unstable simulation The Energy Method [6] t i Nn N C b i 2min min( Lip, ) i1 i N p1 b Smallest LC product in the circuit Provides a sufficient condition on Δt Easy to use in our simulations ECE-Illinois IBIS Summit Sorrento, Italy May 16,

17 Application of LIM to IBIS IBIS Data Processing Ku/Kd Extraction IBIS Standard Formulation LIM IBIS Formulation LIM IBIS Solutions Extension to Gate Modulation Effects Conclusion and Future Work ECE-Illinois IBIS Summit Sorrento, Italy May 16,

18 IBIS Data Processing 1. Arrange static I data 2. Pulldown data (current vs voltage) I pd, m pd points 3. Pullup data (current vs voltage) I pu, m pu points 4. Ground clamp data (current vs voltage) I gc, m gc points 5. Power clamp data (current vs voltage) I pc, m pc points ECE-Illinois IBIS Summit Sorrento, Italy May 16,

19 IBIS Data Processing Next Get T data. T data is presented as: Rising waveform: oltage versus time for fix low R1, m r1 points oltage versus time for fix high R2, m r2 points: Falling waveform: oltage versus time for fix low F1, m f1 points oltage versus time for fix high F2, m f2 points ECE-Illinois IBIS Summit Sorrento, Italy May 16,

20 IBIS Ku/Kd Extraction* I fixt out R fixt fixt I cap C fixt out t t t out t I L t out comp fixt out I I I out cap fixt ECE-Illinois IBIS Summit Sorrento, Italy May 16,

21 Ku/Kd Extraction We need to extract K u and K d Procedure is well documented* Pick value comp1 Find closest corresponding currents in static I data Set them as I pd1, I pu1, I gc1 and I pc1 Pick value comp2 Find closest corresponding currents in static I data Set them as I pd2, I pu2, I gc2 and I pc2 * Ying Wang, Han Ngee Tan "The Development of Analog SPICE Behavioral Model Based on IBIS Model", Proceedings of the Ninth Great Lakes Symposium on LSI, GLS '99. ECE-Illinois IBIS Summit Sorrento, Italy May 16,

22 I KI KI I I out1 u pu1 d pd1 pc1 gc1 I KI KI I I Rearrange as: IBIS Circuit Analysis 2 equations, two unknown system out 2 u pu 2 d pd 2 pc2 gc2 KI KI I I I I u pu1 d pd1 out1 pc1 gc1 RHS1 or KI KI I I I I u pu 2 d pd 2 out 2 pc2 gc2 RHS 2 I I K I pu1 pd1 u RHS1 Ipu2 I pd 2 K d I RHS2 Solve for K u and K d ECE-Illinois IBIS Summit Sorrento, Italy May 16,

23 Example of Ku and Kd Rising Waveform Falling Waveform ECE-Illinois IBIS Summit Sorrento, Italy May 16,

24 IBIS Simulations KI KI I I u pu comp d pd comp pc comp gc comp 0 I I I out comp C comp G comp Nonlinear system use Newton Raphson comp comp ECE-Illinois IBIS Summit Sorrento, Italy May 16,

25 or Better: Use a LIM Formulation G C I t 2 n 12 / n 12 / ext ext ext n 12 / n 12 / n ext ext ext out I I R L I I t 2 n1 n n 12 / n 12 / out out pkg n1 n comp ext pkg out out I I C G n ext ext n 12 / out ext n 12 / t 2 ext Cext Gext t 2 n 12 / n 12 / n pkg pkg comp ext out n1 t 2 out Lpkg Rpkg 2 L R I t ECE-Illinois IBIS Summit Sorrento, Italy May 16,

26 IBIS-LIM Solution G C I I t 2 n 12 / n 12 / comp comp comp n 12 / n 12 / n n comp comp comp out dev C G I I n n comp comp n 12 / out dev comp n 12 / t 2 comp Ccomp Gcomp t 2 n I K I K I I I dev u pu comp d pd comp pc comp gc comp Explicit equations ECE-Illinois IBIS Summit Sorrento, Italy May 16,

27 Transient Simulation Examples NR and LIM give same results ECE-Illinois IBIS Summit Sorrento, Italy May 16,

28 Transient Simulation Examples in some cases Newton Raphson fails to converge LIM NR: failed convergence NR: failed convergence LIM ECE-Illinois IBIS Summit Sorrento, Italy May 16,

29 Handling Gate Modulation Effects (BIRD 98.3) LIM IBIS formulation can easily be modified to handle SSN K t I K K t I d gd sspd gd d gd K sspu pu I sspu I sspu pu 0 K t I K K t I u pu sspu pu u pu K sspd gd I sspd I sspd gd 0 ECE-Illinois IBIS Summit Sorrento, Italy May 16,

30 Gate Modulation Effects (BIRD 98.3) Large power supply inductance Small decoupling capacitance L pu = 5 nh C pu = nf ECE-Illinois IBIS Summit Sorrento, Italy May 16,

31 Gate Modulation Effects (BIRD 98.3) Small power supply inductance Large decoupling capacitance L pu = nh C pu = 0.1 nf ECE-Illinois IBIS Summit Sorrento, Italy May 16,

32 Conclusions We demonstrated that LIM can be used to simulate IBISbased circuits with optimum accuracy. Because of the inserted latency, LIM does not use an iterative scheme to solve nonlinear equations and thus does not suffer from convergence problems LIM based simulations were successful in instances where the traditional Newton Raphson technique failed to provide a solution LIM is expected to be several orders of magnitude faster for large circuits containing a multitude of IBIS models. ECE-Illinois IBIS Summit Sorrento, Italy May 16,

33 References [1] J. E. Schutt-Ainé, "Latency Insertion Method for the Fast Transient Simulation of Large Networks," IEEE Trans. Circuit Syst., vol. 48, pp , January [2] Dmitri Klokotov, and José Schutt-Ainé, Transient Simulation of Lossy Interconnects using the Latency Insertion Method (LIM), Proceedings of the 17th Topical Meeting on Electrical Performance of Electronic Packaging (EPEP), pp , San Jose, CA, October [3] José Schutt-Ainé, "Stability Analysis of the Latency Insertion Method Using a Block Matrix Formulation", Proceedings of EDAPS-08, Seoul, South Korea, December [4] J. Schutt-Aine, D. Klokotov, P. Goh, Jilin Tan, F. Al-Hawari, Ping Liu, Wenliang Dai, "Application of the latency insertion method to circuits with blackbox macromodel representation," Proceedings of the 11th Electronics Packaging Technology Conference (EPTC), pp , Singapore, December [5] P. Goh, J. Schutt-Aine, D. Klokotov, J. Tan, P. Liu, W. Dai, and F. Al-Hawari, Partitioned latency insertion method with a generalized stability criteria, IEEE Trans. on Comp., Packaging and Manufacturing Tech., vol.1, no. 9, Sept [6] S. Lalgudi and M. Swaminathan, Analytical stability condition of the latency insertion method for nonuniform GLC circuits, IEEE Trans. on Circuits and Systems, vol. 55, no. 9, Sept [7] Ying Wang, Han Ngee Tan "The Development of Analog SPICE Behavioral Model Based on IBIS Model", Proceedings of the Ninth Great Lakes Symposium on LSI, GLS '99. [8] P. Tehrani, Y. Chen, and J. Fang, "Extraction of Transient Behavioral Model of Digital I/O Buffers from IBIS," Proceedings of 1996 ECTC Conference, pp ECE-Illinois IBIS Summit Sorrento, Italy May 16,