THE performance of traditional single-gate MOSFETs

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1 688 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 3, MARCH 2014 Analytical Models for Electric Potential, Threshold Voltage, and Subthreshold Swing of Junctionless Surrounding-Gate Transistors Guangxi Hu, Member, IEEE, Ping Xiang, Zhihao Ding, Ran Liu, Lingli Wang, Member, IEEE, and Ting-Ao Tang, Senior Member, IEEE Abstract Analytical models for electric potential, threshold voltage, and subthreshold swing of the junctionless surroundinggate field-effect transistors are presented. Poisson equation is solved and the electric potential is obtained. With the potential model, explicit expressions for threshold voltage and subthreshold swing are obtained. The analytical results are compared with those from simulations and excellent agreements are observed. The analytical models are useful not only for fast circuit simulations, but also for device design and optimization. Index Terms Analytical model, junctionless (JL) fieldeffect transistor (FET), modeling and simulation, surrounding gate (SG). I. INTRODUCTION THE performance of traditional single-gate MOSFETs degrades seriously with the scaling of gate length and gate oxide thickness, as the decrease of carrier s effective mobility and the short-channel effects (SCEs) strongly affect the devices. To overcome these problems, MOSFETs with novel structures are proposed, such as double-gate (DG), surrounding-gate (SG), FinFET, and so on. However, the formation of the very shallow source/drain, the resistance arising from the source/drain junction, the doping techniques, and thermal budget still pose restrictions on the use of these novel MOSFETs. To improve the device performance and ease the fabrication process, a new type of transistor, the junctionless (JL) multigate MOSFET, has been proposed and studied to some extent [1] [6]. Distinct from the traditional SG MOSFET with different types of doping in the channel and the source/drain regions, the JL transistor has a uniform high doping concentration throughout the channel and source/drain regions, which greatly simplifies the fabrication process [3] and improves the device electric properties through small subthreshold swings and large ON-state currents [3] [6]. Manuscript received December 3, 2012; revised December 15, 2013; accepted December 27, Date of publication January 14, 2014; date of current version February 20, This work was supported in part by the National Natural Science Foundation of China Project under Grant and Grant , in part by the State Key Laboratory of ASIC and System Project under Grant 11MS015, and in part by the Special Funds for Major State Basic Research 973 Project under Grant 2011CBA The review of this paper was arranged by Editor H. S. Momose. The authors are with the State Key Laboratory of ASIC and System, Fudan University, Shanghai , China ( gxhu@fudan.edu.cn). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TED A number of analytical models for drain current, I DS, threshold voltage, V th, and subthreshold swing, S, have been proposed to study JL MOSFETs. Duarte et al. [7] presented a nonpiecewise I DS model of a JLSG MOSFET. Choi et al. [8] studied the effects of nanowire width variation on the V th of a JLDG MOSFET. They concluded that the V th fluctuation caused by the width variation of a JL transistor is significantly larger than that of a traditional inversion-mode (IM) transistor. Rios et al. [9] conducted a research on the V th of the trigate transistor and found a dual V th behavior for a JL MOSFET, i.e., a low value governs the subthreshold turn-on and a high value determines the extrapolated threshold of the accumulation regime. Taur et al. [10] investigated the dopant number fluctuation effects on V th in JLDG MOSFETs and drew a conclusion that the effect of dopant number fluctuations on the V th of a minimum width JL MOSFET would be a serious problem. Gnudi et al. [11] stated that the standard deviation of the V th due to discrete dopant fluctuations could be large in a well-scaled 20-nm JL FET. In this paper, we present a comprehensive analytical model to describe potential profile of JLSG MOSFETs by solving 2-D Poisson equation (PE) so that the gradual channel approximation is not needed. Based on the potential model, analytical expressions for V th and S are obtained. Our model results are compared with those from Medici simulations [12] and excellent agreements are found. The models provide a simple and direct way to calculate channel potential, threshold voltage, and subthreshold swing, as well as to understand the behavior of the device. II. MODELS The schematic diagram of the device is shown in Fig. 1. The gate length, gate oxide thickness, and silicon body radius of a JLSG MOSFET are denoted by L, t ox,andr, respectively. The Fermi level at the source end is chosen to be the reference potential, V R. A. Electric Potential With the consideration of the symmetry, the PE in a cylindrical coordinate can be expressed as 2 φ ρ [ ( )] φ ρ ρ + 2 φ z 2 = qn D φ V 1 exp (1) ε si V t IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 HU et al.: ANALYTICAL MODELS FOR ELECTRIC POTENTIAL, THRESHOLD VOLTAGE, AND SUBTHRESHOLD SWING 689 Similar to the method used in [14] and [15], we assume that the solution of (3) is in a parabolic form in the radial direction, then the potential can be expressed as φ (ρ,z) = φ (0, z) ρ2 4 2 [φ (0, z) V GF] (4) where φ (0, z) is the electric potential in the silicon center and given by φ (0, z) = V GF + V R + H + (V DS V GF H) sinh (z/) (V GF + H) sinh [(L z) /] sinh (L/) (5) where and H qn D 2 ε si = qn D R 2 2ε si ln (1 + t ox /R) + ε ox 4ε ox ε si (6) R [2ε si ln (1 + t ox /R) + ε ox ] / (4ε ox ) (7) which is the feature length. Fig. 1. (a) Bird s-eye view of a JLSG MOSFET diagram. (b) Cross-sectional view of the transistor. where φ is the electric potential in the channel, ρ is the radial coordinate, z is the coordinate along the channel length, ε si is the silicon permittivity, N D is the doping concentration, V t = k B T/q is the thermal voltage, and V is the quasi-fermi potential. q, k B,andT have their usual meanings. In this paper, the source end is set to the reference voltage, V R. The boundary conditions are: φ (ρ,0) = V R, φ (ρ, L) = V R + V DS, φ/ ρ ρ = 0 = 0, and φs=φ (R, z) = V GF ε si / C ox φ/ ρ ρ=r,wherev DS is the bias applied to the drain, V GF V GS V FB, with V GS being the gate bias and V FB the flat-band voltage, assuming there is no charge in the oxide and the silicon oxide interface is clean, V FB can be expressed as V FB = (W m W s ) /q (2) where W m and W s are work functions of the gate and the silicon body, respectively. C ox = ε ox /[R ln (1 + t ox /R)] isthe oxide capacitance per unit area, and ε ox is the permittivity of the oxide. It is difficult to obtain an analytical solution of (1). Different from the traditional IM SG MOSFET, the JLSG MOSFET will be turned on in the partially depleted or near flat-band region, and turned off in the fully depleted region [13]. For simplicity, but without losing any physical insights, following the treatment used in [13], we solve (1) in the subthreshold region and assume that the full depletion approximation holds true. Under the fully depleted condition, the exponential term in (1) can be neglected in the whole region, and (1) is simplified to 2 φ ρ φ ρ ρ + 2 φ z 2 = qn D. (3) ε si B. Threshold Voltage We define G (ρ,z) [φ (ρ,z) V ] /V t. Generally, V GS < V FB, and V GF < 0, the electric potential will be maximum at ρ = 0. If G (0, z) = 1, then G (ρ,z) < 1 will be valid throughout the whole channel. From the boundary conditions, G (0, 0) = G (0, L) = 0 at both the source and drain ends, one can observe that the exponential term in (1) is not significantly small and cannot be neglected at those ends and (3) may be no longer a good approximation. To make (3) a sound approximation, we assume that at the origin (ρ = 0), if the channel is more depleted, and the following formulation holds true: G (0, z) = 2, then one obtains V (z) 2V t = φ (0, z) = V GF + V R + H + (V DS V GF H) sinh (z/) (V GF + H) sinh [(L z) /] sinh (L/). (8) Following the treatment applied in [16] and [17], a constant quasi-fermi potential is assumed and V = V R is used here. The difference between the electric and quasi-fermi potentials, φ (0, z) V, will reach a minimum somewhere along the channel direction. The location of the minimum of φ (0, z) V is the same as that of φ (0, z) due to the constant quasi-fermi potential. Therefore, the location of the minimum, z min, can be obtained by setting d dz [φ (0, z)] z=z min = 0 which leads to z min = (/2) ln (B/A) (9) { A (VGF + H V DS ) (V GF + H) exp ( L/) (10) B (V DS V GF H) + (V GF + H) exp (L/). The threshold voltage in this paper is defined as the voltage applied to the gate to such an extent that the difference of

3 690 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 3, MARCH 2014 Fig. 2. Simulated drain current versus gate bias for different channel lengths. V DS = 0.2 V, t ox = 1.5 nm, R = 5nm,N D = cm 3,andT = 300 K. Left: logarithmic scale. Right: linear scale. Fig. 3. Simulated drain current versus gate bias under different drain bias. L = 20 nm, t ox = 1.5 nm, R = 5nm,N D = cm 3,andT = 300 K. Left: the logarithmic scale. Right: the linear scale. φ (0, z min ) V equals to the negative of twice of the thermal voltage φ (0, z min ) V = 2V t. (11) The whole channel will now be fully depleted and mobile charges can be neglected. This definition is similar to that used in [18], where the V th definition was related with draincurrent characteristics based on mobile charge model, and V th was defined as the voltage applied to the gate to make the mobile charges in the silicon channel negligible. With this definition and (8), we have 2V t = V GF + H + (V DS V GF H) sinh (z min /) (V GF + H) sinh [(L z min ) /]. sinh (L/) (12) If (12) is guaranteed, then the gate voltage, V GS, is the threshold voltage, V th V th = V FB H 2V t sinh (L/) + V DS sinh (z min /) sinh (L/) sinh (z min /) sinh [(L z min )/]. (13) The definition presented in (11) is consistent with draincurrent characteristics. Figs. 2 and 3 show the simulated drain current, I DS, versus gate bias, V GS. Both figures show a turning Fig. 4. Simulated transconductance to the drain current ratio, g m /I DS,versus gate bias. t ox = 1.5 nm, R = 5nm,V DS = 0.2 V, N D = cm 3,and T = 300 K. For the device with L = 25 nm, the half of the maximum value of the ratio g m /I DS corresponds to a gate voltage of 0.80 V, which is the threshold voltage. point for each curve at a gate bias of about 0.80 V. A turning point corresponds to a threshold voltage. V th computed from (13) is 0.78 V for the device with L = 25 nm (other parameters are the same with those described in the caption of Fig. 2), which is very close to the turning point value. Next, we show that the V th obtained with (13) is consistent with that obtained by the transconductance (g m ) extraction method, where V th is defined as the gate voltage at which the ratio of the transconductance to the drain current, g m /I DS, drops to the half of its maximum value [19] [21], and we call this the g m /I DS method. The value of g m /I DS equals to ln(10) divided by subthreshold swing, and the maximum value of g m /I DS of an ideal device is Vt 1 [22]. Fig. 4 shows that the simulated maximum value of the ratio of g m /I DS is 36 V 1, its half value is 18 V 1 and corresponds to a gate voltage of 0.80 V, leading to the V th of 0.80 V. C. SCE and Drain-Induced Barrier Lowering Effect SCE or the variation of V th with respect to L can be obtained from (13) V th L EF DG = E 2 (14) where D 2V t sinh (L/) + V DS sinh (z min /) E sinh (L/) sinh (z min /) sinh [(L z min )/] F 2V t cosh (L/) + V DS z min L cosh ( z min ) [ G 1 cosh L z min L cosh z min ( ] 1 z ) min L cosh L z min. (15) The variation of z min with respect to L can be obtained from (9) z min L = (V [ ] GF + H) exp (L/) exp ( L/). (16) 2 B A Drain-induced barrier lowering (DIBL) effect, the variation of V th with respect to V DS, can be obtained as V th V DS = DM EN E 2 (17)

4 HU et al.: ANALYTICAL MODELS FOR ELECTRIC POTENTIAL, THRESHOLD VOLTAGE, AND SUBTHRESHOLD SWING 691 Fig. 5. Electric potential versus scaled channel position. R = 3 nm, t ox = 1.5 nm, V DS = 0.5 V, V GS = 0.3 V, and N D = cm 3. Solid lines: analytical results. Symbols: simulation results. Fig. 6. Electric potential versus scaled channel position. L = 30 nm, t ox = 1.5 nm, V DS = 0.5 V, V GS = 0.5 V, and N D = cm 3. Solid lines: analytical results. Symbols: simulation results. where M and N are given by { ( M 1 1B 2 + A 1 ) [ ( ) cosh L zmin cosh ( z min ) ] N sinh ( z min ) + V DS ( 1B 2 + A 1 ) ( cosh zmin ) (18). D. Subthreshold Swing The subthreshold swing is defined as S = V GF. (19) log 10 I DS Following the same treatment as in [23] and [24], we assume that the drain-to-source current, I DS, is proportional to exp [φ (ρ,z)/v t ]. Since the electric currents are mainly from the center of the silicon, the electric potential at the location of ρ = 0andz = z min is used to obtain the subthreshold swing; therefore, we have the following formulation: [ ] φ (0, zmin ) 1 S = 2.3V t. (20) V GF Substituting (5) into (20), we obtain the expression for S, (22), which is shown at the bottom of this page, with z min = [ exp (L/) 1 1 exp ( L/) V GF 2 B A III. VERIFICATIONS AND RESULTS ]. (21) We verify our model results by comparing with simulation data obtained using the technology computer-aided design simulation tool, Medici [12]. We use a p+ polysilicon gate. Unless stated, the temperature is T = 300 K, and the silicon body is doped to a concentration of cm 3. Figs. 5 and 6 show the electric potential in the origin, ρ = 0, and the analytical results fit with simulations very well. Lines are model results obtained from (5), whereas symbols are results obtained from simulations. In the simulation process, the reference potential is about V, and therefore V R = V is assumed in the numerical computation. In Fig. 5, the device structure parameters and biases are: R = 3nm,t ox = 1.5 nm, V DS = 0.5 V, V GS = 0.3 V, and N D = cm 3. The black solid line presents the analytical results of the JLSG MOSFET with a gate length of 20 nm, whereas the triangles are for the simulation results. The red solid line demonstrates the model results of the device with a gate length of 40 nm, and the circles are simulation results. In Fig. 6, the device structure parameters and biases are: L = 30 nm, t ox = 1.5 nm, V DS = V GS = 0.5 V, and N D = cm 3. The black and blue solid lines represent the analytical results of the JLSG MOSFET with a silicon body radius of 5 and 3 nm, respectively. The symbols are simulation results. To obtain simulated threshold voltage, we use the same definition as that for the analytical model. In the simulation process, drain and gate biases are applied and the minimum of the potential at the origin (ρ = 0), φ (0, z min ), can be obtained. With the drain bias fixed while varying the gate bias, when (11) is satisfied, the applied gate bias is now the threshold voltage. We call this the φ min method. Fig. 7 shows the threshold voltage versus channel length. The solid and dashed lines are the analytical results, and the symbols are the simulation results. It is noted that a device with a smaller L will have a smaller V th. This is the V th rolloff characteristics, which is the same as for the traditional planar one-gate MOSFET [25]. Fig. 7 also shows that a larger V DS will lead to a smaller V th, and this property is the same as that of the IM MOSFET, which is the so called DIBL effect. V th decreases with the reduction of L and/or with the increase of V DS, which is verified by the simulated drain-current characteristics, as shown in Figs. 2 and 3. It is noted that, when L > 25 nm, the model results match with simulation results quite well. When L < 15 nm, the model results deviate from simulated ones, especially when S = 2.3V t [1 + (V DS V GF H) z min V GF cosh z min + (V GF+H) z min V GF cosh L z min sinh z min sinh L z ] min 1 (22) sinh (L/)

5 692 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 3, MARCH 2014 Fig. 7. Threshold voltage versus channel length. The parameters are: t ox = 2nm,R = 5nm,andN D = cm 3. Solid and dashed lines: analytical results. Symbols: simulation results. Fig. 9. Threshold voltage versus doping level. L = 40 nm, R = 5nm,and V DS = 0.5 V. Solid lines: analytical results. Symbols: simulation results. Fig. 8. DIBL effects versus channel length. The parameters are: t ox = 2nm, R = 5nm,andN D = cm 3. The red solid line with circles is for analytical results, whereas the black/blue lines with squares/triangles are for simulation results. Fig. 10. Threshold voltage versus silicon body radius. t ox = 3 nm, V DS = 0.5 V, and N D = cm 3. Solid lines: analytical results. Symbols: simulation results. V DS is large. The discrepancies may come from: 1) the fully depletion assumption and other assumptions have been used in obtaining the analytical results and 2) the g m /I DS method is generally developed to obtain V th for a small V DS. V th obtained using the g m /I DS method is about 0.03 V larger than that obtained with the φ min method, which might because the φ min method underestimates V th slightly. In this paper, we define DIBL as DIBL = (V th VDS =0.1V V th VDS =0.5 V)/ V DS. (23) Fig. 8 shows DIBL effects. The red solid line with circles is for analytical results, whereas the black/blue lines with squares/triangles are simulation results obtained with the g m /I DS and the φ min methods, respectively. It is noted that, when L < 20 nm, the DIBL effects will be significant, which is consistent with those reported in [1] and [26]. Fig. 9 shows the variation of threshold voltage with respect to doping density. The higher the doping level, the smaller the threshold voltage, which is in accordance with the experimental results obtained in [8]. The black and red solid lines are the results from the device with an oxide thickness of 2 and 4 nm, respectively. One can observe from Fig. 9 that a device with a larger t ox has a smaller V th. This characteristic is the same with that of the JLDG MOSFET obtained in [13, Fig. 3(d)]. Fig. 10 shows the variation of V th with respect to R. Itis known that a larger gate bias is required to turn on a JLSG device with a smaller R. This is different from that of its counterpart IMSG device. For the latter, a device with a smaller R has a smaller V th [14]. The V th varies with R by about 75 mv/nm around R = 5 nm. This property is similar to the V th fluctuation phenomenon of JLDG MOSFET reported in [8]. For the JLDG transistor, a device with a larger width has a smaller V th [8]. Fig. 11 shows the subthreshold swing versus channel length. The red line with circles is for the simulation results, whereas the black line with squares is for the analytical results. We obtain simulated S by extracting from the I V curve in the subthreshold region. It is observed that the S deteriorates with the reduction of L, but, for the devices with L > 30 nm, the values of S are quite satisfactory. It is noted that the analytical results match with the simulation ones fairly well for the devices with L < 25 nm, where the maximum error percentage is less than 1% (0.95%). However, the analytical results deviate from the simulation results for the devices with a short channel (L < 25 nm). When L = 10 nm, the deviation is about 5%. Fig. 12 shows the simulated transfer characteristics with and without the inclusion of quantum mechanical effects (QMEs). Symbols are for the simulations where Fermi statistics is

6 HU et al.: ANALYTICAL MODELS FOR ELECTRIC POTENTIAL, THRESHOLD VOLTAGE, AND SUBTHRESHOLD SWING 693 Fig. 11. Subthreshold swing versus channel length. R = 5nm,t ox = 2nm, V DS = 0.5 V, V GS = 0.73 V, and N D = cm 3. Fig. 12. Simulated transfer characteristics, with or without the inclusion of QMEs. The drain currents are not affected by QMEs in the subthreshold and near threshold regions. used and QMEs are considered, while solid lines are for the simulations where Boltzmann statistics is used and QMEs are not considered. The red line and triangles are for the device with R = 3 nm, whereas the black line and circles are for that with R = 5 nm. QMEs seem not to affect the results at all in the subthreshold and near threshold regions. It is noted that only under large gate bias (>1.1 V), space and field confinements are important, and QMEs need to be considered. IV. DISCUSSION A 2-D PE is solved without the gradual channel approximation. An analytical formulation for electric potential is achieved. With the potential model, analytical expressions for V th and S are obtained. Based on the V th model, analytical expressions for the V th rolloff and the DIBL effect are obtained. Both model and simulation results show that the V th will increase with the reduction of either R or N D. Note that the JL MOSFETs work in the partially depleted region. As R or N D reduces, the total number of electrons from the ionized donors in the channel will also reduce and a larger V GS is now needed to less deplete the channel, so that more electrons are left in the channel to turn on the device. When t ox decreases, V th will increase due to the increase of the oxide capacitance with the reduction of t ox. The total depleted charges in the channel are proportional to the products of the oxide capacitance and (V FB V GS ) and, therefore, to create the same number of depleted charges, a larger V GS is necessary for the device with a larger oxide capacitance or a thinner layer of oxide. From (13), we know that V th is proportional to the negative of H,whereH is given by (6). Numerical computation shows that about half of the variation of the V th results from the variation of H. Thereafter, with the decrease of each of R, t ox,andn D, H will also decrease, leading to the increase of V th. With a fixed channel length, the V th will be smaller for the device with a larger R, which has also been observed in [8] for the JLDG MOSFET. For the device with a long channel, the last term in the V th expression of (13) can be dropped and the V th is now expressed as V L th = V FB qn D R 2 2ε si ln (1 + t ox /R) + ε ox 4ε ox ε si. (24) The above equation is the same as the one obtained in [16, Eq. (17)]. The DIBL effect can be obtained with (17). For the device with the structural parameters used in the caption of Fig. 7, when L = 28 nm, the DIBL is about 20 mv/v, indicating that 1 V increase of the drain bias only leads to 20 mv decreases in the V th. We have noticed that, for a JLSG MOSFET with the typical structural parameters presented in the caption of Fig. 11, when L > 25 nm, the S is in the range mv/decade, suggesting that the JLSG devices with those typical structural parameters are suitable for practical applications. Both analytical and simulated results show that the S deteriorates with the reduction of L and/or with the increase of N D. It is also observed that S increases with the increase of t ox, similar to that of the JLDG MOSFET [13, Fig. 3(d)]. Therefore, to obtain a desired S, one can choose proper combinations of t ox, L, andn D. Simulation results (Fig. 12) suggest that QMEs can be neglected for the devices working in the subthreshold or near-the-threshold region, in which this paper is conducted. When L < 25 nm, the model results for V th,dibl,and S will deviate from the simulation results. Such deviations might be attributed to the assumption of the abrupt potentials at the source and drain ends, as well as the fully depletion approximation and other approximations used in this paper. Second-order effects, such as nonuniform charge distribution, dopants fluctuation, gate misalignment, elliptical cross section area, and so on, have not been considered in the model. As model development is a very complicated issue, especially when the device scales down to the nanometer regime, a more practical model development process is to treat the secondorder effects individually and integrate them into the core model. Therefore, for the device with a very short channel, our model should be used together with the considerations of those second-order effects. One remark should be made here is that, for the purpose of fast circuit simulation, the location of the minimum potential, z min, can be treated as a fitting parameter from 0.3 L to 0.4 L,

7 694 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 3, MARCH 2014 instead of using (9) to obtain it, as it has a little influence on the results. As V DS increases, the value of z min will decrease, which means that the location of minimum potential will move to the source side. Analytical expressions for V th,dibl,ands are obtained. The analytical results are verified against a simulation tool, and good agreements are observed. The explicit and quite simple expressions presented in this paper can facilitate the application of the JLSG MOSFET, and the expressions can be used in integrated circuit designs and simulations. ACKNOWLEDGMENT The authors would like to thank Prof. X. Zhou from Nanyang Technological University, Singapore, for his helpful discussions. They would also like to thank anonymous reviewers kind suggestions leading to the improvement of this paper. REFERENCES [1] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J.-P. 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Razavi, et al., Performance estimation of junctionless multigate transistors, Solid State Electron., vol. 54, pp , Feb Guangxi Hu (M 07) received the Ph.D. degree from Fudan University, Shanghai, China, in He is currently an Associate Professor with the ASIC and System State Key Laboratory in Fudan, Shanghai. His current research interests include semiconductor device physics, multigate MOSFETs, nanoscale MOSFETs modeling, and simulation. Ping Xiang is currently pursuing the M.S. degree with Fudan University, Shanghai, China. Zhihao Ding, photograph and biography not available at the time of publication. Ran Liu received the Ph.D. degree from the Max- Planck-Institute for Solid State Research, Stuttgart, Germany, in He is a Cheung Kong Chair Professor with Fudan University, Shanghai, China.

8 HU et al.: ANALYTICAL MODELS FOR ELECTRIC POTENTIAL, THRESHOLD VOLTAGE, AND SUBTHRESHOLD SWING 695 Lingli Wang (M 99) received the Ph.D. degree from Napier University, Edinburgh, U.K. in He is a Full Professor with the State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai, China. Ting-Ao Tang (M 93 SM 03) received the B.S. degree from the Physics Department, Fudan University, Shanghai, China. He is the Chair of the IEEE SSCS Shanghai Chapter, an IET Fellow, and a Vice Chair of the IET Shanghai Network.