Ground plane fin-shaped field effect transistor (GP- FinFET): A FinFET for low leakage power circuits

Transcription

1 Purdue University Purdue e-pubs Birck and NCN Publications Birck Nanotechnology Center Ground plane fin-shaped field effect transistor (GP- FinFET): A FinFET for low leakage power circuits Mehdi Saremi Tehran University of Medical Sciences Ali Afzali-Kusha Tehran University of Medical Sciences Saeed Mohammadi Birck Nanotechnology Center, Purdue University, saeedm@purdue.edu Follow this and additional works at: Part of the Nanoscience and Nanotechnology Commons Saremi, Mehdi; Afzali-Kusha, Ali; and Mohammadi, Saeed, "Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits" (2012). Birck and NCN Publications. Paper This document has been made available through Purdue e-pubs, a service of the Purdue University Libraries. Please contact epubs@purdue.edu for additional information.

2 Microelectronic Engineering 95 (2012) Contents lists available at SciVerse ScienceDirect Microelectronic Engineering journal homepage: Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits Mehdi Saremi a, Ali Afzali-Kusha a,, Saeed Mohammadi b a Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Tehran, Iran b School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University, West Lafayette, IN 47907, United States article info abstract Article history: Received 24 July 2011 Received in revised form 11 January 2012 Accepted 26 January 2012 Available online 6 February 2012 Keywords: FinFET DIBL Ground plane Process variation RDF SRAM cell In this paper, a fin-shaped field effect transistor (FinFET) structure which uses ground plane concept is proposed and theoretically investigated. The ground plane reduces the coupling of electric field between the source and drain reducing drain-induced barrier lowering (DIBL). To assess the performance of the proposed structure, some device characteristics of the structure have been compared with those of silicon on insulator-finfet (SOI-FinFET) and Bulk-FinFET structures (where the BOX layer covers all the regions except the channel region). In addition, we compare different characteristics of static random access memory (SRAM) cells based on the proposed device structure as well as SOI-FinFET and Bulk-FinFET structures. The characteristics include standby power consumption, and read static noise margin (SNM). Finally, the behavior of the proposed device in the presence of dimensional variations (channel length and thin film thickness variations) and random dopant fluctuation (RDF) are studied and compared with those of the other two structures. Ó 2012 Elsevier B.V. All rights reserved. 1. Introduction For nano-scale metal oxide semiconductor field effect transistor (MOSFET) devices, the undesired effects of short-channel-effects (SCEs) induced by decreased gate control become critically important. To minimize these effects, several double and multi gate structures have been proposed. Among them, fin-shaped field effect transistors (FinFETs) have higher immunity to SCEs, quasiideal subthreshold-swing (SS), high mobility of carriers and high saturation-current [1]. FinFETs have proposed with different device structures including double-gate [2], Pi-gate [3], surrounding-gate [4], gate all-around [5], and omega-gate [6]. The structures can be fabricated on both silicon on insulator (SOI) and bulk-wafers. SOI-FinFETs have shown several advantages over Bulk-FinFETs such as less leakage current, less source-body and drain-body capacitances (C SB and C DB respectively) [7,8], higher saturation current, better subthreshold behaviors [9,10], and less sensitivity to the substrate-doping. On the other hand, Bulk-FinFETs have the advantages of lower cost of fabrication [11,12], lower defect density, low self-heating, and more stability against negativebias-temperature instability (NBTI) [13]. Among important short-channel-effects, drain-induced barrier lowering (DIBL) significantly affects the ability to turn off the transistor by the gate voltage even in these new gate structures. In Corresponding author. Tel.: ; fax: address: afzali@ut.ac.ir (A. Afzali-Kusha). long-channel SOI devices, the subthreshold slope can be increased by increasing the buried oxide (BOX) thickness [14]. In short channel transistors, with increasing the BOX layer thickness, the subthreshold slope decreases [15]. This is due to the enhanced DIBL effect induced by more penetration of the electric field into the BOX layers. The ground plane (GP) technique is one of the methods used to reduce the DIBL effect in short-channel SOI structure [16 18]. It is effective only when the distance between the GP and the drain is small compared to the channel length [15].In[15], two different methods have been used in applying the GP technique to the SOI structure. The methods use the GP in the substrate (GPS) and in the buried-oxide (GPB). The results presented in [15] for the GP structures showed lower leakage power consumption compared to that of the structure without ground planes. In this paper, we propose a FinFET device structure that invokes two ground planes under the source and drain for reducing the DIBL effect. The purpose of this paper is to study a new structure whose difference with the conventional Bulk-FinFET are the use of a BOX layer and buried GP layers. Also, its difference with the SOI-FinFET structure which has the BOX layer is the buried GP layers. In Section 2, we describe the proposed structure and compare its characteristics with those of SOI-FinFET and Bulk-FinFET structures. In Section 3, we study the effects of channel doping density and channel length on device characteristics of the proposed structure. In Section 4, the performance of this structure when used in a real application such as static random access memory (SRAM) cells is investigated. Then, the efficiencies of the structures in the /$ - see front matter Ó 2012 Elsevier B.V. All rights reserved. doi: /j.mee

3 M. Saremi et al. / Microelectronic Engineering 95 (2012) presence of process variations are investigated in Section 5. Finally, the conclusion of the paper is given in Section Proposed GP-FinFET structure In this work, we compare the proposed structure with two conventional FinFET structures (SOI-FinFET and Bulk-FinFET) using 3D simulations. In SOI-FinFET, the channel and substrate are isolated by a BOX layer while in Bulk-FinFET the BOX layer covers all the regions except the channel region (similar to the structures of, e.g., [19,20]). The proposed ground plane FinFET (GP-FinFET) structure is similar to SOI-FinFET structure except for the two ground planes and polysilicon layer inside the BOX layer. The fabrication steps for SOI-MOSFET with two ground planes inside the BOX layer are described in [15] as follows: The structure with ground planes can be realized using the SOIAS technology with the bonded-si- MOX approach. By ion implantation of boron through the silicon film in two masking steps, the formation of p + islands and insulation of these islands with polysilicon after thermal anneal, we can form the ground planes. By self-aligned process with the gate-side spacer, the ground plane can be fabricated after the gate-electrode etching. In order to control the electric field around the junction regions, the ground planes are placed under the source and drain regions. Fig. 1 shows a 3D view of the proposed structure which has the ground planes under source and drain where the vertical distance between source/drain and ground-planes are denoted by X. Unless stated otherwise, the doping densities and the dimensions shown in Fig. 1 may be assumed as those given in Table 1. Also, we assumed a maximum aspect ratio (H Channel /t Si ) of 5 to obtain the larger saturation drain current [21,22]. Note that in the proposed structure, because of short fin length and use of tri-gate structure, the corner effects may influence the electrostatic potential profile between the gates and source/drain more than those of SOI-MOS- FETs studied in [15]. Following the suggestion in [23], in the structure used in this work, we have used tall spacers to reduce the corner effects. Our simulations shows that even without tall spacers, the corner effects are negligible. To achieve about the same onstate performances for Bulk-FinFET and SOI-FinFET, the bulk device should have a lightly doped (or undoped) body [24,25]. For these devices, the threshold voltage control may be performed by the metal gate which has the midgap work function (4.6 ev) [24,25]. Therefore, we used the undoped channel and substrate along with the metal gate which covers three sides of the channel. Fig. 1. 3D view of the proposed structure with ground planes. Table 1 Main parameters of the three structures. Parameter Gate oxide thickness X L Channel H BOX H Channel L GP H GP t Si W GP Source/drain doping Channel doping Gate work function To select a proper ground plane width (W GP ), we simulated the structures with different ground plane widths. The results showed that when the ground plane width equaled to the source/drain width, a better control of the electrostatic potential of the channel (by the gate) was obtained. When the ground plane width was smaller than that of the source/drain, the electrostatic potentials beneath the source/drain were not fully grounded degrading the control of the channel electrostatic potential. The 3D simulations were performed using Sentaurus-Device simulator [26]. The models considered in our simulations included doping dependence model, high field saturation model, and vertical electric field dependence model (Enormal model) for mobility and Shockley Read Hall model for recombination. The density gradient transport model, which solves the quantum potential equations self-consistently with the Poisson and carrier continuity equations, was also used for transport [26]. Finally, note that we have compared the intrinsic structures of the devices, and therefore, did not consider any contact resistance model. The electrostatic potentials of GP-FinFET, SOI-FinFET and Bulk- FinFET are shown in Fig. 2. As the results show, the impacts of the source and drain potentials on the channel electrostatic potential in the GP-FinFET are minimized. This is achieved by grounding the electrostatic potential beneath the source and drain using the ground planes in the proposed structure. Therefore, it is expected that the DIBL is minimized in this structure (see Fig. 5b). The drain current (I D ) versus the drain (V DS ) voltage characteristics at a constant gate overdrive voltage (V GS V th ) for the structures are shown in Fig. 3. In the case of the constant gate overdrive voltage, the drain current of GP-FinFET is larger than those of the other two devices at the high drain voltages. The results show that the saturation region for the GP-FinFET device occurs at a higher drain voltage. The higher drain saturation voltage may be attributed to a smaller velocity saturation effect for a given drain-to-source voltage in the case of GP-FinFET. This is due to the use of the ground planes which lower the strength of the electric field induced by the drain-to-source voltage. The subthreshold characteristics (I D V GS ) for the structures are shown in Fig. 4. The results indicate a larger subthreshold slope (less subthreshold-swing) for the proposed structure compared to those of the others. This leads to a considerable reduction in the leakage current. Therefore, the ratio of the ON current to OFF current for the proposed structure is larger than those of the other two structures. In this work, the threshold voltage (V th ) is the gate voltage at which the drain current is equal to 10 7 W/L [A] where W is the effective width of the gate and L is the channel length [27,28]. DIBL and subthreshold-swing are calculated, respectively, using [15,29,30] DIBL ¼ V thðv DS ¼ 1VÞ V th ðv DS ¼ 0:05 VÞ V DS ð¼ 1VÞ V DS ð¼ 0:05 VÞ Value 2 nm 10 nm 50 nm 100 nm 100 nm 125 nm 20 nm 20 nm 500 nm cm cm ev ð1þ

4 76 M. Saremi et al. / Microelectronic Engineering 95 (2012) Fig. 3. Drain current versus drain voltage (at the constant gate overdrive voltage in three cases) for three structures. The channel length of 50 nm and the fin width of 20 nm were assumed. Fig. 4. Subthreshold drain current versus gate voltage for the three structures when V DS = 1 V and V GS = 1 V. The channel length of 50 nm and the fin width of 20 nm were assumed. Table 2 Device parameters of the structures for parameters given in Table 1. FinFET structure GP Bulk SOI V th (V) DIBL (mv/v) I OFF (na) Ratio of I ON to I OFF (10 5 ) Swing (mv/dec) Fig. 2. Electrostatic potentials at V DS = 1 V and V GS = 1 V for (a) GP-FinFET, (b) SOI- FinFET and (c) Bulk-FinFET at opposite view (cut at y axis) respectively. Subthreshold-swing ¼ log d ln I 1 D ð2þ dv GS In Table 2, some of the important device parameters extracted from the simulation results are presented. These include the threshold voltage, DIBL, leakage current (I OFF ), subthreshold-swing, and ratio of the ON current (at V DS = V GS = 1 V) to OFF current (I ON / I OFF ). As was expected, the ground planes reduce the DIBL effect and increase the threshold voltage for the proposed structure. This leads to the reduction of the leakage current as well as subthreshold-swing. The ratio of the I ON and I OFF is a parameter normally used to show compromise between the speed (higher I ON ) and the leakage (lower I OFF ) characteristics of devices. Modifying structures, one can lower the leakage but the speed (the ON current) may also decrease with the same amount. These structures may not be attractive. In the cases where the ratio is high due to a lower

5 M. Saremi et al. / Microelectronic Engineering 95 (2012) OFF current, one can increase the ON current to desired level by increasing the transistor channel width. The leakage increases with the same rate too keeping the (high) ratio constant. The I ON /I OFF ratio for the proposed structure is much higher than those for the other two devices. In the proposed structure, the ground plane contacts provide the structure with a thin effective BOX reducing the DIBL effect. In addition, the better subthreshold-swing is achieved due to the thick BOX layer (small BOX capacitance) and suppressing the effect of the drain source electrostatic potential on the channel. By this strategy, both better subthreshold-swing and DIBL parameters are obtained. 3. Effects of channel doping density and channel length on device characteristics In this section, we study the device characteristics as a function of the channel doping density and channel length. First, we study the effect of the channel doping density (from cm 3 to cm 3 ) on the device parameters of the structures. Fig. 5a shows the threshold voltages versus the channel doping for the three structures at V DS = 1 V. Similar to conventional devices, the threshold voltage is a strong function of the channel doping density. The threshold voltage is higher for the GP-FinFET due to the existence of the ground planes under the source and drain which reduces the DIBL effect. The slopes of the threshold voltage versus doping for the GP-FinFET and SOI-FinFET devices are smaller due to the added capacitance of the BOX layer. Also, it is observed that Bulk-FinFET structure has the highest sensitivity to the doping among the three structures. Fig. 5b shows DIBL versus the channel doping for the three structures. The results reveal the suppression of DIBL for the GP- FinFET structure. In addition, the DIBL sensitivity of the proposed structure to the channel doping density is much lower than those of the other structures. Similar to conventional devices, for all the three structures increasing the doping density lowers the DIBL effect. In the case of the GP-FinFET structure, since the ground planes suppress the DIBL effect, its dependence on the channel doping density is considerably weakened. Therefore, to minimize random dopant fluctuations, this structure may be used at the lowest channel doping density without being concerned about the DIBL effect. Fig. 5c shows the leakage current obtained at the V GS = 0 V and V DS = 1 V versus the channel doping density. It is obvious from this figure that the leakage current of the proposed structure is noticeably lower than those of the other structures at low doping densities while the difference decreases as the doping density increases. One of the reasons that the leakage current of GP-FinFET approaches those of the other two structures is that the DIBL is suppressed as the doping density increases, and hence, the advantage of the GP-FinFET diminishes. The effect of doping density on the subthreshold-swing is plotted in Fig. 5d which shows a smaller swing for the GP-FinFET in comparison to those of others. As discussed previously, the reason for the smaller subthreshold swing of the proposed structure originates from the thick BOX layer (small BOX capacitance) and suppressing the effect of the drain source electrostatic potential on the channel. The results demonstrate that the increase in the channel doping leads to the swing reduction due to the increase in the gate control over the channel. This behavior has been observed in the results presented in, e.g., [31]. Next, the dependencies of the device parameters on the channel length are considered. Fig. 6a and b shows the threshold voltage and DIBL versus the channel length, respectively. The results indicate that the GP-FinFET device has the lowest DIBL for channel lengths smaller than 60 nm. Since at longer channel lengths the importance of DIBL reduces, the threshold voltages and DIBLs of the three structures approach each other as the channel length Fig. 5. (a) Threshold voltage at V DS = 1 V, (b) DIBL, (c) leakage current, and (d) subthreshold-swing (SS) at V DS = 1 V versus channel doping density (from cm 3 up to cm 3 ) for three structures.

6 78 M. Saremi et al. / Microelectronic Engineering 95 (2012) Fig. 6. (a) Threshold voltage at V DS = 1 V, (b) DIBL, (c) leakage current, (d) ratio of saturation current to leakage current, and (e) subthreshold-swing (SS) at V DS = 1 V versus channel length for three structures. increases. Also, note that the dependencies of the threshold voltage and DIBL on the channel length for the GP-FinFET are the lowest. In addition, since the use of ground planes reduces the influence of the drain voltage on the channel potential, the dependence of DIBL on the channel length also diminishes. Fig. 6c shows the leakage current versus the channel length for the three structures. The difference between the leakage currents of the structures increases as the channel length decreases. This is due to the suppression of the DIBL effect (less threshold voltage reduction) at shorter channel lengths for the GP-FinFET device. Fig. 6d shows the subthresholdswing (SS) versus the channel length. For channel lengths smaller than 60 nm, due to the better gate control of the channel potential in the proposed structure, the smallest SS value is obtained. A small SS leads to a high ratio of the saturation to leakage current. As can be observed from the results, the parameter for the Bulk-FinFET is the worst while the parameters for the GP-FinFET and SOI-FinFET are about the same at larger channel length. The results of Figs. 5 and 6 revealed that the advantage of using the ground planes is appreciated when the DIBL is more significant (low channel doping densities and short channel lengths). In addition, the resulted indicated that generally the dependences of the characteristics to the doping density and channel length were weaker for the case of GP-FinFET. As will be shown in Section 5, these weaker dependences make the device more robust against process variations. In Fig. 7a and b, we show the threshold voltage and DIBL of the three structures for the channel lengths ranging from 15 nm to 50 nm. For these ranges of channel lengths, we have used an aspect ratio of 3 [32,33] and considered the gate oxide thickness, H BOX, H Channel, H GP, t Si, and L GP equal to 1, 40, 30, 10, and 30 nm, respectively. The result shows that with the reduction in channel length, the threshold voltage reduces due to short channel effects. Also, the results show that decreasing the channel length increases the DIBL values for all the three structures which is due to the enhancement in the drain fringing field penetration by scaling. Among the three structures, the impact of the DIBL effect is higher for the Bulk-FinFET structure. In addition, note that while for channel lengths equal or larger than 30 nm, the DIBL values for both GP- FinFET and SOI-FinFET are about the same, for smaller channel lengths the values for GP-FinFET are lower than those for SOI-Fin- FET. This shows that the efficacy of the GP-FinFET structure enhances as the channel length is aggressively scaled. It should be mentioned that since the ground plane length is equal to the fin length for all channel lengths, the scaling does not degrade the effectiveness of proposed structure. Now, we study the effect of the ground plane length on the efficacy of the proposed structure. Fig. 8 shows the results for the dependence of DIBL on this length for three different channel lengths. The figure reveals that DIBL is a weak function of the ground plane length. The maximum variation of DIBL is 14% which is for the ground plane length of 5 nm when the channel is 50 nm (L gp /L g = 0.1). Based on the above results, one may expect that the proposed structure maintain its efficiency for highly scaled devices. Finally, note that as discussed in [17], parasitic capacitances caused by the buried ground plane slightly deteriorate the AC performance while the effect of the lengths of the ground plane on the delay time is not considerably high [17]. Furthermore, by varying the space between the ground plane regions and the source and drain junction edges, one can maximize the unity current gain frequency (f T ) [17].

7 M. Saremi et al. / Microelectronic Engineering 95 (2012) Fig. 9. Schematic of an SRAM cell. Fig. 7. (a) Threshold voltage at V DS = 0.05 V and (b) DIBL versus channel length for three structures for the gate oxide thickness of 1 nm, H BOX = 40 nm, H Channel = 30 nm, t Si = 10 nm, H GP = 10 nm, and L GP = 30 nm. Fig. 8. DIBL versus ground plane length (L GP ) at different channel lengths for the gate oxide thickness of 1 nm, H BOX = 40 nm, H Channel = 30 nm, t Si = 10 nm, and H GP = 10 nm. 4. Characteristics of SRAM cells In this section, we compare different characteristics of SRAM cells based on the three FinFET structures. In Fig. 9, the 6T SRAM cell is shown. The characteristics include standby power consumption, read current, and read static noise margin (SNM). In this section, the results of 3D mixed-mode simulations are presented. For the simulations in a fairly equal condition, we set the read currents of the SRAM cells equal by using different gate work functions for the transistors in each structure. We set 4.6 ev, ev and 4.55 ev for the gate work functions of SOI-FinFET, Bulk-FinFET and GP-FinFET, respectively. The read operation is performed by precharging BL and BLC to V dd (power supply). The read operation starts by setting WL to V dd. Then, one of BL or BLC (for example, BL) begins to discharge. As the difference between BL and BLC voltages reaches a predefined value, e.g., 0.1V dd, then the sense amplifier detects the voltage difference completing the read operation [34]. Due to the voltage division, the VR voltage increases slightly. The current of AR in this case is the read current. As the first step, we investigate the stability of the cell. This parameter may be defined using the static noise margin (SNM) which is the minimum dc noise put at the storage nodes making the cell on the verge of instability [35]. The maximum length of the side of the square encompassed within the butterfly curves is considered as SNM. The read SNMs of the GP-FinFET (154 mv) and Bulk-FinFET (156.7 mv) are approximately equal (approximately 8% smaller than that of SOI-FinFET (170.7 mv)). The results show that the read SNMs of the structures are more or less the same. One of the important parameters for SRAM cells is the standby power. Since in SRAM arrays most of the cells are in the hold state, the standby power is the major component of total power consumptions. In the SRAM cell shown in Fig. 9, AR, PR and NL are the main sources of the subthreshold power in the standby mode. Among the cells, GP-FinFET has the minimum standby power which is about 2.45 nw, due to the higher threshold voltage and less DIBL effect (approximately 4.85 and 1.85 times lower standby power than those of Bulk-FinFET (11.9 nw) and SOI-FinFET (4.53 nw), respectively). If the same gate work function (4.6 ev) is used for all three structures, the read current of GP-FinFET will be approximately 12% and 8% smaller than those of the SOI-FinFET and Bulk-FinFET SRAM cells, respectively. In this case, the read SNM of the GP-Fin- FET SRAM cell is approximately 6% and 4% higher than those of Bulk-FinFET and SOI-FinFET, respectively. Also, the standby power consumption of the cell based on GP-FinFET will be approximately 6.2 and 3.7 times smaller than those of Bulk-FinFET and SOI-Fin- FET, respectively. 5. Process variation study In this section, we study the effects of the variations in channel length, thin film thickness, and random dopant fluctuation (RDF) on the device characteristics. Among different device dimensions, channel length and thin film thickness variations are the main sources of variations in FinFET structures because they are defined lithographically and are susceptible to variations. Other dimensions including the oxide thickness and work function difference semiconductor and metal (DU MS ) are defined by thermal steps

8 80 M. Saremi et al. / Microelectronic Engineering 95 (2012) Table 3 Mean and standard-deviation of threshold voltage for channel length and thin film thickness variations. V th l (V) r (mv) Structure Channel length variation Thin film thickness variation Channel length variation Thin film thickness variation Bulk-FinFET SOI-FinFET GP-FinFET Table 4 Mean and standard-deviation of DIBL for channel length and thin film thickness variations. DIBL l (mv/v) r (mv/v) Structure Channel length variation Thin film thickness variation Channel length variation Thin film thickness variation Bulk-FinFET SOI-FinFET GP-FinFET Table 5 Mean and standard-deviation of leakage current for channel length and thin film thickness variation. Leakage-current l (na) r (na) Structure Channel length variation Thin film thickness variation Channel length variation Channel width variation Bulk-FinFET SOI-FinFET GP-FinFET which can be controlled well [36]. We assume that the channel length and thin film thickness have Gaussian distributions. Since 3D simulations are too time-consuming, we use 500 samples with a mean (l) equal to 50 nm and standard-deviation (r) equal to 3.33 nm for the channel length and a mean equal to 20 nm and standard-deviation equal to 1.33 nm for the thin film thickness. (3r = 0.2l for both channel length and thin film thickness distributions). In Table 3, we listed the values of the means and standarddeviations of the threshold voltages for the structures. Based on the results, r/l of the threshold voltage for the GP-FinFET structure is the lowest. The reason that the variation is lower for GP-FinFET may be attributed to more resistance of this structure against the effects of the source drain electric field in compared to the other two structures. In each structure, the threshold voltage mean is approximately equal under the channel length and thin film thickness variations. However, the standard-deviation under the channel length variation is more than that of the thin film thickness variation. This suggests that the threshold voltages of these structures are more sensitive to the channel length variation. Table 4 lists the means and standard-deviations of DIBL for these structures due to channel length and thin film thickness variations. In each structure, DIBL mean is approximately equal under the channel length and thin film thickness variations. However, the standard-deviation under the channel length variation is more than that of the thin film thickness variation. This suggests that DIBLs of these structures are more sensitive to the channel length variation. The leakage current is exponentially depends on the threshold voltage. Therefore, the leakage current normally follows the lognormal distribution, instead of the normal distribution. Table 5 presents the variations of the leakage current of the three structure due to the channel length and thin film thickness variations. According to Table 5, r/l for the channel length and thin film thickness variations for GP-FinFET are the least. In addition, the standard-deviation of leakage current of GP-FinFET is much less than those of the other two structures. This is due to the fact that Table 6 Means and standard-deviations of threshold voltage, DIBL and leakage current for channel doping variation. Structure Threshold voltage l (V) r (mv) Bulk-FinFET SOI-FinFET GP-FinFET DIBL l (mv/v) r (mv/v) Bulk-FinFET SOI-FinFET GP-FinFET Leakage-current l (na) r (na) Bulk-FinFET SOI-FinFET GP-FinFET in the GP-FinFET structure the vertical control of the electrostatic field is much better than those of the other structures. Now, we study the effect of RDF on the device characteristics of these structures. While the density of dopants versus channel depth follows a Poisson distribution (see, e.g., [37]), a Gaussian distribution is used to model the distribution of the total number of dopants in the channel (see, e.g., [27]). Assuming the channel doping concentration to be cm 3, leads to ten as the average number of channel dopants. We use 500 samples of Gaussian distribution with mean (l) and standard-deviation (r) equal to 10 and 3.33 dopants (3r = l), respectively [27]. Table 6 provides the variations of the threshold voltage, DIBL, and leakage current of the three structures due to RDF. As the results reveal, the ratios of r/l of the threshold voltage, DIBL, and leakage current for the GP-FinFET structure are the lowest among the three structures.

9 M. Saremi et al. / Microelectronic Engineering 95 (2012) Fig. 10. (a) DIBL and (b) subthreshold-swing versus the ratio of the vertical distance of source/drain and ground-planes to the buried oxide thickness (X/H BOX ) for different H BOX and H GP values. The ratios of r/l of the threshold voltage for these three structures are close to each other but the ratios of r/l of the DIBL and leakage current for the GP-FinFET are much less than those of the other two structures. Based on the results presented here, it may be concluded that the GP-FinFET structure is more robust against the dimension variations and channel doping variation when compared to the other two structures. Now, we study the effects of the vertical distance between source/drain and ground-planes (X) on the DIBL and subthreshold swing parameters of the GP-FinFET for different H BOX and H GP values. The variations of these two parameters versus X/H BOX are presented in Fig. 10. For each pair of H GP and H BOX, there is a depth for the ground plane which maximizes the shielding effect by reducing the magnitude and slope of the electrostatic potential in the channel. This is due to the fact that the maximum of the source/drain electrostatic potential occurs at that depth. For the results presented before Fig. 10, we had used X equal to 10 nm (the optimum X was 40 nm) which was the distance used in [15]. It is expected that the previous results for GP-FinFET will improve considerably if they are reproduced using the ground planes positioned at the optimum depth. Finally, we compare Pelgrom et al. [38] and Takeuchi et al. [39] plots for threshold voltages of SOI-FinFET and GP-FinFET in Fig. 11a and b, respectively. Based on these plots which are obtained using 3D simulations, the standard deviation of the threshold voltage can be expressed with the following geometrical dependence: r Vth ¼ A V pffiffiffiffiffiffiffi th WL ð3þ Fig. 11. (a) Pelgrom plot and (b) Takeuchi plot of the standard deviation of threshold voltages for SOI-FinFET and GP-FinFET. rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi T r INV ðv th þ V 0 Þ V th ¼ B Vth LW Here, W is the channel width, L is the channel length, r V th is the standard deviation of the threshold voltage, A Vth is the slope of Pelgrom plot, T INV is the electrical gate dielectric thickness, V 0 is potential difference between the Fermi-level and the band edge in inversion and B Vth is the slope of Takeuchi plot. Note that A Vth is independent of the device geometry and representative for a given technology [38]. Fig. 11a and b indicates, the A Vth coefficients are equal to 3.2 and 2.05 mv lm and the B V th coefficients are equal to 2.1 and 1.31 mv lmv 0.5 nm 0.5 for SOI-FinFET and GP-FinFET, respectively. Therefore, the threshold voltage variation for GP-Fin- FET is less than that of SOI-FinFET. Furthermore, the Pelgrom and Takeuchi plots for GP-FinFET are more linear than those of SOI-Fin- FET. Note that while the Takeuchi plots for two structures are approximately linear, the nonlinearity of the Pelgrom plot for SOI-FinFET is more than that of GP-FinFET. When the channel doping non-uniformity is insignificant and the only reason for the random fluctuation of the threshold voltage is RDF (which is the case for our structures), B Vth should be constant [40]. In the case of the Pelgrom plot, A Vth depends on the threshold voltage whose variation is more in the case of SOI-FinFET when compared to GP-FinFET counterpart (see Table 6). Therefore, more nonlinearity of the Pelgrom plot for SOI-FinFET is observed. 6. Summary and conclusion In this work, we introduced a FinFET structure called GP-FinFET that used the ground plane technique for reducing the DIBL effect. To evaluate the performance of the structure, we compared the GP- FinFET to SOI-FinFET and Bulk-FinFET. The comparison showed ð4þ

10 82 M. Saremi et al. / Microelectronic Engineering 95 (2012) that the proposed structure reduced the DIBL and leakage current, increased the ratio of the saturation current to leakage current, and improved the subthreshold-swing. The results also indicated that the improvements increased as the channel length decreased. Also, the performance was studied in terms of the channel doping density and the channel length. Next, we compared the read characteristics of the SRAM cells based on GP-FinFET, SOI-FinFET, and Bulk-FinFET. The comparison revealed a lower standby power for the SRAM cell based on GP-FinFET. The proposed structure may be used for implementing digital circuits where the static power is of prime concern while the speed is of less importance. These include the circuits which are used in many devices fabricated for mobile applications. These devices operate with batteries which have limited reservoirs of energy. Finally, we studied the effects of process variations, including channel length, thin film thickness variations and RDF on the characteristics of the structures. The GP-FinFET structure showed less variability of characteristics in comparison to Bulk-FinFET and SOI-FinFET. This attributed to a better vertical electrostatic potential control in this structure. References [1] J. Kedzierski et al., in: IEDM Tech. Dig., 2001, pp [2] S. Xiong, J. Bokor, IEEE Trans. Electron Dev. 50 (2003) [3] J.T. Park, J.P. Colinge, C.H. Diaz, IEEE Electron Dev. Lett. 22 (2001) [4] A. Kranti, Rashmi, S. Halder, R.S. Gupta, Solid State Electron. 46 (2002) [5] N. Singh, A. Agarwal, L.K. Bera, R. Kumar, G.Q. Lo, B. Narayanan, D.L. Kwong, Electron Lett. 41 (2005) [6] F.L. Yang et al., in: IEDM Tech. Dig., 2002, pp [7] T. Park et al., in: Symp. on VLSI Tech. Dig., 2003, pp [8] T. Park et al., in: IEDM Tech. Dig., 2003, pp [9] Y. Bin, C. Leland, S. Ahmed, W. Haihong, S. Bell, Y. Chih-Yuh, et al., in: IEDM Digest of Technical Papers, 2002, pp [10] A. Bansal, S. Mukhopadhyay, K. Roy, IEEE Trans. Electron Dev. 54 (2007) [11] T.S. Park, S. Choi, D.-H. Lee, U.-I. Chung, J.T. Moon, E. Yoon, et al., Solid-State Electron. 49 (2005) [12] T.H. Hsu, T. Lue, Y.-C. King, J.-Y. Hsieh, E.-K. Lai, K.-Y. Hsieh, et al., IEEE Electron Dev. Lett. 28 (2007) [13] H. Lee, C.-H. Lee, D. Park, Y.-K. Choi, IEEE Electron Dev. Lett. 26 (2005) [14] T. Numata, S. Takagi, IEEE Trans. Electron Dev. 51 (2004) [15] M.J. Kumar, M. Siva, IEEE Trans. Electron Dev. 55 (2008) [16] W. Xiong, J.P. Colinge, Electron Lett. 35 (1999) [17] S. Yanagi, A. Nakakubo, Y. Omura, IEEE Electron Dev. Lett. 22 (2001) [18] W. Xiong, K. Ramkumar, S.J. Jang, J.T. Park, J.P. Colinge, in: Proc. IEEE Int. SOI Conf., 2002, pp [19] J. Liu et al., in: 10th IEEE Int. Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2010, pp [20] J. Park et al., in: IEDM Tech. Dig., 2006, pp [21] B. Yu et al., in: IEDM Tech. Dig., 2002, pp [22] H. Ananthan, K. Roy, IEEE Trans. Electron Dev. 52 (2006) [23] H. Zhao, Y. Yeo, S.C. Rustagi, G.S. Samudra, IEEE Trans. Electron Dev. 55 (2008) [24] M. Poljak, V. Jovanović, T. Suligoj, in: The 14th IEEE Mediterranean Electrotechnical Conference, 2008, pp [25] M. Poljak, V. Jovanović, T. Suligoj, Microelectron. Eng. 86 (2009) [26] Sentaurus-Device Simulator from Synopsys Inc., Version Z [27] Yiming Li, Chih-Hong Hwang, Hui-Wen Cheng, Microelectron. Eng. 86 (2009) [28] Z.X. Yan, M.J. Deen, in: IEE Proceedings G Circuits, Devices and Systems, 1991, pp [29] R.R. Troutman, IEEE J. Solid-State Circ. SC-14 (1979) [30] M.J. Deen, Z.X. Yan, IEEE Trans. Electron Dev. 39 (1992) [31] D.S. Havaldar et al., IEEE Trans. Electron Dev. 53 (2006) [32] M. Shrivastava et al., IEEE Trans. Electron Dev. 58 (2011) [33] V.P. Hu et al., IEEE Trans. Electron Dev. 58 (2011) [34] A. Chandrakasan, W.J. Bowhill, F. Fox, in: Piscataway, IEEE Press, NJ, [35] E. Seevinck, R. List, J. Lohstroh, IEEE JSSC SC-22 (1987) [36] H. Ananthan, K. Roy, IEEE Trans. Electron Dev. 53 (2006) [37] A. Asenov et al., in: IEDM Tech. Dig., 1999, pp [38] M.J.M. Pelgrom, A.C.J. Duinmaijer, A.P.G. Welbers, IEEE J. Solid-State Circ. 24 (1989) [39] K. Takeuchi, T. Fukai, T. Tsunomura, A.T. Putra, A. Nishida, S. Kamohara, T. Hiramoto, in: IEDM Tech. Dig., 2007, pp [40] K. Takeuchi et al., in: International Conference on Simulation of Semiconductor Processes and Devices, 2009, pp