Advanced Millisecond Annealing Technologies and Its Applications and Concerns on Advanced Logic LSI fabrication processes

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1 Materials Science Forum Online: ISSN: , Vols , pp doi: / Trans Tech Publications, Switzerland Advanced Millisecond Annealing Technologies and Its Applications and Concerns on Advanced Logic LSI fabrication processes Masataka Kase 1, a, Tomonari Yamamoto 2,b and Tomohiro Kubo 1,c 1 Fujitsu Limited, 50, Fuchigami, Akiruno, Tokyo, , Japan 2 Fujitsu Laboratories Limited, 50, Fuchigami, Akiruno, Tokyo, , Japan a kase.masataka@jp.fujitsu.com, b yamamoto.tomonari@jp.fujitsu.com., c kubo.tomohiro@jp.fujitsu.com Keywords: Millisecond annealing, frtp, Laser spike annealing, flash lamp annealing, CMOS device, transistor, SiGe Abstract. The recent progress of advanced millisecond annealing (MSA) technology is discussed for the application to the advanced logic LSI fabrication processes. The combination with conventional spike annealing and MSA is proving practical to reduce the parasitic resistance and control the dopant diffusion. The characterization result of advanced 45 nm generation devices including the channel straining technology using embedded SiGe epitaxial growth is described with the arrangements of process flow and annealing steps. MSA has a principle problem of the annealing temperature variation depending on the optical properties of materials on the wafer surface because the annealing process time is similar to the heat transfer time. In the device scale, the variation of temperature is examined as the exact temperature with newly proposed evaluating methods used for the first time in this industry. Introduction Millisecond annealing (MSA) has been developed to achieve high activation and less diffusion of dopants, therefore its primary application might be the enhancement of dopant activation within the polysilicon gate without any diffusion of the dopant placed in the bulk region. [1] Also, the research will be highlighted into the approaches of engineering dopant profile underneath the gate structure such as the extension and halo. The MSA-only approach has been proposed that the dopant placement is fixed ideally by just ion implant conditions. However, there might be some issues with process integration, so the production-worthy device characteristics have not been demonstrated sufficiently. However, the combination with conventional spike rapid thermal annealing (s-rta) and MSA seems to show more practical results presently. [2,3] The design of an integration scheme using such a process sequence is quite important to extract the performance of transistor. Four MSA techniques have been released as follows; dynamic scanning annealing (DSA), laser spike annealing (LSA), flash lamp annealing (FLA) and flash-assist RTP (frtp TM ). [2,4-6] These energy sources are solid state laser, CO 2 laser, Xe arc flash lamp and Ar arc flash lamp respectively. The dependence of photon absorption with the materials covering the surface of the wafer during the fabrication process is strongly dependent on what kind of pattern, process sequence and substrate type. Actually, the difficulty to determine the exact temperature variation in such a short time and small dimension as the scale of advanced devices has been underplayed. Because the annealing temperature is high to be near melting point of Si and the short annealing time makes it difficult to identify the origin of wafer breakage, the wafer bowing and breakage are important concerns. The device structure and its details influence the probability of such failures, so the countermeasures on the device side can be quite effective comparable to the improvements on the equipment side. But, there have been few publications where these phenomena are shown because of the sensitivity of the manufacturing and commercial competition of equipment and device fabrication. This paper describes the recent progress on the device integration scheme of MSA into the advanced logic LSI fabrication process and analysis of device performance. The examination of the All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (# , Pennsylvania State University, University Park, USA-19/09/16,07:56:34)

2 326 Rapid Thermal Processing and beyond: Applications in Semiconductor Processing local temperature variation of MSA is shown as the exact temperature with newly proposed evaluation methods for the first time in this industry. Figure 1: Key features of 45 nm node high-performance and low-leakage CMOS devices. Junction Profile Engineering and Device Performance of 45 nm node CMOS Technology Device Structure and Process Sequence. The effectiveness of MSA for the performance improvement of CMOS devices with embedded SiGe in the pmos regions is quite important because the thermal endurance of SiGe depends on the thermal cycle and process sequence. We also clarify how MSA affects the dopant profiles and device characteristics. The key features of the 45 nm node high-performance CMOS structure are shown in Fig. 1. The LSA has been used as MSA in this experiment. Multiple stressors including the ΣSiGe technique [7] are used to enhance mobility. In our approach, MSA should be implemented just after the SDE and halo implant called as step 1, and deep source-drain (SD) implant called as step 2. The LSA on step 1 forms an effective nmos halo and low-resistance pmos SDE, and step 2 forms a low-resistance nmos deep SD. Process results. Figure 2 (a) shows the secondary ion mass spectroscopy (SIMS) profiles of boron concentration annealed by spike-rta with LSA and without LSA with fluorine co-implants, and (b) shows the fluorine concentration profiles. The results indicate that a higher concentration in the boron plateau region, which suggests the improved activation level of boron and the suppression of transient Figure 2: SIMS profiles of boron (a) and fluorine (b) concentrations for samples annealed by spike-rta with and without LSA. SIMS profiles of the boron (c) concentration for samples annealed by spike-rta with and without LSA for no co-implants are also shown.

3 Materials Science Forum Vols enhanced diffusion (TED), can be obtained by using LSA combined with a fluorine co-implant. The junction profiles of boron and fluorine are not sensitive to LSA temperature changes within a significantly wide temperature range. Figure 2 (c) indicates that the phenomena could not be obtained without fluorine. Figure 3 shows the SDE sheet resistance of pmos transistors fabricated using LSA adopted at process steps 1 and step 2 respectively. LSA after SDE implant and F co-implant appears to be interacting B with F and residual defects effectively, so the TED would be suppressed as shown in Fig. 2. Compared with the sample without LSA, a 60 % lower R s is achieved due to the active B concentration in the plateau region of the SIMS profile has increased more than twice. In case of step 2, the ΣSiGe and other processes can decrease dramatically the amount of remaining fluorine, so the sheet resistance is not lowered effectively. The amount of fluorine is quite important in determining when the Boron diffusion occurs, so the MSA has strong merit as the defect recovery without fluorine diffusion. Figure 4 shows cross sectional transmission electron microscope (XTEM) images of a pmos (a) after SDE and halo implantation, (b) after LSA, and (c) after s-rta. Figure 4 (a) indicates clearly that some damage in the Si substrate is induced by ion implantation. In particular, the Figure 3: SDE sheet resistance of pmos fabricated using LSA step 1 only (open squares), LSA step 2 only (open triangles), and without LSA (solid circles). halo implant is the origin of the dark contrast at the depth ranging from 10 nm to 60 nm, because the projected range of the halo implant would be similar to these shown in Fig. 4 (a). Also there is the surface amorphized layer which is formed by the low energy SDE implant. As seen as dark dots at the depth of 60 nm on the XTEM image of Fig. 4 (b), some residual defects still remained after LSA. Also, we can be observed some dark contrast placed near the Si surface region. These might be caused from the residual damage of ultra low energy SDE implant. However theses are clearly diminished after s-rta and ΣSiGe growth, especially the channel region underneath the gate dielectric is quite clear. Figure 5 shows off-state junction leakage currents of pmos fabricated at various LSA temperatures. The ΣSiGe step was not been adopted in this sample. The junction leakage current is not sensitive to LSA temperatures for a wide temperature range, so higher temperature is not necessary in this approach. At least, the LSA process has a wide range of process temperature to be utilized it without increase of leakage current or defect generation Figure 4: Cross-sectional TEM images of pmos for as-implanted (a), after LSA step 1 with the optimum peak temperature (shown in Fig. 3) (b), and after s-rta (c). Samples were fabricated with the process shown in Fig. 1.

4 328 Rapid Thermal Processing and beyond: Applications in Semiconductor Processing. Device results. Figure 6 shows the relation between L min and I on at a constant I off for pmos with and without LSA and with and without fluorine co-implants. L min means that the gate length of transistor can be operated in the condition of threshold voltage, V th, V th = 0 V. Each split has two or three SDE implantation doses in order to investigate the SDE dose dependence of L min and I on. We can clearly see that with a fluorine co-implant, step 1 can raise the L min -I on trade-off line in the increasing I on direction. Figure 7 shows the LSA temperature dependence of the SDE sheet resistance in pmos fabricated using our proposed LSA scheme with a fluorine co-implant. Our technique results in a dramatic reduction in SDE sheet resistance, and its sensitivity to LSA temperature is very low within a temperature range of over 100 C giving a wide process window. Figure 5: Off-state junction leakage currents of pmos fabricated at various LSA temperatures. ΣSiGe was not performed. Figure 6: L min -I on trade-off lines of pmos devices fabricated with and without LSA (open and solid) and with and without F co-implants (squares and circles). Figure 7: LSA temperature dependence of SDE sheet resistance for pmos fabricated with our proposed approach. Quantitative observation of sub-100 nm range local temperature fluctuation in MSA Local temperature fluctuation of MSA. In the case of annealing techniques based on light irradiation heating, which includes conventional RTA and ms annealing, the emissivity non-uniformity within a die or a patterned wafer should cause local temperature variations in principle. The temperature fluctuation within a wafer in RTA that originates from the emissivity

5 Materials Science Forum Vols non-uniformity has already been investigated [8]. It was found that the emissivity fluctuation within a die results in the variation of the advanced device characteristic annealed by the lamp type spike RTA equipment [9]. The annealing time in MSA is much shorter than s-rta, so the lateral thermal diffusion length in MSA is about 100 µm, which is much shorter than s-rta which is about 5 mm. It becomes more critical for the successful manufacturing of advance devices to suppress the fluctuation of the device characteristic. It is necessary for the manufacture of LSI with MSA to evaluate and suppress the temperature variation that depends on micro emissivity non-uniformity in MSA. We succeeded in the measurement of a device-scaled temperature Figure 8: Test pattern structure (a) the lattice and emissivity non-uniformity in the area of pattern and active area for TW measurement. (b) 100 µm or less by using thermal wave (TW) three types of lattice structures technique. Additionally we studied the influence of the aspect ratio, density and structure of patterns upon emissivity non-uniformity. MSA and sample preparation. FLA was performed with the condition of irradiation intensity ranging from 23 to 31 J/cm 2. The peak temperature of the surface of wafers is estimated to reach values ranging from 1000 to 1300 ºC. We prepared the various samples with the several depths of trench and several density of lattice patterns. The depth of trenches ranges from 150 to 400 nm as shown in Fig. 8. The isolated active areas, which mean flat silicon areas to be the TW measurement point, were arranged in the lattice pattern field. We also prepared three types of device structures; (1) trench structure, has only trench structures by Si etching, (2) Shallow Trench Isolation (STI) structure has the trench structure filled with oxide, and (3) Transistor structure has the poly-si gate on the Si islands in lattice patterns. The interval of the lattice pattern was varied to investigate the emissivity variation. Thermal wave measurement. The TW method was used to clarify the emissivity and temperature distribution locally on the device scale. The diameters of pump and probe laser spots are about 1 µm, however the measurement spatial resolution reaches at about 10 µm, because there is propagation of the thermal waves in the silicon substrate. The measurement area has been determined to be of a size of 10 µm square. The amount of damage induced by ion implantation just after ion implantation has been measured by TW method often in the past. However, we measured the amount of the residual ion-implanted damage recovered by FLA and evaluated the correlation between the TW signal and its dependence on residual damage and FLA power, which is relative to the temperature of the surface of wafers. We successfully optimized the ion implantation condition to gain the simple correlation that the TW signal decreases monotonously when the FLA power increases. The temperature measurement during MSA is quite important issue to stabilize the annealing temperature, in particular the FLA has not had a practical temperature measurement method yet. To clarify the temperature difference, we use the relative emissivity concept comparing with the blanket wafer and several patterned wafers. The absorbed irradiation power, P is defined as the product of the irradiation power Q with the absorptivity, which is equal to the emissivity,, as follows, P = Q. (1)

6 330 Rapid Thermal Processing and beyond: Applications in Semiconductor Processing This relationship is available in each different sample such as the blanket wafer and patterned wafer. The implanted damage was annealed by the absorbed irradiation power, therefore the residual damage after FLA is quantified by thermal wave and the examination of the dependency of irradiation power gives the relation between the Q and thermawave signals. When the patterned sample annealed at the irradiation power Q pattern has the same thermawave signal as the blanket wafer annealed at the Q blanket, the following relation is achieved due to the same absorbed power is adopted, blanket Q blanket = pattern Q pattern, (2) where the emissivity, of blanket and pattern wafer are blanket and pattern, respectively. As a result, the relative emissivity relative is defined as follows, pattern Qblanket relatve = =. (3) blanket Qpattern Figure 9 shows the distribution of relative emissivity based on TW measurements of the samples with various trench densities which are increased in alphabetical order from B to F blocks and 45 nm node SRAM patterns were formed in the A block [10]. The relative emissivity has changed greatly in blocks B and D. The pitch difference of block D is 140 µm and almost the same as the lateral thermal diffusion length in FLA. The relative emissivity of the STI structure is larger than the trench structure because a part of the surface of the pattern is covered with the oxide which has a reflectivity less than silicon. The poly-si gate causes an increase of the relative emissivity in the transistor structure. The increase of the relative emissivity occurs due to the effect of extra absorption due to multiple reflections by the poly-si gate structure compared to the trench structure. (a) (b) Figure 9: Distribution of relative emissivity calculated from TW measurement. The square, circle and triangle lines are showing the sample structure of trench, transistor, STI, respectively. Local temperature variation. The temperature variation depending on emissivity variation is described by the following equation [11], 2-1 T peak = ( Tsurface_ave -Tsub ), (4) ave where T peak is the difference in temperature between two areas of different emissivity, T surface_ave and T sub are the average temperatures of two different areas on the surface and the substrate temperature, and 1, 2, ave are the emissivity in one area, the other area and average emissivity of both respectively. Therefore the peak temperature difference can be extracted from the relative emissivity. Figure 10 shows the relation between the temperature difference of a pattern wafer to a blanket wafer when it is assumed that T sub and T surface_ave by FLA are 450 ºC and 1200 ºC respectively. In the case of the transistor structure the range of temperature variation depending on the emissivity

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