Evaluation of the plasmaless gaseous etching process

Transcription

1 Solid State Phenomena Vol. 134 (28) pp 7-1 Online available since 27/Nov/2 at (28) Trans Tech Publications, Switzerland doi:1.428/ Evaluation of the plasmaless gaseous etching process Yoshiya Hagimoto 1, a, Hajime Ugajin 1, Daisuke Miyakoshi 1, Hayato Iwamoto 1, Yusuke Muraki 2 and Takehiko Orii 2 1 Sony Corporation, Asahi-cho, Atsugi-shi, Kanagawa, Japan 2 Tokyo Electron Kyushu LTD, matsushima-cho, miyagi-gun, miyagi, Japan a Yoshiya.Hagimoto@jp.sony.com Keywords: plasmaless gaseous etching,,, divot Introduction The precise control of the etching of various films on device surfaces is becoming increasingly important because slight changes in device structures can cause serious deterioration of their electrical properties. For example, a depression that is called a divot, in the CVD oxide of a shallow trench isolation () results in increased leakage current, especially in advanced devices. The cause of the divot formation is considered to be the successive etching of the CVD oxide in the with hydrofluoric-based chemicals. The purpose of this successive etching is to remove the oxide on the device. The CVD oxide film has a poor structure, so the wet etch rate of the CVD oxide is greater than that of the thermal oxide. In this paper, we report a plasmaless, gaseous etching process technology that achieves a larger reduction of the etch rate of the CVD oxide than that of the conventional wet etching process. We discuss the mechanism of the reaction of this process and apply this technology to the formation process. Experimental For this evaluation of the plasmaless gaseous etching process, we used a Certas TM chamber that was developed by Tokyo Electron Limited [1]. Hereafter, we call this process (chemical oxide removal). A schematic of the is presented in Figure 1. This system comprises a first treatment chamber and a second treatment chamber. The first is a chemical treatment chamber in which the substrate is exposed to a gaseous chemistry, such as /, under controlled conditions that include surface temperature and gas pressure. The second is a heat treatment chamber for sublimating by-products of the reaction in the first treatment chamber. Result and Discussion Basic process performance of We have checked the basic process performance of the. First, we have compared the surface roughness of silicon substrate surface after the process with that after the conventional D process by using the AFM (Atomic Force Microscopy). In this evaluation, bare silicon substrates were processed by the or D. The etched amount for the thermal oxide was the same for both processes. As shown in Figure 2, surface roughness (Ra) is almost the same among three conditions including the process, the conventional D process, and no treatment, which indicates that there was no damage to the silicon substrate surface by the process. Next, we have investigated the etching performance of the for various films. Figure 3 shows the etched amount of various films as a function of the process time. The etched amount of the CVD oxide, such as the plasma-teos (tetra ethyl ortho silicate), and the HDP (high density plasma) is smaller than that of All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of TTP, (ID: , Pennsylvania State University, University Park, United States of America-3/6/14,2:3:5)

2 8 Ultra Clean Processing of Semiconductor Surfaces VIII the thermal oxide. In the conventional wet process, on the other hand, the etch rate of the CVD oxide, especially in the plasma-teos, is much larger than that of the thermal oxide. We suppose that the etching mechanism of the is quite different from that of the wet etching process. Etching mechanism of the Figure 4 shows the FT-IR (Fourier Transform Infrared Spectroscopy) spectrum of the plasma-teos and thermal oxide after the first-chamber treatment of the. We observed several peaks characteristic to the (NH 4 ) 2 SiF 6 for the plasma-teos and thermal oxide. The ratio of nitrogen, silicon, and fluorine obtained with the XPS (X-ray Photoelectron Spectroscopy) measurements (Figure 5) is almost consistent with that of (NH 4 ) 2 SiF 6, supporting the idea that a (NH 4 ) 2 SiF 6 layer was formed on both surfaces. Next, we discuss the etching mechanism of the. First, and are adsorbed on the surface, and the following reactions occur. SiO SiF 4 + 2H 2 O SiO SiF 4 + 2H 2 O + 4 SiF (NH 4 ) 2 SiF 6 With increasing thickness of the (NH 4 ) 2 SiF 6 layer on surfaces, and should diffuse into the (NH 4 ) 2 SiF 6 layer and reach to the oxide surface, then the next reaction starts. In this way, both a diffusion process and the reaction process take place in the etching reaction of the. As the etching reaction proceeds, the diffusion process becomes the rate-determining element of the total etching reaction. That is why the etched amount in the process becomes almost saturated as the process time increases, which is analogical to the thermal oxide growth model (Deal-Grove model). The etching mechanism mentioned earlier can be applicable irrespective of the kinds of oxide; therefore, the etch rate of an oxide with poor structure like that of the CVD oxide is reduced in the (Figure 6). In the wet etching process, on the other hand, by-products of the etching reaction can easily dissolve in chemicals and be removed from the oxide surface, therefore, the etch rates of films with poor structure, such as the CVD oxide, are much larger than that of the thermal oxide. We suppose the subtle difference in the etch rates of different kinds of films in the can be attributed to the difference in the quality of accumulated (NH 4 ) 2 SiF 6 layers. The CVD oxides imply many impurities, and those impurities may interfere with the diffusion of or. The slight peak shift around 785cm -1 (expanded in the inset of Figure 4) may suggest a difference in the quality of by-products of the thermal oxide and those of plasma-teos. Application of the to the process Figure 7 shows a schematic of the divot formation, a shape abnormality generated above the trench upper edge by the successive etching process for the removal of the oxide on the device surface. We have substituted the for the conventional wet etching process in the following description, including the sacrificed oxide removal and the gate oxide removal for the multi oxide formation, and compared the shape formed when using the D with that when using the. Figure 8 shows the etched amount of the HDP in the region for the D and that for the. In this experiment, the etched amount for the thermal oxide was the same for both the D and the process. The total etched thickness was about 3 nm for the thermal oxide for both processes. As shown in Figure 8, we found that the etched amount of the in the is smaller than that in the D, and this is in good agreement with the result of etching blanket films. Figure 9 is AFM images of the obtained with the two processes. We found that it was possible to suppress the divot formation by

3 Solid State Phenomena Vol substituting the etching process for that of the D. TEM images also suggest that the shape is remarkably improved by using the process (Figure 1). Summary We evaluated the plasmaless gaseous etching process and found that by using the, we could reduce the etch rate of the CVD oxide more than when using the conventional wet etching process. We consider these phenomena can be attributed to the etching mechanism of the that is quite different from that of wet etching. Furthermore, our results revealed that the shape was improved by substituting the for the conventional wet etching process. We believe that this technology will be a promising etching technique for advanced devices. References [1] US patent : US (A1) The first f treatment chamber Surface Micro Etch / adsorption onto wafer surface Wafer temp. 2~4 NH 3 Wafer By-product The second treatment chamber Heat up to 1~2 To Evaporate By-product from Wafer Surface ( w/ N 2 Gas ) N 2 H 2 O SiF 4 Wafer SiF H 2 N 4 2 SiF 4 Heater Surface roughness Ra (nm) Figure 1: Schematic of the. No treatment D Etched amount (nm) LP- TEOS P- TEOS HDP Process time (min) No treatment D Figure 2: Surface roughness of silicon substrate after the or D processes Figure 3: The etched amount of various films treated by the as a function of process time

4 Ultra Clean Processing of Semiconductor Surfaces VIII.12 Absorbance Th-Ox 25 2 Frequency (cm-1) Absorbance Figure 4: FT-IR Spectrum for the reacted layers on the thermal oxide and the plasma-teos measurements. The slight peak shift around 785cm -1 (expanded in the inset) may suggest a difference in the quality of by-products of the thermal oxide and those of plasma-teos Frequency (cm-1) 7 Th-Ox Photoelectron Binding Energy (ev) Ratio (%) Binding Energy (ev) Ratio (%) Estimation N(1s) (NH4)2SiF6 F(1s) (NH4)2SiF6 Si(2p) (NH4)2SiF6 Figure 5: The ratios of nitrogen, fluorine, and silicon on the reacted layer of the thermal oxide and plasma-teos obtained with XPS measurements sacrificed oxide for well implantations Diffusion Adsorption Diffusion (NH 4 ) 2 SiF 6 layer Surface reaction ThOx,TEOS,HDP Figure 6: Schematic of the reaction model Etched amount Si sub 1 st Gate oxide 2 nd Gate oxide Si sub Sacrificed oxide removal Etched amount (nm) Si substrate Si sub Si sub Gate oxide removal for multi oxides formation Figure 7: Schematic diagram of the divot formation D Figure 8: The etched amount of D D Figure 1: TEM images of the shape Figure 9: AFM images of the shape

5 Ultra Clean Processing of Semiconductor Surfaces VIII 1.428/ Evaluation of the Plasmaless Gaseous Etching Process 1.428/