Electrical Characterization of PiN Diodes with p + layer Selectively Grown by VLS Transport

Transcription

1 Materials Science Forum Online: ISSN: , Vols , pp doi: / Trans Tech Publications, Switzerland Electrical Characterization of PiN Diodes with p + layer Selectively Grown by VLS Transport Nicolas Thierry-Jebali 1, a, Mihai Lazar 1, b, Arthur Vo-Ha 2, c, Davy Carole 2, d, Véronique Soulière 2, e, Farah Laariedh 1,f, Jawad ul Hassan 3, g, Anne Henry 3, h, Erik Janzén 3, i, Dominique Planson 1, j, Gabriel Ferro 2, k, Christian Brylinski 2, l and Pierre Brosselard 1, m 1 Université de Lyon, INSA de Lyon, Laboratoire Ampère, UMR-CNRS 5005, 21 Avenue Jean Capelle F Villeurbanne Cedex, France 2 Université de Lyon, Université Claude Bernard Lyon 1, CNRS, UMR 5615, 43 Bd du 11 Novembre 1918, F Villeurbanne Cedex, France 3 Department of Physics, Chemistry and Biology, Linköping University, SE Linköping, Sweden a nicolas.thierry-jebali@insa-lyon.fr, b mihai.lazar@insa-lyon.fr, c arthur.vo-ha@univ-lyon1.fr, d davy.carole@univ-lyon1.fr, e veronique.souliere@univ-lyon1.fr, f farah.laariedh@insa-lyon.fr, g jawul@ifm.liu.se, h anhen@ifm.liu.se, i erija@ifm.liu.se, j dominique.planson@insa-lyon.fr, k gabriel.ferro@univ-lyon1.fr, l christian.brylinski@univ-lyon1.fr, m pierre.brosselard@insa-lyon.fr Keywords: PiN diodes, VLS, Localized Epitaxy, Electrical Characterization Abstract. This paper deals with electrical characterization of PiN diodes fabricated on an 8 offaxis 4H-SiC with a p ++ localized epitaxial area grown by Vapour-Liquid-Solid (VLS) transport. It provides for the first time evidence that a high quality p-n junction can be achieved by using this technique followed by a High Temperature Annealing (HTA) process. Introduction Day after day, the quality of 4H-SiC bulk and epilayer materials is improving and several unipolar devices such as Schottky and JBS rectifiers, JFET and MOSFET are now commercially available. Nevertheless, some technological limitations still exist. One of them is related to the absence of validated process for implementing local and in-depth p-type doping into 4H-SiC. Currently, Al ion implantation is the simplest and most popular technique to perform localized p + doping, however, with significant drawbacks. First, the high energy ions degrade the crystal quality and a high temperature annealing (typ C) is required to both partially activate the Al elements and tentatively restore the crystal quality [1]. In practice, it has not been possible so far to obtain high p- type doping level with acceptable defect densities. Also, the depth of the p-type implanted areas is limited to a few hundreds of nm for standard ion implanter energy ( < 200 kev ). SiC Selective Epitaxial Growth (SEG) by Vapour-Liquid-Solid (VLS) transport in a bowl-shaped geometry (see Fig. 1) appears as a promising solution to create deep, highly doped, and high crystal quality areas, both n or p type. Such SEG-VLS growth of highly p-doped (> 5x10 19 cm -3 ) 4H- SiC areas was successfully demonstrated recently on large area circular-shaped structures buried down to 1 µm [2]. The crystal growth results needed to be completed by electrical characterization of PiN diode structures. This is the purpose of the work presented in this paper. All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-13/05/16,10:23:36)

2 912 Silicon Carbide and Related Materials 2012 Experiments Fig. 1 and 2 display the structure of the fabricated and characterized PiN diodes with 300 µm diameter. The n - layer was grown in a hot-wall CVD reactor on 8 -off 4H-SiC substrate. The 1 µm depth bowl-shaped structures were obtained by optical lithography and SF 6 /O 2 Reactive Ion Etching (RIE) patterning. Figure 1: Structure of the fabricated and characterized PiN diodes Figure 2: SEM picture of a 300 µm diameter circular PiN diode after the VLS growth Details about the SEG-VLS process are reported elsewhere [2]. Cathode and anode metallization stacks for ohmic contacts are: Ni(170nm)/Ti(5nm) and Al(240nm)/Ti(40 nm)/ni(10nm) [3], respectively, annealed in a Rapid Thermal Annealing (RTA) furnace, during 90 s under Ar, at 900 C and 800 C respectively. The diodes (>10 diodes per sample) were electrically characterized at room temperature using a K2410 System Measure Unit with probe station. On some of these diodes, current-voltage measurements at variable temperature ( C) have been performed. Results and discussions Fig. 3 reports J-V behaviors of several diodes from 3 different samples SEG-VLS grown under different sets of growth conditions. For a better readability, only a few representative J-V characteristics have been plotted. Figure 3: J-V behaviors of several diodes on 3 samples with different SEG-VLS growth conditions. a) reverse characteristics - b) forward characteristics. S stands for sample and d is for diode. First, we did not evidence any clear influence of VLS growth conditions on the forward and reverse J-V characteristics. Indeed, on all samples, there is large spreading of I-V behaviors of the diodes. At V r = -400 V, some diodes have a low leakage current J < 10-4 A cm -2 while some have a high leakage current J 10-2 A cm -2. Some even exhibit low breakdown voltage V BR < 50 V. Moreover, as can be seen on Fig. 3-b, the direct bias threshold voltage (V 0 ) varies from 1.6 to 1.8 V while, for a normal 4H-SiC P-N junction, V 0 is usually found around 3 V. Therefore, the current

3 Materials Science Forum Vols conduction model of our diodes had to be clarified. To get more information, I-V-T measurements were performed on several diodes from Sample 2. Fig. 4-a presents the results obtained on a typical diode. On Fig. 4-b, we have plotted the evolution, with the measurement temperature, of the diode differential resistance (R D ) and V 0, extracted from the linear part of I-V-T characteristics. Figure 4: a) Current-Voltage-Temperature (I-V-T) characteristics of a typical diode b) Evolution of the threshold voltage (V 0 ) and the differential resistance (R D ) extracted from I-V-T- behaviors as functions of the measurement temperature. Surprisingly, the plots clearly exhibit an intersection of the I-V-T characteristics, with an increase of R D and a decrease of V 0 as the measurement temperature is increased. Such behaviors are typical of a thermionic current conduction mechanism, where the access resistance R C mainly depends on the materials resistivities of the n - (epi) and n + (substrate) zones, and V 0 is governed by the Schottky barrier height. Moreover, for most of the diodes on the 3 samples, fitting the forward I-V characteristics along a Thermo-ionic Emission model at room temperature provides Schottky Barrier Height (Φ b ) and Ideality Factor (n) values in the ranges : 1.16 < Φ b < 1.35 ev and 1.54 < n < 1.8. Different hypotheses can be raised to explain these results. First, it may happen that the grown crystal is not 4H-SiC but other SiC polytype or some kind of AlSiCN compound. However, with the same growth conditions, our previous studies [2] clearly identified a step-bunched p ++ epitaxial 4H- SiC surface on the grown areas. Indeed, it is highly unexpected that epitaxial 4H-SiC could possibly grow on top of any kind of foreign material. Another hypothesis would involve the presence of crystalline defects (possibly metallic behavior inclusions) around the VLS-epi / CVD-epi interface, modifying the P-N junction electrical behavior. Previously [4], some kinds of defects have actually been observed after standard (non SEG) VLS growth of a P ++ layer onto a N + 4H-SiC substrate. Figure 5: Effect of the High Temperature Annealing on the J-V-T characteristics of the diodes. a) Reverse bias b) Direct bias.

4 914 Silicon Carbide and Related Materials 2012 Assuming that last hypothesis is correct, a High Temperature Annealing (HTA) might improve the crystalline quality of the interface by providing some limited diffusion of the acceptor elements. Fig. 5 shows the typical J-V-T characteristics under forward and reverse bias of typical diodes made on the same CVD epi sample, with and without High Temperature Annealing (HTA) after VLS growth. Prior to this annealing at 1700 C under Ar during 30 mn, the surface of this sample has been passivated by a carbonized polymer layer. As expected, J-V-T characteristics of diodes without HTA exhibit the same Schottky-like behavior as previously with comparable V 0 values and rapid increase of the leakage current for V r > 50 V. The J-V-T characteristics of diodes on VLS + HTA samples are extremely different. The forward J-V characteristics at different temperatures are parallel one to each other, as expected for a bipolar conduction, with a decrease of V 0 and a stagnation of R D as the measurement temperature is increased. Moreover, the V 0 value at RT is found around V V, compatible with that of a 4H- SiC P-N junction. In order to confirm the different conduction modes in the PN diodes on HTA and as-grown samples, we have performed electroluminescence tests at V f = 4 V. Fig. 6 shows clearly that diodes on VLS + HTA sample exhibit light emission while no significant emission is observed from diodes on VLS only sample. These observations tend to confirm the bipolar nature of the conduction mode on VLS + HTA samples. Figure 6: Observation of the electro-luminescence under forward bias at 4 V on typical diodes from VLS only and VLS + HTA samples. Conclusion In conclusion, our studies demonstrate for the first time that p ++ SEG by VLS transport, followed by High Temperature Annealing, can provide high quality p-n junctions on 4H-SiC. This work paves the way towards the use of this technique for the achievement of new devices for power electronics, including deeply buried peripheral protection zones such as guard rings or JBS structures. Acknowledgments The authors want to thank for their financial support: the Agence Nationale pour la Recherche (ANR) (project VHVD-SiC / ANR-08-BLAN ), the Swedish Energy Agency (project ), and the Swedish Research Council (VR ). References [1] V. Heera et al, J. Appl. Phys (2004), [2] D. Carole et al, Mater. Sci. Forum (2012), [3] F. Laariedh et al, Mater. Sci. Forum. 711 (2012), [4] C. Jacquier et al, Mater. Sci. Forum (2004),

5 Silicon Carbide and Related Materials / Electrical Characterization of PiN Diodes with p + Layer Selectively Grown by VLS Transport / DOI References [3] F. Laariedh et al, Mater. Sci. Forum. 711 (2012), /