Novel Back-Biased UTBB Lateral SCR for FDSOI ESD Protections
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1 Novel Back-Biased UTBB Lateral SCR for FDSOI ESD Protections Yohann Solaro 1,2,3, Pascal Fonteneau 1, Charles-Alexandre Legrand 1 Claire Fenouillet-Beranger 1,3, Philippe Ferrari 2, Sorin Cristoloveanu 2 yohann.solaro@st.com 1 2 3
2 Outline 2 Introduction & Context
3 Outline 3 Introduction & Context Lateral Silicon Controlled Rectifier (LSCR) Fabrication & Principle
4 Outline 4 Introduction & Context Lateral Silicon Controlled Rectifier (LSCR) Fabrication & Principle LSCR Experimental Results
5 Outline 5 Introduction & Context Lateral Silicon Controlled Rectifier (LSCR) Fabrication & Principle LSCR Experimental Results Conclusions
6 Introduction & Context
7 Introduction & Context (1) 7 Electro-Static Discharge Damages [Russ, 1999]
8 Introduction & Context (1) 8 Electro-Static Discharge Damages Gate oxyde breakdown Drain junction filamentation Interconnects damages [Semenov, O., 1999] [Russ, 1999]
9 Introduction & Context (1) 9 Electro-Static Discharge Damages Gate oxyde breakdown Drain junction filamentation Interconnects damages [Semenov, O., 1999] ESDs are destructive events [Russ, 1999]
10 Introduction & Context (1) 10 Electro-Static Discharge Protection Requirements Principle & Design of a protection Robustness, Effectiveness, Speed, Transparency [Amerasekera & Duvvury 2002] Z CLAMP << Z CORE under ESD condition Z CORE << Z CLAMP normal operation [Russ, 1999]
11 Introduction & Context (1) 11 Electro-Static Discharge Protection Requirements Principle & Design of a protection Robustness, Effectiveness, Speed, Transparency [Amerasekera & Duvvury 2002] Z CLAMP << Z CORE under ESD condition Z CORE << Z CLAMP normal operation Global or Local strategies [Russ, 1999]
12 Introduction & Context (1) 12 Electro-Static Discharge Protection Requirements Principle & Design of a protection Robustness, Effectiveness, Speed, Transparency [Amerasekera & Duvvury 2002] Z CLAMP << Z CORE under ESD condition Z CORE << Z CLAMP normal operation Global or Local strategies [Russ, 1999]
13 Introduction & Context (2) 13 Reduced ESD design window in Fully Depleted SOI I TLP V dd + 10% «Core MOS» breakdown [Benoist et al. 2011] FDSOI 3 Bulk V TLP
14 Introduction & Context (2) 14 Reduced ESD design window in Fully Depleted SOI I TLP I t2 I t2 : Failure current V h : Holding voltage V t1 : Triggering voltage V dd + 10% «Core MOS» breakdown [Benoist et al. 2011] (V h, I h ) (V t1, I t1 ) FDSOI 3 Bulk V TLP
15 Introduction & Context (2) 15 Reduced ESD design window in Fully Depleted SOI I TLP I t2 I t2 : Failure current V h : Holding voltage V t1 : Triggering voltage V dd + 10% «Core MOS» breakdown [Benoist et al. 2011] (V h, I h ) (V t1, I t1 ) new candidate for FDSOI ESD protection : LSCR FDSOI 3 Bulk V TLP
16 LSCR Fabrication & Principle
17 LSCR Fabrication & Principle 17 Device Geometry From SOI PIN-Diode Cathode Contact NiSi RPO SiN Anode Contact N+ SOI BOX P- P+ Ground Plane (GP)
18 LSCR Fabrication & Principle 18 Device Geometry From SOI PIN-Diode to SOI Lateral SCR (Thyristor) Cathode Contact NiSi RPO SiN As Anode Contact N+ SOI BOX P- N P+ Ground Plane (GP)
19 LSCR Fabrication & Principle 19 Device Geometry From SOI PIN-Diode to SOI Lateral SCR (Thyristor) Cathode Contact NiSi RPO N+ SiN 7 nm +15 nm P- N P+ SOI BOX As Anode Contact Ground Plane (GP) Lateral N+/P/N/P+ arrangement SOI thickness = 7 nm BOX = 25 nm No Front Gate deposited [1] Si. Epitaxy (+15 nm) on whole structure (raised Source/Drain)
20 LSCR Fabrication & Principle 20 Device Geometry Cathode Contact NiSi RPO N+ SiN SOI BOX 7 nm +15 nm This work: «Thin» technology (UTBB-SOI) SOI thickness = 7 nm Si. epitaxy = + 15nm BOX = 25 nm Other works: (PD-SOI) [1] Li et al. EOS/ESD, [2] Cao et al. Microelectronics Reliab, [3] Marichal et al. EOS/ESD [4] Entringer et al. EOS/ESD 2006.
21 LSCR Fabrication & Principle 21 Device Geometry [4] Cathode Contact NiSi RPO SiN N+ SOI BOX [2] SOI [3] SOI SOI BOX This work: «Thin» technology (UTBB-SOI) SOI thickness = 7 nm Si. epitaxy = + 15nm BOX = 25 nm Other works: (PD-SOI SCRs) [1] Li et al. EOS/ESD, [2] Cao et al. Microelectronics Reliab, [3] Marichal et al. EOS/ESD [4] Entringer et al. EOS/ESD 2006.
22 LSCR Fabrication & Principle 22 Device Geometry «Side Base Contacts»: P-Base (B P ) can be tied to K («locked» mode) N-Base (B N ) left floating in this study BOX etch Ground-Plane (GP) used as a back gate
23 LSCR Principle 23 NPN Modulation NPNP = Thyristor = Two inter-linked BJTs [1,2] with shared BC junctions [1] Moll et al., Proceedings of the IRE, [2] Sze, Wiley, V Gb = -2V E C N P N P Simulated band diagram at mid-film x = - 11 nm E V
![LSCR Principle 24 NPN Modulation NPNP = Thyristor = Two inter-linked BJTs [1,2] with shared BC junctions NPN Base potential modulated by V Gb V](/docs-images/93/114168081/images/24-5.jpg "Gb [1] Moll et al., Proceedings of the IRE, 1956. [2] Sze, Wiley, 1981.")
24 LSCR Principle 24 NPN Modulation NPNP = Thyristor = Two inter-linked BJTs [1,2] with shared BC junctions NPN Base potential modulated by V Gb V Gb [1] Moll et al., Proceedings of the IRE, [2] Sze, Wiley, V Gb -2V E C +1V N P N P Simulated band diagram at mid-film x = - 11 nm E V
25 LSCR Experimental Results
26 Experimental Results 26 NPN Characterization NPN gain known to impact the SCR behavior (V t1, I t1, I leak ) Strong accumulation condition in the NPN base : V Gb = -2V Common-Emitter NPN Forward Gummel Measurement Common-Emitter Gain β (= I C /I B ) mainly depends on NPN Base length: L P N-GP β 38 P-GP L P = 200 nm β 8 L P = 500 nm
27 Experimental Results 27 NPN Characterization Back channel NMOS transfert characteristic (I D -V Gb ) N-GP P-GP
28 Experimental Results 28 NPN Characterization Back channel NMOS transfert characteristic (I D -V Gb ) Short channel swing is degraded : L P = 500nm : S 95mV/dec L P = 200nm : S 175mV/dec N-GP P-GP Short Long
29 Experimental Results 29 NPN Characterization Back channel NMOS transfert characteristic (I D -V Gb ) Short channel swing is degraded : L P = 500nm : S 95mV/dec L P = 200nm : S 175mV/dec N-GP P-GP V th shift: +850mV due to GP-type (workfunction difference between N and P-GP) Short Long 850 mv
30 Experimental Results 30 The NPN bipolar is effectively Modulated! The NPN base potential is modulated by V Gb The Base-Emitter barrier depends on V Gb V Gb I C eff E B C +2 V I C V Gb I B 0 V -2 V L P = 200 nm P-GP
31 Experimental Results 31 The NPN bipolar is effectively Modulated! The NPN base potential is modulated by V Gb The Base-Emitter barrier depends on V Gb V Gb I C eff β NPN eff [1] [1] Colinge, IEEE TED, E B C +2 V I C Common-Emitter NPN Forward Gummel Measurement +2 V V Gb V Gb I B 0 V 0 V -2 V -2 V L P = 200 nm P-GP L P = 200 nm P-GP
32 Experimental Results 32 NPN Modulation changes SCR triggering The NPN Base potential is modulated by V Gb The Base-Emitter barrier depends on V Gb V Gb I C eff β NPN eff I t1, V t1 SCR Triggering point (I t1, V t1 ) is set by β NPN (L P...) L P = 200nm P-GP L P = 500nm V Gb = 0V B P Locked
33 Experimental Results 33 NPN Modulation changes SCR triggering The NPN Base potential is modulated by V Gb The Base-Emitter barrier depends on V Gb V Gb I C eff β NPN eff I t1, V t1 SCR Triggering point (I t1, V t1 ) is set by β NPN (L P, GP-type...) L P = 200nm N-GP P-GP L P = 500nm V Gb = 0V B P Locked
34 Experimental Results 34 NPN Modulation changes SCR triggering The NPN Base potential is modulated by V Gb The Base-Emitter barrier depends on V Gb V Gb I C eff β NPN eff I t1, V t1 SCR Triggering point (I t1, V t1 ) is set by β NPN (L P, GP-type...) P-GP L P = 200nm V Gb = 0V B P Locked
35 Experimental Results 35 NPN Modulation changes SCR triggering The NPN Base potential is modulated by V Gb The Base-Emitter barrier depends on V Gb V Gb I C eff β NPN eff I t1, V t1 SCR Triggering point (I t1, V t1 ) is set by β NPN (L P, GP-type, V Gb...) +1V 0V V Gb P-GP L P = 200nm B P Locked
36 Experimental Results 36 NPN Modulation changes SCR triggering The NPN Base potential is modulated by V Gb The Base-Emitter barrier depends on V Gb V Gb I C eff β NPN eff I t1, V t1 SCR Triggering point (I t1, V t1 ) is set by β NPN (L P, GP-type, V Gb...) B P Floating V Gb +1V 0V B P Locked Strong capacitive coupling between P-base and back-gate allows floating-mode operation P-GP L P = 200nm
37 Experimental Results 37 NPN Modulation changes SCR triggering The NPN Base potential is modulated by V Gb The Base-Emitter barrier depends on V Gb V Gb I C eff β NPN eff I t1, V t1 SCR Triggering point (I t1, V t1 ) is set by β NPN (L P, GP-type, V Gb...) B P Floating V Gb +1V 0V Strong capacitive coupling between P-base and back-gate allows floating-mode operation P-GP L P = 200nm
38 Experimental Results 38 NPN Modulation changes SCR triggering The NPN Base potential is modulated by V Gb The Base-Emitter barrier depends on V Gb V Gb I C eff β NPN eff I t1, V t1 SCR Triggering point (I t1, V t1 ) is set by β NPN (L P, GP-type, V Gb...) Strong capacitive coupling between P-base and back-gate allows floating-mode operation
39 Experimental Results 39 NPN Modulation changes SCR triggering The NPN Base potential is modulated by V Gb The Base-Emitter barrier depends on V Gb V Gb I C eff β NPN eff I t1, V t1 SCR Triggering point (I t1, V t1 ) is set by β NPN (L P, GP-type, V Gb...) Strong capacitive coupling between P-base and back-gate allows floating-mode operation I leak V t1 LSCR is able to trigger in the 28FDSOI ESD design window
40 Experimental Results 40 SCR V dd = 1V Stronger Base-Emitter barrier means lower leakage N-GP P-GP B P Locked N-GP P-GP Floating B p locked Floating B p locked I V Gb = 0V 7 na/µm 100 pa/µm 93 pa/µm 0.5 pa/µm B P Floating L P = 200 nm I V Gb = -1V 0.9 pa/µm 0.7 pa/µm 17 fa/µm 1.1 pa/µm
41 Experimental Results 41 Transmission Line Pulse (TLP) High-Current measurements No need of Base contacts V t1 adjustment with V Gb is confirmed Performance: I t2 5mA/µm (TLP 100 ns) L P = 200 nm P-GP B P floating t Pulse = 100 ns Failure (I t2 ) +2 V -2 V V V Gb = +1V Gb 0V V Gb = 0 V L P = 200 nm P-GP BP floating t Pulse = 100 ns
42 Conclusions
43 Conclusions 43 LSCR experimentally demonstrated and understood via TCAD in an Ultra-Thin-SOI technology: I leak < 20 fa/µm is achievable with adequate V Gb «Tunable V t1» (adjustable to application) with Back Bias, GP-type, NPN Base length Controlled only with back gate biasing : No need of Base Contacts or Front Gate SOI-LSCR is fully compatible with standard FDSOI CMOS process TLP performances (ESD failure current) validates I t2 5mA/µm Adequate for «Core MOS» protection in 28nm FDSOI
44
45
46 BackUp Slides
47 Transient Characteristics for ESD 47 Transient & ESD Applications V Gf = +1.5 V L int = 1 µm L int = 200 nm V Gb = -2 V Voltage Pulse with 50 ps RT and I A = 1mA/µm For decreased L int : Overshoot Peak Voltage decreases from 9V to 3V Device response time (< 50 ps)
![FEDs 48 [Salman et al. 2006] [Cao et al.](/docs-images/93/114168081/images/48-3.jpg "2011] FED V g1 controls the inversion in the (P-) region")
48 FEDs 48 [Salman et al. 2006] [Cao et al. 2011] FED V g1 controls the inversion in the (P-) region and change the triggering voltage of the structure t Si = 70nm t BOX =? doped: P+/P-/HVt/N+ FED L g1 = L g2 = 0.5 µm, L gap? V g1
49 LSCR Characterization 49 NPN Gain in accumulation Accumulation condition V Gb = -2V 2 designed Bases: L P =200 & 500 nm No dependance of β NPN on GP type β NPN 40 with L P =200 nm V Gb = -2V L P GP-type (N or P) 200 nm Common-Emitter configuration N-GP P-GP 500 nm L P V Gb = -2V
50 LSCR Characterization 50 NPN = «Back-Channel» NMOS NMOS Extraction of Threshold [1] & Swing in linear regime (V D = 20mV) 850mV V th shift N-GP to P-GP S = 95 mv/dec to 175 mv/dec L P GP-type (N or P) N-GP 200 nm P-GP Floating Body configuration N-GP P-GP L P 500 nm [1] Ghibaudo et al. Electronics Letters, 1988
51 LSCR Characterization 51 Effective NPN Gain control β NPN eff is dramatically increased by back NMOS I D current V Gb < -1V allows a strong diminution of I leak (20fA/µm) β NPN eff : I t1 & V t1 V Gb +2V B P Floating +1V 0V V Gb B P Locked 0V V Gb -2V L P = 200 nm P-GP L P = 200 nm P-GP
![2005]](/docs-images/93/114168081/images/52-9.jpg "[Entringer")
52 LSCRs 52 State of the Art [Marichal et al. EOS/ESD 2005] [Entringer et al. EOS/ESD 2006]
![al. EOS/ESD, 2012]](/docs-images/93/114168081/images/53-8.jpg "«Lateral Diodelike»")
53 LSCRs 53 State of the Art [Cao et al. Microelectronics Reliab, 2011] [Li et al. EOS/ESD, 2012] «Lateral Diodelike» «SCRlike» LSCR «DWFED»
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