4H SiC Schottky diodes under ESD and thermal stresses: A failure analysis method.

Transcription

1 4H SiC Schottky diodes under ESD and thermal stresses: A failure analysis method. Pascal DHERBECOURT Groupe de Physique des Matériaux UMR CNRS 6634 The first part of the presentation reports electrical and physical characteristics degradations of silicon carbide Schottky diodes placed at temperature (T>200_C) above manufacturers use recommandation. When simulating automotive harsh temperature environment, the tests have led to an increase of the dynamic resistance greater than 20%, driving the device in a non catastrophic failure mode. A following physical X-Rays analysis reveals an expected degradation of the solder joint as the testing temperature has been set just a few degrees above the lower melting point element, limiting the device operating temperature range. Correlation between electrical and physical degradations could have been driven by only inspecting the lower melting point element post-degradation state. However, we widened the area of inspection to observe that the resin package has undergone such degradation that it might play a full part in the degradation process taking place in derating mode use. The second part propose a complete failure analysis of silicon carbide (SiC) junction barrier Schottky (JBS) diodes under high electrostatic discharge (ESD) human body model (HBM)-like stresses addressing the limit of robustness for this new generation of high power devices. The Physics of Failure is fully investigated, first by analyzing electrical measurements which are relevant to physical integrity and interface states using parameters predicted by thermionic emission (TE) theory. Secondly Optical Beam Induced Resistance Change (OBIRCH) is used for the localization of surface defects. Finally, Focused Ion Beam (FIB) cuts are performed and Transmission Electron Microscopy (TEM) analyses are carried out to characterize the structural and elemental composition modifications. With the results, correlations can be made between electrical and physical degradations, leading to reliable hypotheses about the root cause of the weaknesses of these devices when subjected to this kind of stress.

2 4H-SiC Schottky diodes under ESD and thermal stresses: A failure analysis method. Pascal DHERBECOURT Normandie Université - Rouen Groupe de Physique des Matériaux UMR CNRS

3 The «Groupe de Physique des Matériaux»: a research cluster with the CNRS, University of Rouen, INSA of Rouen. GPM SKILLS : Fundamental research directly related to the applications (electronic, mechanical or magnetic). Many collaborations with the aviation industry, energy, and microelectronics (Arcelor, ALCAN, EDF, Ugimag, VALEO, Michelin, Freescale, Thales...). The highlight of the GPM : scientific instrumentation with the development of TAP. ERDEFI : Failure analysis of power electronic components ( Electrical characterization, Thermal and overvoltage stresses,..) Si, SiC and GaN technologies 2

4 Electrical static and dynamic characterization Global approach: Ageing and failure analysis methodology Ageing with operational working conditions on a specific bench Chemical, laser and mechanical depackaging Photoemission Microscopy PEM OBIRCH to localize any defect Structural Analysis FIB, TEM, SEM, TAP to understand failure process 3

5 SiC Schottky diode under study Commercially SiC Schottky Barrier Diode in TO-220 package. Maximum junction temperature is recommended at 175 C. These devices are designed to withstand a 1200V breakdown voltage and to support a 5A DC current in forward mode. Below : A top view of the device anode. Surface structure analysis Aluminum metallization of the front side of the die The entire surface evaluated by SEM analysis at 1.8 mm2. 4

6 SiC Schottky diode under test Materials composing the packaging : material declaration report and EDX analysis The global composition of elements comprising the packaging: Package opening 5

7 SiC Schottky diode under test Trench MOS Barrier Schottky (TMBS) diode Cross section analysis P+ well and Junction Termination Edge (JTE) are integrated to limit high localized electric field in the structure. 6

8 High Temperature Storage Reliability Experimental protocol JEDEC JESD22-A103D HTSL : Devices are subjected to a storage temperature of 240C for over 350 hours. Including every 24 hours, I-V pulsed characterization. Results : Variation of V th is lesser than 3% (not significant). No change for the ideality factor and high barrier height after modeling, This results confirm a strong stability of the die at of the metal/semiconductor interface. However, dynamic resistance has shown a significant change, increasing of more than 20%! 7

9 The solder joint seems to be the point of weakness of the structure: for Motorola J Alloy, melting temperature is about C. May be a strong reduction of the contact surface between the ohmic contact of the die? Dynamic resistance evolution versus high temperature storage time for four unbiaised devices. Investigations were driven in this direction! 8

10 Physical characterizations Before stress : X-rays imaging of new devices : a good homogeneity, and few voids at the solder joint /ohmic contact interface. Before stress : After stress : After stress : important solder joint roughness at the ohmic contact side interface has appeared : The solder joint is widespread over a larger area, it could be assumed that the solder joint has slid on the leadframe. 9

11 Cross section of a new device showing a perfect contact between die, copper leadframe, solder joint and resin. Cross section of damaged device showing numerous voids at solder / die and resin contact. 10

12 Conclusion for temperature Storage Life test : SiC Schottky diodes in TO-220 package have been tested in a simulated derating mode. Solder joint, appears as the Achilles heel of the structure as temperature was set just above its melting value. However, resin to leadframe interface degradation is a crucial concomitant factor : It allows the widespread and the melting away of the solder joint under the die. 11

13 Schottky diodes under ESD stresses Norme HBM/IEC Robustness ESD HBM-like-Test protocol Electro-Static Discharge Human Body Model (ESD HBM) The ESD waves are applied by contact in reverse mode directly on the DUT pins thanks to the ESD Gun Schaffner NSG438 2 kω 330 pf at 15 kv Devices are iteratively degraded at each new ESD strike. A full set of 20 devices is tested and the number of electrical strikes is modulated to study the electrical evolutions of devices. 3 have shown no electrical change : insensitive to ESD? Very interesting and not explained at this level. 12

14 I-V characterizations from a new device to a degraded device by four 15 kv strikes. The leakage current limit and asymptotic behavior is clearly shown 13

15 Localization of the physical defect is revealed by using an Optical Beam Induced Resistance CHange (OBIRCH) technique. First, an integrated picture of the die's surface was stored before superimposing it with the red spot OBIRCH analysis image. This view is then used for microscopy defect localization, before a FIB cut. OBIRCH surface defect localization. 14

16 TEM observation is carried out by Scanning Transmission Electron Microscopy High Angle Annular Dark Field (STEM HAADF) A cataclysmic region is identified and the initial structure was completely destroyed, leading to a discontinuity in the initial crenulated geometry. 15

17 Research the accurate model of the electrical behavior? Four domains from Part I to Part IV Parts III and IV : not take into account the low barrier Phenomenon : Thermionic emission Theoretical model of fresh device : with 16

18 The real modeling for a fresh device? Taking into account Part I and Part II : described by a two Schottky barriers model. The total current is the resultant of two currents physically flowing in parallel through two different barrier regions. A mathematical algorithm is deployed based on the Lambert W-function Double Schottky branches model for fresh devices. 17

19 Finally, an explicit solution of total current is given by this equation: with The modeling of fresh devices is validated by experimental data! 18

20 The modeling for a aged device with ESD stresses? Fresh device ESD stressed device local defects due to ESD stress! A third Schottky branch plus a shunt resistance are added to the initial model to comply with the natures of new areas of metal/semi-conductor contacts. 19

21 The modeling for a aged device with ESD stresses? Simulation without third Schottky branch (green), leads to feeble change in the curve under the threshold. But : Simulation without R shunt (black), shows significant effect of the curve under the threshold Conclusion :the path created has a strong ohmic nature and then the new M/SC interface is mainly an ohmic contact.! Introduction/ Diode SiC/ High Temperature Storage Life/Schottky diodes under ESD Graphical representation of the fitting model over the experimental results 20

22 The modeling for a aged device with ESD stresses? 21

23 Conclusion for ESD stresses : This study allows to identify the origin and failure mechanisms of devices with ESD stressed.. Electrical extraction process is suitable for new and modified IV characteristics. This shunt resistance in the equivalent electrical model is identified with the presence of a crack resulting from ESD stresses. OBIRCH localization, FIB cuts and microscopy views are carried out to ensure a full structural analysis. 22

24 Thank you for your Attention! 23