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1 AN ABSTRACT OF THE THESS OF Bo Zhou for the degree of Master of Science in Electrical & Computer Engineering presented on December 2, 996. Title: High Speed Digital FR Filter Design Abstract approved: Redacted for Privacy Shih_Lien Lu The objective of this thesis is to design a high speed digital FR filter. The inputs of the system come from a Delta-Sigma modulator. This FR filter takes 024 inputs, multiplies them with their coefficients and adds the results. The main design task is to take the input data, which are unweighted single-bit binary numbers at 56MHz, multiply each bit with the corresponding coefficient and add them to get a weighted multi-bit output at 20MHz.

2 Copyright by Bo Zhou December 2, 996 All Rights Reserved

3 High Speed Digital FR Filter Design by Bo Zhou A THESS submitted to Oregon State University in partial fulfillment of the requirements for the degree of Master of Science Completed December 2, 996 Commencement March 997

4 Master of Science thesis of Bo Zhou presented on December 2, 996 APPROVED: Redacted for Privacy Major Professor, representing Electrical & Computer Engineering Redacted for Privacy Chair of Department o Electrical & Computer Engineering Redacted for Privacy Dean of Graduat chool understand that my thesis will become part of the permanent collection of Oregon State University libraries. My signature below authorizes release of my thesis to any reader upon request. Redacted for Privacy Bo Zhou, Author

5 ACKNOWLEDGEMENTS With utmost respect and gratitude, want to thank Dr. Shih_Lien Lu, my supervisor. His broad knowledge and sharp thinking gave the initial idea for this project, and his kindness and patience encouraged me through the project. greatly appreciate his the support on this project and on my whole master study. Many thanks to Dr. Jack Kenney, Dr. David J. Allstot and Dr. James Welty for taking their precious time out of their busy schedules to serve on my graduate committee and to read the manuscript of this thesis. Thanks to Dr. Richard Schreier, Mr. Bo Zhang, Mr. Haiqing Lin, Mr. Bo Wang and Mr. Wenjun Su for their kind help with the thesis. Thanks to Ms. Rita Wells for her help with all the tedious paper work that makes this thesis possible. Thanks to Mr. John Seredich at Silicon Systems ncorporated for taking the effort to help me fix the format and present the thesis in such an elegant way. Thanks to Westinghouse Electric Co. for their financial support on the project. And finally, want to say thank you to my husband and my little boy for all the precious things you give to me.

6 TABLE OF CONTENTS Page Chapter. ntroduction. FR Filter System.2 Linear Phase FR 3.3 System Outline 4.4 Organization of the Document 5 Chapter 2. Overall Structure of the System 6 2. nput Part Shift Register Latch Register Pre-Processor Part XOR AND Data Processor Part Wallace Tree Carry-Select and Carry-Look-Ahead Adder Summary 0 Chapter 3. Full Adder 3. Full Adder 3.2 The Comparison of Static CMOS Adder and Transmission Gate Adder Static CMOS Full Adder Simulation 4

7 TABLE OF CONTENTS (Continued) Page 3.3. The Affect of Temperature on Circuit Performance The Affect of Transistor Size on Circuit Performance The Effect of Power Supply Variation on Circuit Performance Summary 9 Chapter 4. Design and Simulation of D Flip Flop 2 4. Sequential Circuits Flip-Flops D Flip-Flop CMOS Static DFF Simulation The Comparison of Three Kinds of Transmission Gate DFF Working Performances with Different Sizes of Transistors Timing Simulation About DFF Summary 30 Chapter 5. Function Blocks 3 5. Shift Register and Latch Register Wallace Tree Carry-Save Adders Wallace Tree Sign-Bit in Wallace Tree Structure Trade-Off for Wallace Tree Carry-Look-Ahead and Carry-Select Adder Summary 44

8 TABLE OF CONTENTS (Continued) Page Chapter 6. Conclusion Conclusion Future Work 45 Bibliography Appendices Appendix A Hspice Simulation Results Appendix B Wallace Tree Structures Appendix C Schematics of the Wallace Trees

9 LST OF FGURES Figure Page. Direct-Form Realization of FR Filter Structure 3.2 Direct-Form Realization of Linear-Phase FR System 4 2. Overall Structure for the System 6 3. Complementary CMOS Full Adder Transmission Gate XOR Transmission Gate Full Adder 4 4. Block Diagram for a Flip-Flop Static CMOS D FLP FLOP Test Circuit for Different Kinds of Transmission Gates CMOS Static DFF with mproved Size Transistors DFF Clock & nput Relation Shift Register and Latch Register Block Examples of Single Bit CSA Counters (3,2) and (7,3) Counter Structures (5,4) Counter Structure Example of Multi-Bit Wallace Tree Three 20-bit Wallace Tree Structure 38

10 LST OF FGURES (Continued) Figure Page 5.8 Seven 20-bit Wallace Tree Structure Fifteen 20-bit Wallace Tree Structure Fifteen 20-bit Wallace Tree with (3,2) to be the Basic Element Continued Carry-Look-Ahead & Carry-Select Adder 44

11 LST OF TABLES Table Page 3. Truth Table for Full Adder 3.2 Stimulus to Simulate the Affect of Temperature on FA Delay Delay of FA with Minimized Transistor Sizes Delay of FA with Optimum Transistor Sizes The Delay of FA with Vdd Variation 9 4. Speeds of DFF With Different Transmission Gate 26

12 LST OF APPENDX FGURES Figure Page A. Full Adder with Minimum Sized Transistors 50 A.2 Full Adder Simulation with Minimum Size Transistors (T= -220) 5 A.3 Full Adder Simulation with Minimum Sized Transistors(25C,5.5V) 52 A.4 Full Adder with Optimum Sized Transistors 53 A.5 DFF with mproved Sized Transistors 54 A.6 Static DFF Simulation () 55 A.7 DFF Simulation (2) 56 A.8 DFF Simulation (3) 57 A.9 DFF Simulation (4) 58 A.0 DFF Simulation (5) 59 B. MAC 0 6 B.2 MAC 02 6 B.3 MAC 03 6 B.4 MAC B.5 MAC 62 B.6 MAC 2 62 B.7 MAC 2 63 B.8 MAC 22 63

13 LST OF APPENDX FGURES (Continued) Figure Page B.9 MACRO 3 63 B.0 MACRO 4 64 B. MAC 3 64 B.2 MAC 4 64 B.3 MAC 5 65 B.4 MAC 6 65 B.5 MAC 7 65 B.6 MAC 8 66 B.7 W3N20L20 66 B.8 W3N2OB 66 B.9 W3N2L20 67 B.20 W3N26L20 67 B.2 W5N2OB 68 B.22 W9N2OB 69 B.23 Level 70 B.23 Level (continued) 7 C. FR Top Level Schematic 73 C.2 Shift

14 LST OF APPENDX FGURES (Continued) Figure Page C.3 Shift 64 C.4 Latch 024 C.5 Latch 64 C.6 XOR 52 C.7 XOR 64 C.8 M256 C.9 M32 C.0 M8 C. FA 24 or Counter (3,2) C.2 Counter (7,3) C.3 Counter (5,4) C.4 Level C.5 W3N2OB C.6 W5N2OB C.7 W9N2OB C.8 Level C.9 MAC 0 C.20 MAC

15 LST OF APPENDX FGURES (Continued) Figure Page C.2 MAC C.22 MAC C.23 MAC 95 C.24 MAC 2 96 C.25 MAC 2 97 C.26 MAC C.27 MAC 3 99 C.28 MAC 4 00 C.29 MAC 5 0 C.30 MAC 6 02 C.3 MAC 7 03 C.32 MAC 8 04 C.33 W30N20L20 05 C.34 W3N26L20 06 C bit Carry-Look-Ahead & Carry-Select Adder 07 C.36 4-bit Carry-Select Adder 08 C.37 4-bit Carry-Look-Ahead Adder 09

16 High Speed Digital FR Filter Design Chapter. ntroduction n the last two decades, Digital Signal Processing (DSP) has made enormous progress both in theory and practice. With the advancement of Very Large Scale ntegrated Circuit (VLS) technology, more and more applications are using DSP as the primary solution due to the reliability, reproducibility, compactness and efficiency of the digital technology. The objective of this thesis is to design a high speed digital Finite mpulse Response (FR) filter, which is part of a Delta-Sigma Analog to Digital Converter. This filter will be part of a digital decimator which is used to convert the highspeed bit-stream output of the Delta-Sigma modulator into Nyquist-rate PCM data. Conceptually, this operation consists of two parts: lowpass filtering and down-sampling. For the sake of economy, the over-sampling ratio can be reduced in stages. Since a singlestage filtering down-sampling block requires more than 0,000 taps to achieve our specification requirement, we employed the design of a multiple-stage decimator. This work describes the design and implementation of the first-stage decimator. The inputs of the system come from a Delta-Sigma modulator. This Finite mpulse Response filter takes 024 inputs, multiplies them with their coefficients and adds the results. The main design task is to take the input data, which is unweighted single bit binary numbers at 56MHz, multiply each bit with the corresponding coefficient and add them to get a weighted multibit output at 20MHz... FR Filter System The so-called FR filter is a widely used filter in DSP. Mathematically, a sampled data FR filter is represented by:

17 2 m- y(n) = c. x(n- 0 i = 0 Where y(n) = the output of the filter x(i) = the input signal stream ci = the ith coefficient of the filter m- = the order or length of the filter n general, we can view the equation as a computational procedure (an algorithm) for determining the output sequence y(n) of the system from the input sequence x(n). There are a number of well-known forms for the sampled data FR filter. One form is shown in Figure.. t is the so called Direct-Form Structure FR. The system of a FR filter is mainly composed of registers, adders and multipliers when implemented with hardware. The precision of the adder and multiplier depend on the precision of the coefficient, the length of the filter, and the desired precision or result. The multipliers can be a costly component. f the filter response is fixed and the coefficients are therefore fixed, the multipliers may be simplified to contain only the product terms required. n fixed FR filters, a great deal of signal-processing expertise goes into designing the coefficients that reduce the number of additions efficiently.

18 3 OUT Figure. Direct-Form Realization of FR Filter Structure.2 Linear Phase FR An FR filter has linear phase if its unit sample response satisfies the condition c(n) = ±c(m n) n = 0,, M The system we are dealing with is a linear phase FR filter, so we can use this symmetry or antisymmetry characteristic to simplified the system. So the structure shown in Figure.2 is used for the design.

19 4 x(n) Delay Delay Delay Delay 2*C0 2*C2 2*C3 Delay Delay Delay Delay 40 y(n) Figure.2 Direct-Form Realization of Linear-Phase FR System.3 System Outline The oversampled bit-stream is clocked at 0 GHz. An intermediate multiplexer reduces the one-bit-stream at 0 GHz into 64-bit parallel data at 56 MHz. The final output of the FR filter will be clocked at 20MHz. As a result the system will have to work at a high speed. There are two main obstacles for the design. One is to finish the large amount of multiplication and addition within a relatively short period of time, the other is managing the large amount of data flow. Several main design methods are taken here to achieve the above mentioned goals. They are:. XOR reduces the number of additions at the first step.

20 5 2. AND gates implement the multiplications. 3. Wallace Tree structure reduces the large number of additions. 4. Combination of carry select and carry lookahead does the final addition. 5. Pipelined structure manages the data flows. There are three basic circuit elements used in the design. They are: D flip-flop, XOR, and full adder. Besides these three repeatedly used elements, there are some other circuit macros, such as the carry lookahead and carryselect macro, which are also used in the implementation of the filter. n this design, since the whole circuit consists numerous number of repeating macros, the optimally of each basic cell can contribute greatly to the overall performance of the circuit. Using the minimum number of transistors for the basic macros can reduce the parasitic capacitance for the circuit, which will contribute not only to lower power consumption, but also benefit the delay. Spice simulation and first step layout have been done for the basic elements of the circuit in order to estimate the overall chip area and circuit performance. Powerview was used to set up the schematic structure for the design. Logic simulation has been done for the macros of the system..4 Organization of the Document Chapter 2 presents the overall structure of the system. Chapter 3 explains the design of the D flip-flop and shows the simulation results of its main characteristics. Chapter 4 explains the design of Full Adder and discusses the affect of temperature variation, power supply variation and transistor size optimization on its delay. Chapter 5 presents all the function blocks of the system and discusses the different structures of Wallace Tree. Chapter 6, gives the conclusion of the design and some suggestions about the future work.

21 6 Chapter 2. Overall Structure of the System A general electronic system is a black box that performs a desired input/output transformation. A digital system has its input and output coded in binary format. Like any other digital system, our design accepts certain binary inputs and produces certain outputs. The inputs for the system are 64 unweighted bits in parallel at 56MHz. The output for the system is one multi-bit word at 20MHz. The transformation of this system (56M) involves taking these 64 = 024 inputs, multiplying them with the 20M corresponding 20-bit 024 coefficients, and adding the results together. The final output is a 30 bit words. Many times digital systems are advantageous because they can be partitioned into modules. Each module can be built with cells which act as the building blocks. The main modules of the system are: the input part, including the shift register block and the latch register block; the pre-processor part, including the XOR block and the AND block; and the addition part, including Wallace Tree and carry-look-ahead & carry-select block. lr 64 in 56 MHz 024 Shift 56 MHz Latch 20 MHz unweighted bit stream MUX and AND Matrix bit words positive Wallace Tree & Negative Wallace Tree wo negative 28-bit words i two positive 28-bit words carry-look-ahead & carry-select adder i30 20 MHz Figure 2. Overall Structure for the System

22 7 Figure 2. is the block diagram for the overall structure of the system. These blocks can be divided into three parts: the inputs part, the pre-processing part, the processing part. This chapter will describe the blocks in each part individually. 2. nput Part The input part reads in the input data and converts them to certain data form that is appropriate for the data-processor of the system to deal with. Shift register block and latch register block are used in this part to achieve the goal. 2.. Shift Register. The inputs of the system are 64 unweighted bits at 56MHz in parallel. The system needs to take in 024 input data, then do the data processing every 5Ons The shift register block reads in the 64 parallel inputs every 6.4ns shifts them down and stores them in 64 register levels. So the shift register block is composed of 64 levels of register cells. Each cell contains 64 DFF's in parallel. All the registers in this block work at 56MHz Latch Register Since the clock for the output is 20MHz, the MHz input needs to be latched at 20MHz and sent to the next stage in parallel. The latch register reads the outputs of the 64 x 64 matrix shift register every 5Ons, and sends them to the next stage in parallel.

23 8 2.2 Pre-Processor Part The large number of data is a big obstacle for the design. Pre-processor makes use of the characteristic of the system and reduces the number of inputs before the main data-processor. By this, the size of the addition part can be reduced dramatically. The blocks in this part are the XOR block and the AND block. The XOR block reduces the number of input data entering the filter, the AND block does the multiplication for the filter XOR The coefficients of FR filter are symmetric, i.e. C(i) = C(n i) or antisymmetric, i.e. C(i) = C(n i). We can use this characteristic to try to reduce the number of data that the processing part. f the inputs are symmetric, i.e.!nw@ N (n i) = 0, the multiplications and the addition of the two multiplications will give 2 x C(i) or 2 x C(n i). f they are anti-symmetric, i.e. N (i) N (n i) =, the addition of the two multiplications will produce a zero. Based on this, we add a XOR block before the filter itself to find if the coefficient is symmetric or anti-symmetric. This XOR block compares coefficients in parallel and drives the AND block AND The multiplication is done by bit to bit AND-gates, which are equivalent to 2 to- muxes. The input of the mux are individual bits of the coefficience x 2, whichare ready for the chip and the outputs of the XOR' s.

24 9 2.3 Data Processor Part The Data Processor Part is the main part of the FR filter. t contains the addition of all the outputs from the multiplications. t begins with the Wallace Tree structure, and uses the carry-look-ahead and carry-select adder to do the final addition of the output from the Wallace Tree Wallace Tree Wallace Tree structure provides the structure for additions. Based on the manageability and speed trade-off, two basic counters (5,4) [5-to-4] and (3,2) [3-to 2] are used. t is assumed that the coefficient of the filter are evenly distributed positive and negative numbers. Wallace Tree can not deal with the sign-bit. So the data is grouped into positive and negative group numbers, the sign bit information will be kept for the final addition. But practically, the sign of the coefficient of the filter is random. Duplicatation of this design and some minor changes can be done to achieve this. Section 5.4 discusses this in detail. The Wallace Tree compose several levels that can convert bit number to 4 28-bit numbers gradually Carry-Select and Carry-Look-Ahead Adder The Carry-Select and Carry-Look-Ahead Adder takes four 28-bit output from Wallace Tree, along with the sign bits, and calculates the sum of these four 29-bit

25 0 numbers. Carry-select and carry-look-ahead are used in this block to achieve higher speed. 2.4 Summary The chapter briefly describes the overall structure of the digital filter. The detail functionary and performance will be described in later chapters.

26 Chapter 3. Full Adder 3. Full Adder A full adder is a combinational circuit that forms the arithmetic sum of three input bits. t consists of three inputs and two outputs. Two of the input variables are the two bits needed to be added. The third input is the carry out from the previous lower weighted addition. These three inputs are equally weighted. Because the arithmetic sum of the three binary digits ranges in value from 0 to 3, two binary bits are needed for the outputs. One output has the same weigh as that of the three input bits, the other has a higher weight than that of the inputs. The truth table of the full adder is shown in Table 3.. Table 3. Truth Table for Full Adder nputs Outputs A B C S COUT The eight rows under the input variables designate all possible combinations of 's and 0's that these variables may have. The 's and 0's for the output variables are determined from the arithmetic sum of the input bits. When all input bits are 0's, the

27 2 output is 0. The S output is equal to when only one input is equal to or when all three inputs are equal to. The C output has a carry of if two or three inputs are equal to. So the truth table gives one simple definition about full adder: a full adder finds the number of ones in the inputs, and gives that number in binary form. Thus, it is actually a 3-to-2 counter. The schematic of a full adder using static CMOS complementary gate is given in Figure 3. _J Ac Cci C CARRYX SUMX B BH Figure 3. Complementary CMOS Full Adder

28 3 3.2 The Comparison of Static CMOS Adder and Transmission Gate Adder Besides the static CMOS full adder, a different implementation of adder uses a novel exclusive-or (XOR) gate. The schematic for this XOR gate is shown in Figure 3.2. L B A EB B Figure 3.2 Transmission Gate XOR With XOR, inverters and transmission gate, a full adder may be implemented as the Figure 3.3. The SUM (A Gs B C) is formed by a multiplexer controlled by A ED B. f a second thought is given to the truth table of full adder, it can be found that Carry=Cin when A ED B =, and Carry=A (or B) when A ei B = 0. This adder has 24 transistors, the same as the complementary one, but the Carry and Sum have the same delay. n addition, the Sum and Carry signals are noninverted. The disadvantage of this structure is that the delay is much worse than the static CMOS design according to 0.

29 4 H. L JL C L SUM CARRY 0 L Figure 3.3 Transmission Gate Full Adder 3.3 Static CMOS Full Adder Simulation There are several factors that affect the circuit performance. Simulations are done with regard to the effect of temperature, transistor size and power supply variations The Affect of Temperature on Circuit Performance The circuit performance is largely decided by the -V characteristic of the transistors used in the circuit. The delay, for instance, is decided by the charging or

30 5 discharging current of the output node and the parasitic or real capacitance of that node. For the MOSFET used in this design, the -V characteristic is: 0 <V ds<vgs-vt V gs> V t / d = K [(V -V ) V V ds] w 2 L gs t ci_, s 2 d, = K---7(7 V )2 2 L gs t V ds> V gs-vt V gs> V t d = 0 V ds?- V gs< V t n the above equations, K = ii,cox, where ti is the mobility of the carrier of the MOSFET, Cox is the capacitance density (capacitance per unit area). Both.t. and V t are heavily temperature dependent, while they have opposite affect on the -V characteristic. i.t is the mobility of the channel. There are two collision or scattering mechanisms that dominate in a semiconductor and affect the carrier mobility: lattice scattering and ionized impurity scattering. For the channel mobility of MOSFET, lattice scattering is the main mechanism because of the low impurity concentration. The lattice scattering is related to the thermal motion of atoms. To the first order approximation, gat ED So the temperature coefficient for the channel mobility.t is negative, i.e. the mobility increases as the temperature decreases.

31 6 On the other hand, the threshold voltage is a function of temperature too. The absolute value of the threshold voltage decreases with an increase in temperature. This variation is approximately -4mv/ C for high substrate doping levels, and -2mv/ C for low doping levels. So the affect of temperature on the circuit depends on the combination of the two factors. n oder to get a rough feeling about the affect of these two factors, the following calculation is done to compare the time for a inverter's output node drop from 5v to 4v under 25 C and -220 C.When the output of a inverter drops from 5v to 4v, the pmos is in cutoff region while the nmos is in its saturation region. The saturation current of the nmos provides the discharge current for the node. Where: W/L = 3/2 sat = ( / 2) (W /L) K (V V t)2 K = it Cox = 84(/V2) (V V t) = = 4.3 So the /sat = 200p.. For discharge current, At = (AQ)/ = (AV C)//, if the load capacitance is 50fF (a typical gate capacitance for a inverter), the discharge time is approximately 0.04 ns under room temperature. f the temperature is -220 C, according to the above discussion of temperature affect on Vt and, the Vt will be approximately.5v, while

32 7 84 (-3/2) the K will be 53 = (-3 /2) 234(µ/V2), so the resulting /sat = 000µ, 300 which will result in a decrease in discharging time about 0 times. From the above discussion, it is obvious that the temperature drop will speed up the circuit. Simulations use the following stimulus under different temperatures to verify the effect. Table 3.2 Stimulus to Simulate the Affect of Temperature on FA Delay ain bin cin time point sum cout ns ns ns 0 40 ns 0 50 ns ns ns ns 0 Table 3.3 Delay of FA with Minimized Transistor Sizes T=25 C T=-220 C a (b) cin a (b) cin sumb up edge 0.97 ns 0.80 ns 0.68 ns 0.80 ns down edge 0.2 ns 0.28 ns 0. ns 0.09 ns

33 8 Table 3.3 Delay of FA with Minimized Transistor Sizes T=25 C T=-220 C coutb up edge.38 ns.56 ns.40 ns.60 ns down edge 0.29 ns 0.35 ns 0.6 ns 0.8 ns goes down. From Table 3.3, the delay of the circuit does decrease while the temperature The Affect of Transistor Size on Circuit Performance The sizes of the transistors in the circuit affect the circuit performance because they affect the -V characteristic of the MOSFET. Generally speaking, the large size gives larger current under the same nodes' voltages, which means a stronger driving ability. But a larger size transistor means a larger load for the stages that drive it. So the affect of the sizes for the transistors on the circuit performance is not a straight forward relation. Table 3.4 Delay of FA with Optimum Transistor Sizes T=25 C T=-220 C a (b) cin a (b) cin sumb coutb up edge 0.76 ns 0.65ns 0.68 ns 0.60 ns down edge 0.4 ns 0.25 ns 0.0 ns 0.09 ns up edge.2 ns.22 ns.08 ns.30 ns down edge 0.29 ns 0.25 ns 0.6 ns 0. ns

34 9 The simulation results show that the speed of the full adder relies on the sizes of the transistors in the circuit. The "optimum size" taken here is from. The optimum may not be suitable for the circuit, but it does give some idea that the size of the transistor affects the circuit performance. A variety of software packages have been developed to aid in the optimization of transistor sizes The Effect of Power Supply Variation on Circuit Performance n an C chip, the variation of power supply is very normal and usually within the range of 0%. Generally speaking, the increase of power supply means large current for the same transistor, so that will make the circuit faster. Simulation is done using the same stimulus shown in Table 3.2 on page 7 while the VDD is changed from 4.5 to 5.5v. The simulation results are shown in Table 3.5. Table 3.5 The Delay of FA with Vdd Variation Output Edge nput A or B Carry nput 4.5 V 5.0 V 5.5 V 4.5 V 5.0 V 5.5 V Sb Up.3 ns 0.98 ns 0.85 ns 0.98 ns 0.80 ns 0.65 ns Down 0.24 ns 0.22 ns 0.7 ns 0.29 ns 0.28 ns 0.27 ns Cb Up.75 ns.39 ns.3 ns.95 ns.58 ns.30 ns Down 0.30 ns 0.29 ns 0.27 ns 0.28 ns 0.35 ns 0.30 ns Simulation results verify that the delay of the circuit decreases as the power supply goes up.

35 Summary From the simulation and discussions in this chapter, the complementary CMOS full adder is the choice for the design. The average for this full adder is approximately 0.8 ns using 0.8 um CK processing in SS. The delay of the circuit decreases as the temperature goes down. The optimization of the sizes for the transistors in the circuit will increase the performance of the circuit, which can be achieved by some software simulation. The power supply variation affects the circuit performance: as the power supply goes up, the delay of the circuit drops. But with all the variations, the full adder used in the design can have a delay less than.2 ns, which is equivalent to 800 MHz.

36 2 Chapter 4. Design and Simulation of D Flip Flop 4. Sequential Circuits Sequential circuits have memories so that the output signals can be function not only of the present input signals but also of past ones. Often, in sequential circuits, output signals are fed back. Thus, an output signal can be a function, not only of past input signals, but also of the past output signals. So a sequential circuit can be considered to consist of the interconnection of a combinational circuit and a memory. Sequential circuits are so named because they allow operations to be performed in sequence. Sequential circuits are usually slower than combinational circuits because the operations have to be performed in sequence. However, the modem large digital computer, or even most small computer applications must have memories to function properly. Thus, sequential circuits are of prime importance in modem digital devices. Sequential circuits are classified into two types, synchronous and asynchronous. n synchronous sequential circuits, the signals only change their values at discrete times, that is, they all change in synchronism. Pulses are generated by a device called a master clock. The master clock pulses synchronize the operation of all the devices within the digital device. n general, different types of digital circuits respond at different rates. The rate at which the master clock generates pulses must be slow enough to permit the slower circuit to respond. This then limits the speed of all circuits.

37 22 n an asynchronous sequential circuit, each device responds at its own states. Therefore, in general, asynchronous circuits are considerably faster than sequential ones. The system designed here is a synchronous sequential circuit with the input speed at 56MHz, while the speed for the overall circuit is 20 MHz. 4.2 Flip-Flops A very basic sequential circuit is called a flip-flop or latch. This is a digital device whose output remains constant (i.e., either a 0 or ) until it is switched in response to its input signal. This accounts for its name: that is, it flips or flops from one possible output to the other and remains there until flipped back, or, equivalently, latches at one output until changed by the input. There are different kinds of flip-flops. A general block diagram representation is shown in Figure 4.. One or more inputs Q Outputs Q QB QB Figure 4. Block Diagram for a Flip-Flop. The value of the output marked Q is called the state of the flip-flop. That is, when Q=, then the state is and when Q=0, the state is 0. Flip-flops usually have two outputs, one equals the state and the other equals its complement. The complement output is marked as QB.

38 23 Once the state of a flip-flop is set, it remains this way until changed by the input. Thus, a flip-flop "remembers" its inputs. 4.3 D Flip-Flop The D (delay) flip-flop has only one input. The levels of a clock, CLK, are used to drive the D flip-flop (DFF) to either the storage state or the input state. f D is the input signal, Q and Q' are the CLK and CLK, the state equations for positive and negative level-sensitive latch can be expressed as Q' = D CLK + Q CLK and Q' = D CLK + Q CLK The first equation describes a latch which passes the input data when CLK = and stores it when CLK = 0. nversely, the second equation describes a complementary latch, which receives input data at CLK = 0 and stores it at CLK =. f two complementary latches are connected in series, one will be in the storage state while other is in the input state and a 'non-transparent' edge triggered flip-flop is formed. One well-known structure is called the master-slave D flip flop. The master stage reads in the input state when the clock is low (high), while the slave stage passes the input state to the output when the clock is high (low). One structure that makes use of the transmission gate is shown in Figure 4.2. As can be seen from the circuit, the master and slave stage will remain isolated as long as

39 24 the clk and clk2 are not high simultaneously. The negative feedback loop keeps the state of the master and slave stage latched as long as the clock does not have another upedge or down-edge. At the up-edge of the clock, the master stage reads the input, while the slave stage passes the input state to the output at the down-edge of the clock. So this kind of flip-flop is called edge-trigger DFF. clacl clk2 OUT clk2 x clkl Figure 4.2 Static CMOS D FLP FLOP 4.4 CMOS Static DFF Simulation 4.4. The Comparison of Three Kinds of Transmission Gate DFF The transmission gate in the above structure can be a single NMOS or single PMOS transistor or CMOS transmission gate. Due to the working characteristics of these three kinds of gates, the working performance and the highest working frequency for them will be very different.

40 25 n order to find out the working characteristics for NMOS, PMOS and CMOS transmission, the following setups are used. CLK VNP () r_40utp VN CLK CLK VNN HVOUTN Figure 4.3 Test Circuit for Different Kinds of Transmission Gates For NMOS transmission gate, when the CLK = 0, the gate is open, the VOUTN keeps its old state. When CLK = VDD, the gate is closed, the stable voltage for VOUTN depends on the voltage level of VNN. f VNN = 0, the resulting VOUTN = 0 ; if VNN = VDD, the resulting VOUTN = VDD VT. Most of the processing are n-well processing, so the bulk node for NMOS can only tied to Ov, which means the VBS = VDD V = 4.3v this VBS will form a negative feedback on the VNN (body-effect). vt = vg) + /2 G j 27..Ts), /Vbs + 2 where vto = 0.7v, = 0.3v. So the resulting Vt =.5v, this will pull the VNN =3.5v. So the NMOS transmission gate can only transfer voltage between 0 to 3.5v. f this kind of transmission gate is used in the circuit, the noise margin for the next stage will be largely reduced. An even worse thing is that if these kinds of transmission gates were

41 26 used in series, this body-effect would become worse and worse along the transmission gate chain, and ultimately kill the initial signal. For PMOS transmission gate, this body-effect can be eliminated by connecting the bulk node of PMOS with its source node. This is because most of the processing are n-well process, so the bulk node for each PMOS can be tied to its own voltage instead of tied together to certain voltage. So the PMOS transmission gate has better voltage performance than NMOS. The second factor that must be taken into consideration when choosing the transmission gate is to find out the highest working frequencies for them. n order to do this, different kinds of clocks are put into the DFF's composed by each of these three kinds of transmission gates, increase the clock frequency gradually until it fails, while the frequency ratio of the clock to input signal is kept at 2:. The result of simulation is summarized in Table 4. Table 4. Speeds of DFF With Different Transmission Gate Gate Type CMOS NMOS PMOS Highest Frequency 358M 357M 00M The simuation shows that only the CMOS and NMOS transmission gates have the required working frequency. Considering the voltage level problem of the NMOS transmission gate, the CMOS transmission gate is the best choice for the design.

42 Working Performances with Different Sizes of Transistors The working performance of the circuit is largely affected by the sizes of the transistors. n CMOS static circuits, a larger size transistor gives a larger current under the same gate voltages, which means stronger driving ability. But a large size transistor also means large load capacitance for the previous gate. Simulation is done with the design using minimized size transistors. Based on the waveform of the internal nodes, we increase the sizes of the driver transistors for the slower nodes, while keeping the faster node driver transistor at the minimum size. The optimum sized DFF can work up to 56MHz, while the minimum sized DFF can work up to 356 MHz. VCLK -C 6/2 C VN 0 J 8/2 L 0/2 8/2 >.70/2 4/2 VCLKB J L D- 0/2 6/2 8/2 4/2 Figure 4.4 CMOS Static DFF with mproved Size Transistors

43 Timing Simulation About DFF When using DFF, it is necessary to understand the timing of the various signals used in DFF. This is especially true when different components are interconnected. f gates are to function properly, then the clock signal must meet certain requirements. There are two such important specs about DFF, the setup time and the hold time. The setup and hold time of a register are the deviation from an ideal register caused by finite circuit delay. The setup time is the delay between the 50% whole voltage point of the incoming signal and the 50% whole voltage point of reading edge of the clock, i.e. the input must be set up at the 'setup time' before the reading clock edge. The hold time is the delay between the 50% whole voltage point of the reading edge of the clock and the 50% voltage point of the changing edge of the input, in order to get the input read in the DFF correctly. From the view of charge and discharge, setup time is the time to chargeup (or discharge) the input node to the right input state. f the input driver is an ideal voltage source, there should be no time needed to charge (or discharge) that node up. But in real circuits, this is the time for the driver which drives the DFF to charge (or discharge) it output node to the right state before the reading edge of the clock for the DFF. Hold time is the time to charge (or discharge) the internal node of the DFF to the right state, so it is

44 29 determined by the charge (or discharge) current and the parasitic capacitance of the internal nodes within the DFF. f the data of a register does not obey the setup and hold time constraints, a potential clock race problem may occur. This race results in erroneous data being stored in the register. are used: n order to simulate the setup time for the DFF, the input and clock in Figure 4.5 nput Clock Figure 4.5 DFF Clock & nput Relation The simulation is done by moving the up-edge of the input step-by-step towards the up-edge of the clock, until the operation fails. The simulation shows the setup time for the circuit is Ons for both T=25 C and T.-220 C, assuming that the node capacitance at the input point is 50 ff. n order to get the hold time for the circuit, the down-edge of the input is pushed backwards to the up-edge until the circuit fails to read in the right input.

45 30 Simulation gives a hold time to be 2.3ns for T=25 C and 2.4ns for T.-220 C, assuming the output node load is 50 ff. 4.5 Summary This design uses CMOS static DFF. t has Ons setup time and 2.3ns hold time. The DFF with PMOS transmission gate has a much lower speed than that with NMOS or CMOS transmission gate. The DFF with NMOS and CMOS can work up to 350MHz using. micro CMOS process, but the NMOS transmission gate has a very serious bodyeffect that can't be eliminated in n-well processing. So the CMOS transmission gate is chosen for the design. The size of the transistors in the DFF affects the performance of the circuit. But the optimum size isn't available due the limitation of tools. Consider a digital system containing many master-slave flip-flops, with the outputs of some flip-flops going to the inputs of other flip-flops. Assume that the clock pulse inputs to all flip-flops at the same time. At the beginning of each clock pulse, some of the master elements change states, but all the flip-flop outputs remain at their previous values. After the clock pulse returns to 0, some of the outputs change state, but none of these new states has any affect on any of the master elements until the next clock pulse. Thus the states of flip-flops in the system can be changed simultaneously during the same clock pulse, even though outputs of flip-flops are connected to the inputs of flip-flops. This is possible because the new states appear at the output terminals only after the clock pulse has returned to 0. Therefore, the binary content of the second is transferred to the first, and both transfers can occur during the same clock pulse.

46 3 Chapter 5. Function Blocks The system is composed of the following function blocks: Shift Register, Latch Register, Wallace Tree and Carry-look-ahead & Carry-select Adder. 5. Shift Register and Latch Register The first block for the system is 024 shift registers. This block latches the 64 unweighted bits in parallel for 8 times. So it comes as the matrix of 64 x 8 form. The inputs of the DFF work at 56MHz. The block that follows the shift register block is the latch register block. This block takes the 8 rows of 64 register output, converts them to 024 bits in parallel. The input frequency for this block is 20MHz. The schematic of this block is shown on Figure Wallace Tree When three or more operands are to be added together, the speed of the traditional carry-ripple adder is restricted by the carry ripples between bits. When the number of bits is large, the traditional carry-ripple adder becomes so slow that it can not be used in a speed sensitive system. Several techniques for these kinds of multiple operand addition that attempt to lower the carry-propagation penalty have been proposed and implemented. The technique that is most commonly used is carry-save addition. n a carry-save adder (CSA), the carry propagation is only allowed in the last step, while in all the other steps a partial sum and a sequence of carries are generated.

47 32 Therefore, a CSA is capable of reducing the number of operands to be added from 3 to 2, without any carry propagation. input 644/ Shift > Shift. > Shift > Shift --> Shift > Shift Clock -- > Shift 64 Latch Register 024 bit 20 MHz 56Mhz 20 MHz Shift 64 Figure 5. Shift Register and Latch Register Block

48 Carry-Save Adders A carry-save adder can be implemented in several different ways. n the simplest implementation, the basic element of the carry-save adder is a full adder with three inputs, x, y, and z, whose arithmetic operation can be described by: x2i+y2i+z2i = c2i++s2i where x, y and z are the inputs of CSA with 2i weight c and s are the outputs of CSA with 2i + and 2i weight t is obvious that the full adder is a (3,2) CSA or counter. Besides (3,2) counter, there are (7,3) and (5,4),... counters. CSA can also be put in another way, that is CSA counts the number of ones in the same weighted multi input and output the counted number in binary data form. Figure 5.2 gives some real number examples for these kinds of CSA.

49 (3,2) (7,3) (5,4) Figure 5.2 Examples of Single Bit CSA The structures for these basic counters are shown in Figure 5.3. The real implementations for these counters are shown in Figure 5.4 and Figure 5.5. OEM (3,2) counter (7,3) counter (5,4) counter Figure 5.3 Counters

50 Figure 5.4 (3,2) and (7,3) Counter Structures 35

51 36 N [0 4] \+/ c2 C i: ith weight Delay: Five FA Delays Figure 5.5 (5,4) Counter Structure

52 Wallace Tree f the operands for the CSA or counters are multi-bit words, a way to organize the operations is a tree commonly called Wallace Tree. Similar to the single bit CSA, the multibit CSA counts the number of ones in the same weight bits separately without caring about the carry ripple from the lower weighted bits. Figure 5.6 is an example of Wallace Tree dealing with real multi-bit numbers : 7 al 0 8 D. rl 0 24 o o o o Real Number Form Binary Form Figure 5.6 Example of Multi-Bit Wallace Tree Figure 5.7 gives a three 20-bit Wallace Tree, three 20-bit number can be reduced to two 2-bit numbers in one full-adder delay. Figure 5.8 shows a 20-bit (7,3) Wallace Tree, seven 20-bit numbers can be reduced to two 22-bit numbers in four full-adder delays, Figure 5.9 shows a 20-bit (5,4) Wallace Tree, fifteen 20-bit numbers can be reduced to two 22-bit numbers in seven full-adder delays eoso ) C) 4 0 C) P ) C) C) , ) 4 0 () Three 20-bit words N.-Two 20-bit words Figure 5.7 Three 20_bit Wallace Tree Structure

53 38 6)0006 6toeoo & e) & &0e e) &oeooe e) oeleeoeeee) & D f word 22-bit one and word delays 20-bit One adder full Structure words-p. is four Tree 2-bit delay Wallace Seven Total 20-bit Seven 5.8 Figure

54 39 QD C2 GO 0 0) 0 0 QD 0) CO GO QD 0) 0 GO 4 Q5 D 6) 40 CO ) C2 GO 0 0) C2 0 QD ) C ) ) C2 GO QD 0) 4 e ) CO GO 0 0) 0 GO QD 0) CO 0 0 0) E) 4 OD C2 GO Q) Q) C2 0 QD 0) CO 0 0 0) 0 GO 4 Q5 4, 6) QD C2 GO QD 0) CO 0 0 0) CO ) 0 GO 0 0) 0 GO 0 0) 0 GO QD 0) 40 e QD f ) 0 GO 0 0) 0 GO 05 0) CO E) 4 OD f2 GO 0 0) 0 GO 0 0) 0 GO 0 0) C2 GO 0 4 6) Q) C2 GO QD 0) C2 GO 0 0) 0 GO 0 4, ) C ) 0 GO 0 0) 0 GO QD 0) 40 e 4 C ) C2 GO 0 0) CO GO 0 0) E) GO 0 Q) 0 GO 0 0) 0 GO 0 0) 0 GO 0 40 & 4 o GO 0 0) C2 GO GO 0 0) 0 GO ) C2 GO 0 0) C2 GO 0 0) 0 GO 0 0) 40 e ) CO GO 0 o GO 0 QD f2 0 0) :,) GO 0 0) C2 GO 0 QD CO 0 0 0) C5 S 6) C5 40 Q) C2 GO 0 0) C2 GO 0 0) G7 GO 0 0) G7 40 lb 4 40 GO 0 0) C2 GO GO 0) e2 co QD 0) 0 GO 0 0) C2 0 0 GO QD 0) CO GO QD 07 0 GO 0) C2 GO 0 QD CO GO GO QD CO G7 OD CO GO 0 0) CO GO QD C2 GO Q) 0 0 GO GO el f2 GO GO 0) C ) 0 GO 0 GO GO 0) f ) C2 GO 0 QD f D 4 40 lb Fifteen 20-bit Words --pp- Two 24-bit Words Total delay: 5++=7 Seven Full Adder Delays Figure 5.9 Fifteen 20-bit Wallace Tree Structure

55 40 n Wallace Tree, the number of operands is reduced by a factor of 2/3 at each level if the basic (3,2) counter is used. Consequently, Number of levels log ( k/ 2) log(3/2) This equation only provides an estimation of the number of levels. f different kind of basic counters is used, the level number may vary Sign-Bit in Wallace Tree Wallace Tree is very efficient to reduce the number of additions. The basic element for this structure is the counter, which causes some problems. As indicated by the name, counters only count the number of ones in the inputs, so they won't take care of the sign bits. So if the counters are used to deal with signed numbers, some pre-separation has to be done to separate the positive and negative numbers. Then the counter can be used to deal with each group separately. The results are four numbers, two of them are positive, two of them are negative. These numbers should be reunited with their sign bit information to recover the right numbers. For this design, the inputs of the Wallace Tree are signed binary numbers. For simplicity, it is assumed that the inputs are evenly positive and negative. So the Wallace Tree is divided evenly into two parts, positive part and negative part. But this is seldom the case. The worst case is all the numbers are positive or all are negative.

56 4 The following adjustments can be done in order to make the circuit work in that case:. Use XOR at each of the inputs to decide which block, positive or negative block, the input should be sent to. Meanwhile send a zeros to the non-chosen block. 2. Duplicate the structure in both positive and negative blocks to make sure the circuit in each block can deal with 52 numbers instead of 256 ones. Due to the duplication, the Wallace Tree will need two more three 20-bit to two 2-bit layers at the end of the positive and negative blocks. So Wallace Tree can be used for the addition of signed numbers at the price of larger hardware implementation Structure Trade-Off for Wallace Tree When parallel additions are done, there are several basic circuit elements to choose from, (3,2), (7,3), (5,4), etc. How to choose the basic element is a trade-off between the simplicity of the circuit and the total time required to finish the calculation. As shown in Figure 5.0, if the (3,2) counter is used instead of the (5,4) counter as the basic element, the total delay is only 6 full adder delays instead of 7 full adder delays. But as also seen from the two structures, using (5,4) as the basic element makes the structure simpler and easier to manage. n this design, two kinds of basic elements are used. (5,4) is used in the top level of the Wallace Tree to reduce the large number of inputs, while (3,2) is used for the following levels when the number of additions is reduced to amore manageable number.

57 GO ) 0 GO 0 0) ) 0 GO 0 0) ) ) 0 GO GO 0) OD GO 0 OD 0 GO 0 0) 0 GO 0 0) 0 GO 0 0) 0 GO 0 40 it 4i ft it 4i go P P P 40 4 it i t it it 4 ft go P ft 40 e) e) c) e) e) e) o c) e) e) e e e) c) 0 e) e) e e) e) e) e) () e) e) c) e) o D lb ) ) GO OD 0 GO 0 0) 0 42

58 40 Figure Fifteen 0 Continued 0 Total 0 20-bit words o o o , OD o , is , delay six One full 2-bit , D i) Q) ) adder word and , delays , 4, 4 e one 22-bit words tt 4 4 4/ 4 o / o

59 Carry-Look-Ahead and Carry-Select Adder The outputs of the Wallace Tree are two positive 28-bit numbers and two negative 28-bit numbers. n order to add them to one 30-bit number, a 4-bit carry lookahead and carry-select adder is used. Four bits Carry-look-ahead Four bits Carry-look-ahead c(n-)=0 carry-select tc(n-)= C (n) S (n). Figure 5. Carry-Look-Ahead & Carry-Select Adder n Figure 5., one of the 'Four bits Carry_look_ahead' does the addition assuming the carry input from the previous bit is 0, the other one does the addition assuming the carry input from the previous bit is, then the carry-select selects the right output when the previous carry reaches this block. 5.4 Summary The input part of the system: shift-register and the latch-register blocks, converts the inputs to the data form that can be dealt by the system. Wallace Tree does the large amount of additions for the system, with the help of the pre-processing part to deal with the sign bit. The cost of this may be twice the hardwares for the realization. Traditional adder is still needed at the end of the Wallace Tree to get the final single multi-bit word.

60 45 Chapter 6. Conclusion 6. Conclusion From the design and the simulation, 024 data points enter the designed FR filter in the form of 64 bits in parallel at 56 MHz, and the system transfers the information into one single 30-bit word at 20MHz. Since the data flow for the system is all pipelined, the highest speed the system can attain is /(one FA delay), which is about 300MHz. There are about 200 DFF, 024 XOR, 024 AND, 3000 FA and 32 4-bit carrylook-ahead adder. The estimated area for the gate layout is about 65 mm2. f considering the pads and the routing area to be twice the area of the transistor area, the total die size will be around 00 mm Future Work This design is based on the assumption that all the coefficients are un-signed, if the coefficients are signed binary numbers, the whole structure can be duplicated to do that. This design uses some (7,3) (5,4) to do the Wallace Tree; the speed can be further increased by using (3,2) to do the Wallace Tree. This will require more detailed design of more circuit levels.

61 46 Based on the tree structure of Wallace Tree, the basic floorplan can take the square form, with the input at the outerside of the chip and have the output generated at the center of the chip. The chip area for the successive levels shrink in accordance with the shrinkage in the amount of data or adding for each levels.

62 47 Bibliography West, Neil H. E. and Eshraghian, Kamran Principles of CMOS VLS Design, Addison-Wesley Publishing Company. 2 Waser, Shlomo and Flynn, Michael J ntroduction to Arithmetic for Digital Systems Designers, Holt, Rinehart and Winston. 3 Geiger, Randall L., Allen, Phillip E. and Strader, Noel R VLS Design Techniques for Analog and Digital Circuits, McGraw-Hill. 4 Neamen, Donald A Semiconductor Physics and Devices Basic Principles, RWN. 5 Mano, M.Morris, 992. Digital Design, Englewood Cliffs, N.J.:Prentice Hall 6 Proakis, John G. and Manolakis, Dimitris G., 996. Digital Signal Processing Principles, Algorithms and Applications, Englewood Cliffs, N.J.:Prentice Hall. 7 Lu, Shih_Lien and Ercegovac, M., Aug "A novel CMOS implementation of double-edge-triggered flip-flops," EEE J.Solid -State Circuit, vol.25, pp Koren, srael, 993. Computer Arithmetic Algorithms, Englewood Cliffs, N.J.: Prentice Hall. 9 Chirlian, Paul M., 987. Analysis and Design of ntegrated Electronic Circuits, second edition, New York.: Harper & Row, Publishers. 0 Lu, Shih_Lien, ECE Department, OSU, Comment on "A New Design of the CMOS Full Adder", to be published. Swartzlander, Jr. Earle E., 992. Parallel Counters, EEE Computer Arithmetic, vol., pp

63 Appendices 48

64 49 Appendix A Hspice Simulation Results

65 PGPcL C CD" VAC> VBC> - VCD> co (PS) 9 A (PS) PGP W=3u L=2u (P C.) O PGP M M2 M7 M M2 M3 'GP PCP PCP W=3u PGP 'GP W=3u. W=3u L=2u L=2u L=2u (PS) V W=3u L=2u (P) W=3u L=2u (P) M3 M8 M PGP W=3u PCP W=3u PGP W=3u L=2u L=2u L=2u (P (P VCB cn cn M9 M5 NGP W=3u L=2u (N N (P (P ) NGP W=36 L=2u E>VC3 NGP W=3u L=2u (P (P ) W=3u L=2u M5 MS M0 Ml j M7 M8 YGP W 3u NGP w=3u NCP wr3u NCP Wr3u NCP W=3u NCP W=3u L 2u L=2u L=2u L=2u L=2u L=2u (NS) (N ) (N ) (NBODY-5 (N ) (NM M20 (P W=3u =2u M2 PGP W=3u L=2u (P M22 NGP wr3u L=2u (N M23 NCP W=3u L=2u (N M2 NGP W 3u L=2u (N C>VSB (NS) Full Adder with Minimized Size Transistors

66 DO:AO:va X DO:AO:vcb 4 DO:AO:vsb _i_ -, i, ' - Panel -, fa simulition with MM siz at T.-220C z 2 _ li n 00n 50n 200n Time (lin) (TME) 250n 300n 350n 40C Wave D0:A0:vb DO:AO:vcb ( DO:AO:vsb A Sysitc Panel n 00n 50n 200n Time (n) (TME) Panel 3 250n 300n 350n 40C Wave D0:A0:vc DO:AO:vcb DO:AO:vsb A Symbol 0 T 0 50n 00n 50n 200n 250n 300n 350n 40C Time (lin) (TME)

67 52 Panel Wave Symbol DO:AO:va /, fa with min size at T=25 V=5.5v DO:AO:vsb DO:AO:ps n 00n 50n 200n Time (lin) (TME) 250n 300n 350n 40C Wave Symbol DO:AO:vb r DO:AO:vcb Panel 2 4 > 2 0 _ 0 50n 00n 50n 200n 250n 300n 350n Time (lin) (TME) WaveM DO:AO:vc DO:AO:vsb Panel n 00n 50n 200n 250n 300n 350n 40C Time (lin) (TME) Figure A.3 Full Adder Simulation with Minimum Sized Transistors(25C, 5.5V)

68 PGPciL =2u VAC> VBC> VCC> (PS) A (PS) M9 W=3u (P PGP M (P ) W=32u Lr2u V PCP 2 (P ) W-32u L-2u PCP 7 W=3u L=2u (PS) M W=3u L=2u (Kr M3 M8 M M2 W=3u L=2u (Ps) M3 W=3u L=2u (P M20 PGP W.3u L=20 (P M2 PGP NGP (N W=32u L=2u M w=isu L=2u PCP NGP (P W=3u L=2u M9 W=3U L=2u N VCB PcPcW=3u L=2u (P M5 E> NGP W=3u VC 3 L=2u NGP PGPciW=3u L=2u (P M22 W=3u L=2u (N C>VSB 23 JGP M5 W=6u L=2u NS) MG NGP W=Gu L=2u L_ (NS) M0 NGP. W=3u L=2u (N M6 M7 NGP 73) NGP W=3u L 2u L=2u (NBOD''T (NS) M8 NGP 73u L 2u (NST NGP (N W=3u L=2u 2 NCP 4=3u L=2u (N (NS) Full Adder with Optimum Size Transistors

69 Y8u (PS) VOLKE> (PS) VNE> 7 L, Va VOUT -J; VB VOUT 6 VOLKBEE> pcd (P > (NS) (NS) (PS) 2u, =2u.= ' NGP.- M20 M 9 M9 VC W=6u L=2u s) PCP (P =2u wr s.j8u 'CP NCP M7 M8 VOUTB mio W=lu L=2u NCf (NS) NS) y (NS) DFF with mproved Size Transistors (NS)

70 Panel _Wave symbol DO:AO:vin >E-- 5 /'. \ \ 00:AO:vout ( t / / / \ / 4.5 \ / / ernes DFF 456M T=-90C(lowest) for W/L= u/2p(pmos) W/L- u(nm s) [static) 4 / _ a> 2 3. i / 500m / / 4. / 0 _ \ \ / / / l / _ r V' -,/ r -, '-- 2n 4n 6n 8n 0n 2n 4n 0 Time (lin) (TME)

71 VVave_Symbo Do:Ao:vin X DO:AO:vout ( -4 5 \ /,- H \ / Panel / 4.5 / ) i NMOS tic OFF 56M down to -50C r, h NMOS W/L=8ur2p -\ \ i 3.5 t \ a> i i i ;.5 500m / / i i \ \ / ) \ \ i / i f 0 i,-, -r 2n 4n 6n 8n Time (lin) (TME) 0n 2n 4n

72 Panel W a a Arta % \ DO:AO:vout (_-) / \ \ i \ 4.5 NMOS static DFF 56M down to -304v \ th NMOS W/L=4u/Tu 4 \ ' 2.5 g 2 t.5 i 500m / / \ \, / \ \ \ \ i / 0, i ' ' f 0 2n 4n 6n 8n Time (lin) (TME) 0n 2n 4n

73 ', Panel ---,M --.M MD =M. Mi i Maar WOW SO. MS MO = N=p 6- m M M M Wava SymboL DO:AO:out *...'S,%...A DO:AO:in ' i! o " ;, i!. it i,..,i i i i i. P.. p.,...., i i, 2 > i / i, i li i f i i i i i i i! i is i i %. i -n %MAN aas raw AWAT &rbe....= No rm.. wt.. :U6VEVONss no Airy warom0.04 YU Yea...- ow an.. or. mi :Will 0 f 2n 4n 6n 8n 0n 2n 4n 6n 8n 20n 22n Time (n) (TME) 24n 26n 28n 30n 32n 34n 36n 38n Wave _SymboL DO:AO:a DO:AO:n Panel 4 a 0, 2 0_ 2n 4n 6n 0 8n 0n 2n 4n 6n 8n 20n 22n 24n 26n 28n 30n 32n Mn 36n 36n Time (n) (TME) Panel 5 _Wave Symbo DO:AO:ck )(, DO:AO:ck2 ( 4 3 a ' r ' T 2n 4n 6n 8n 0 0n 2n 4n 6n 8n 20n 22n 24n 26n 28n 30n 32n 34n 36n 38n Time (lin) (TME) Static DFF with PMOS Transmission Gate (fmax=00m)

74 , ', Panel _...Wave_SymboL DO:AO:out DO:AO:in p / n ' \ \ i, \,, ri,, /, \ \,,/ `i l' / ''''''''.5n 2n 2.5n 3n 3.5n 4n 4.5n 5n 5.5n Time (n) (TME) 6n 6.5n / / in 7.5n \ \ ', 8n 8.5n 9n, / / 9.5n / Panel 4 Wave DO:AO:a DO:AO:n ( SymboL p in.5n 2n 2.5n 3n r n 4n f "---r 4.5n 5n 5.5n 6n Time (lin) (TME) "r"" 6.5n 7n ' n 8.5n 9n -- ' 9.5n Wave - Symbo DO:AO:ck DO:AO:ck p in.5n 2n 2.5n 3n 3.5n 4n 4.5n 5n 'llffl 5.5n 6n 6.5n 7n 7.5n an 8.5n 9n Time (lin) (TME) T--' 9.5n Static DFF with CMOS Transimission Gate (fmax=357m)

75 Appendix B Wallace Tree Structures 60

76 6 Figure B. MAC 0 Figure B.2 MAC 02 Figure B.3 MAC 03

77 62 Figure B.4 MAC , Figure B.5 MAC Figure B.6 MAC 2

78 63 Figure B.7 MAC 2 Figure B.8 MAC 22 Figure B.9 MACRO 3

79 64 Figure B.0 MACRO 4 Figure B. MAC 3 Figure B.2 MAC 4

80 Figure B.3 MAC Figure B.4 MAC 6 Figure B.5 MAC 7

81 66 Figure B.6 MAC lb Figure B.7 W3N20L20 lb lb 4 4 Figure B.8 W3N2OB

82 67 W3N2L20 Figure B.9 W3N2L20 W3N26L20 Figure B.20 W3N26L20

83 GO Q) S ) 0 CO Q) C Q) QD GO GO CO GO GO C9 S) 40 0 GO 0 0 GO 0 0 G GO 0 OD ? CO Q) C Q) GO GO a GO 0 Q) 0 CO CO 0 4 C9 40 6) GO 0 Q) CO 0 0 Q) GO 0 OD GO GO Q) Q) CO GO Q) GO CO 0 4 C9 6) GO 0 Q) GO CO Q) CO C 40 Q) CO Q) 0 0 S GO 0 OD 0 GO 0 0 GO 0 0 OD CO ip D GO 0 0) 0 GO GO 0 0 CO C5 0 6) Q CO 0 Q) 0 CO 0 Q) 0 CO P el at CO 0 0 a GO 0 Q) AG C9 OO W5N2OB 5 20-bit Wallace Tree Figure B.2 W5N2OB

84 O 0 GO GO G OD 0 4 GO o GO OD GO 4 OD a OD e OD GO GO o GO OD OD 0 6 o GO OD 0 G OD GO OD GO O OD OD OD GO O OD GO GO 4 P 4 0 GO O OD OD GO G 0 OD GO GO 40 4 OD 0 GO o 0 O OD GO OD Q) O 0 OD GO OD Q, 0 0 GO GO OD D Q) OD GO 0 0 OD GO OD GO 0 4 GO 43N20B MAC3 0 MAC4 D MACS MACE MAC7 GO MAC8 W9N2OB W9N2OB B.22 Figure

85 70 W3N20L20 W3N2OB W SS W ) ( V VS600 W3N2OB W3N2OB W3N2L20 W3N26L20 (2 (g) " " *(0( *00E MACR MACR WS,660000S)S6000VS *****04***00040** MACR e0000eeeleeooeeeoe000ee oeoeeooe)ee0eq000eeee oe)oe(d00000eeoeqooeeee MACR004 LEVEL ( to be continued) Figure B.23 Level

86 7 KEEP KEEP (Continued for LEVEL BEE) meacr" ooaeooe ooeo a co 000e MoACR MACRO2 MACR eGaiDeGOGOGG GO0 MACR03 MACRO4 LEVEL Figure B.23 Level (continued)

87 Appendix C Schematics of the Wallace Trees 72

88 ] 73 latc-024 E xclm-_024 T:-- T: m256 m256 `,7-77''7-,7 t 7r m9 mt S wic 256 enre bits->4(group) to le-veil 23,22mbJ bito->4(group).7.20bitm Trim=..." '7... -"nil : ilimmi krtveami W/s-nzoi, mill iw.30. Pamtl..242:6:= FR Figure C. FR Top Level Schematic

89 N sh N shlet.4 st A.Va vvr tomos az.. 00r /ow /442 K2 N odr N N N w+0u2 OUT( i c2 RR 42,6 ours xel NEW h ST -44 roe.,40744,4 Mt stir N h... OUT KO.3 0.-rr s ) SHFT024

90 75 SET N CLX plummuumpi impinimpulerwinvoi riarformarpoprigr. MO rigrisrprimgromori OUT[0.63: mmaill4.0."pliniaii rgi gra Era rdir. SHFT64 Figure C.3 Shift 64

91 RKKT OLOCt 0 t C44627 OUT[ 007(02.2..) COT(234.7.) 0 ( ) 0 ( O. "[...3) N( CLK HtS2.K,S ) O LATCH024

92 TM fliffiel CLK OTr[0:63 NCO: s S LATCH64 Figure C.5 Latch 64

93 78 A.00:63 E[0.63) A[64,273 3( W.. 2 re S.9 2 acer64 acor64 f OUT 6. OUT[0.633 OUT[ OUT[28.9].42. OUT92:2553 xor64 A[28.93 D[28:9 A[92.255] B[92.255] A(256.39] n[256s39] OUT[ OUT( JOUT( A(384:4473 B[ ] A(448,5] aco=64 3[448:5] X0R024 Figure C.6 XOR 52

94 79 8[0.63] CO 3 DO 8 B Fd D OUTO our 3. OUT2 OUT3 OUT4 OUTS OUT6 OUT7 At 40..%), J. LL OUTEO:63 4 Yours OUT0 OUT OUT Al OUT6 OUT7 OUT8 OUT9 0UT20 OUT3 00T2 lout4 OUT ,2'3 OUT22 OUT=3 JYC FLL 4 4 OUT24 YOUT25- YOUT2elfUT27 YUT28 OUT29 OUT30 tfsl OUT32 OUT33 UT 34 OUT35 OUT36 4l DUT37.i OUT38 to, but 9 OUT40 OUT4 OUT42 OUT43 OUT44 OUT45 lout46 OU847 WOWENMEMEWOMMOMME OUT49 OUT50 OUT5 OUW52 0UT53 OUT54 OU TS5 DO / OUT56 OUT57 OUTS 8 OUTS 9 our6 cl, 4 ss..., Your 6 i 4,,, OUT62 X0R64 Figure C.7 XOR 64

95 OO rn C0.0.. C OOOOO CO. C OO COO OOO OO C OOOOO.) OO OO.00. OOOOO 9 COS.3... C3 203 CO.( OOOOOOOOOOO C C.03. C OOOOO 3 CO = m32.6 Bill WW!ll OOOOOOOOOOO OOOOO 03 2= iiiiiittes,slistssistilitstt.0.47 S t OOOOO m3. OOOOOO 2 f f!ff!ffflif f 77 ) Willi 40i 7:44.; -eto OOO OOO 0.7gliii!iiit" m3 2 OOOOOO 3 OOOOOOOO OO 4.ast, me...0.9:9:7": <0iieante.:....;79Wffilli!! iiiilliiiliiiiiiiiiilliiiiii m ij ))4).. ao! 99.9* m3 2 i44?.! WO 0 _J00 "24;7244,'4Z..4:.4Z4.4,4./ m : N `44.49::t., ,Mill Mil iiiiiiiiiiiiiiiiiiiiiiiiiiiiiii m3 2 -mmhg. -atamilitl,!,, itim-), --,47.4%wann --zuman.74thian.,"4.04in.,...244: 000H iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii a- m32 a il..ll. ":MUnie. owe" "fel. coma &V :4pttli "n54:i.., "'"4.4.t%., Figure C.8 M256

96 8 C00[0:9] =NENEFLLU." CO[0.93 NEWaJUJ.N CO2(0:93 NNEMEELLLLP CO3[0 :93 LLB' CO4[0.9] ENEMELL2UN C05[0 :9] r: CO6[0.93 NEN=NFUlu.N C07(0.93 =/4232J-L'' 3(0:7]..7, OUT00[0.9 OUT0[0.9 '42.24MMEMO 00 OUT02[0:9 wuu"lumnem (-453 OUT03[0:93 :'x:4a]2mmeno 007'04[0:93 '""N.UUMENNEE OUT05[0:9 ""."0-WLEMEMMO oxywo4[0.9 "'"N.LLLMEMMME OUT07[0:9 ""LUUJEMEMN our08t0.9 OUT09[0:93 OUT0[0:9] MEEMMPMJj 9 OUT[0:9] MEMEMPMM. OUT2[0:9 MEMEMP2,4., ouv3(0.9) MEMOWEDg OUT4[0:93 MMEEMPM" pow5(03.9 MMEMPmu, /!DO:453 CO8[0:93 "NULUMEMME CO9[0:9].00 9 'N.P.U.UENNEE C[0:9] UENME C2[0:9 "LLLUMNEME C3[0.9] MLUNNNME C4[0,93 'N.L.JUNMENE C5[0:9] "L'UUNNEME C6[0.9) MM=UUJ" C7[0:93 NMEWLUU" C8[0:9] MENWaLuJ" C9[0:9] immowaluu. C20[0:93 NF'LLLJN C2[0:93 ==LLLJN C22[0.9] C23[0:9] 007.6[0:93 ""'N'ULLEN=EM OUT7[0:93 "4..4MMMN OUT8[0:9] w''"..2mmenne OUT9[0:9 OUT20[0.93 w"lu=mom OUT2[0:93 MJ.LMEMMOMM (0:9 007'23[0:9] ""LULLE= C24[0:93 MENNEWMj C25[0:93 MMONEWELU C26[093 N NEMEMMW C27[0:9] MENOMMLUS C28[0:93 E MMENPU C29[0:93 MEMMV0.0. C30[0:93 N EMENPrni C3[0:9] nom.f= OUT24[0:93 "N.U.LUMMMEM OUT25[0:9) "LU.LUNEMMM OUT26[0:9) 'NJ...LUMEN= [0.93 OUT28[0:9] 'NUJMMENEE OUT 'N.U.JUMMENE OUT30[0:9 "LUUMMENE OUT3[0:9] "N.P..LUNEEMM M32 Figure C.9 M32

97 82 Priki mll GS t :203 ll MOW iim, Ws lift liiie- n lift win lift llelue 43 hoe lima lift 64 Rio lige lige Rog_ l igkel lige Pao lift li:43 liio W W 444 MA PAM &All li;43 l'iito 44 li4 go 04 lift l'ilm 04 li04 Rio Mt! 04 riika, l ift lift :43 We Ma l ike 4 moo arm on Rs Cotrealf% Coif.. 4.7".) TTe. OVV0.9/ M8 Figure C.0 M8

98 Figure C. FA 24 or Counter (3,2) 83

99 Q. O H 0 LLe E- El El E, 8 m LP 6 Ea pp 0.- El 0 U El o 0 0 Cd Cd - U O Z H Z H H r';l )t H H H H H Figure C.2 Counter (7,3) 84

100 5n(unweigHted)-->4 weighted out ZN a fa COWS OUTS ZN3 ZNS a Z.N4 N7 N fa fa UT a a a fa w... pd W5'04

101 (0.0 ialli242"::74:w" 044:Ptii4TT rallglitm000( (0.0j.4024(0.0( glii74!,44.0sf0) xml.%44.:0.4:8.4:0.a.404tv g;,0:7)=4::.? M NATNNORPT) 0(0!" ,0444:::0.ni 0"3"0t.)04:0.) Nniel0()NSSSe0) X.44(0.0) in70[0.) N77.00].XN0S(0.9."":00,0) 003 2g;.0 0X577( X:T04(0?: e"44;leirli 054(0.0) (00.0) 2mafdlytam,' ) ?:" '""Tele' ]( ).47240:*... el:" el:".alleele4hi'llgn:leli'littl'shi") 040( 8 4(0.0 4'4':4.)., out is 0j3mbij2.2bij.4=bij0.8

102 400,03 int (0,2, O a x sax a ( ro ro it4 044 OVT UTO OUT4 0U.02 OU.S , ,70[0. 0, UTOO 0/ ColfrOl OfXsai Ogrpol SKVO can, is. 20) 20 W3N2OB

103 : : ON BEE NNE ii Mill MOM iii =2:!ill Mi ERE ME =0 iiiiiiiiiiilli 00" ZS= i 0f ZEES!!Pi = =2 ill ;; iig ;!!!!!! 2:2 iliiiiiililiii N " FF. :