Modeling of Non-Volatile Memories With Silvaco. Dragica Vasileska Professor Arizona State University

Transcription

1 Modeling of Non-Volatile Memories With Silvaco Dragica Vasileska Professor Arizona State University

2 Content Introductory Concepts Non-Volatile Memories Explanation of Various Effects Different Effects Implementation in Silvaco Simulation Example

3 Market Shares by Product Discretes & Opto 12.9% Memory 25% Bipolar 0.5% Microperipheral 5.7% Analog 14.9% DSP 3.1% Logic 16.3% Microprocessor 15.4% Microcontroller 6.2%

4 Semiconductor Memory Classification Read-Write Memory Volatile Read-Write Memory Non-Volatile Read-Only Memory Non-Volatile Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM

5 Non-Volatile Memories A non-volatile memory is a memory that can hold its information without the need for an external voltage supply. The data can be electrically cleared and rewritten Examples: Magnetic Core Hard-disk OTP: one-time programmable (diodes/fuses) EPROM: electrically programmable ROM EEPROM: electrically erasable and programmable ROM Flash

6 IC memory classification Volatile memories Lose data when power down Non-volatile memories Keep data without power supply SRAM DRAM ROM PROM EPROM EEPROM Stand-alone versus embedded memories FLASH EEPROM This lecture: stand-alone

7 Non-volatile memory comparison

8 Cost-Performance Drivers Cost per M transistors/bits ($) 10k 1k Logic SRAM ROM DRAM Logic in 1980 DRAM in 1980 EEPROM Flash HDD HDD in 1980 ns µs ms Access time

9 Characteristics of State-of-the-art NVM

10 MOSFET operation (very basic) C V fb V T accumulation depletion inversion V

11 Current through the MOS transistor inversion Channel charge: Q ~ (V gs V T ) Channel current: I ~ (V gs V T ) MOS transistor - simplistic MOS transistor - real I I V gs V gs V T V T

12 Concept of the floating-gate memory cell MOS transistor: 1 fixed threshold voltage Flash memory cell: V T can be changed by program/erase MOS transistor Floating gate transistor I d I d programming erasing V gs V gs V T

13 Floating gate transistor: principle V T is shifted by injecting electrons into the floating gate; It is shifted back by removing these electrons again. Floating gate Control gate CMOS compatible technology!

14 Channel charge in floating gate transistors unprogrammed programmed Control gate Control gate Floating gate Floating gate silicon To obtain the same channel charge, the programmed gate needs a higher control-gate voltage than the unprogrammed gate

15 Logic 0 and 1 Reading a bit means: I d 1. Apply V read on the control gate V T = -Q/C pp 2. Measure drain current I d of the floating-gate transistor When cells are placed in a matrix: drain lines V read 1 I read >> 0 0 I read = 0 V gs Control gate lines

16 Programming and erasing the floating gate Floating gate Control gate Control gate Floating gate SiO 2 Si 3 N 4 Polysilicon

17 Band diagram (over-simplified!)

18 Program/erase of a floating gate transistor Floating gate is surrounded by insulating material. How to drive charge in and out of it? Injection/ejection mechanisms: Fowler-Nordheim tunneling (FN) Channel Hot Electron Injection (CHE) Irradiation (most common: UV, for EPROMs)

19 Conduction through SiO 2 Dominant current components: Intrinsic quantummechanical conduction Fowler-Nordheim tunneling Direct Tunneling Defect-related: Trap-assisted tunneling (via a molecular defect) Current through large defects (e.g. pinholes) Intrinsic current is defined by geometry & materials V G Defect-related current can be suppressed by engineering V D V B

20 Gate oxide conduction -example 4 nm oxide I G (A) Unstressed oxide V G (V) Hard breakdown Soft breakdown SILC

21 Program/erase mechanisms

22 Flash program and erase methods

23 CHE: Hot electron programming Field kinetic energy overcome the barrier Hot holes Hot electrons Hole substrate current Pinch-off high electric fields near drain hot carrier injection through SiO 2 Note: < 1% of the electrons will reach the floating gate power-inefficient

24 Programming: Channel Hot Electron Injection

25 CHE: properties Works only to create a positive V T shift High power consumption: ~300 µa/cell (most electrons get to the drain: lost effort) Moderate programming voltages Risky: hot carriers can damage materials May lead to fixed charge, interface traps, bulk traps Results in degradation of the cell (see later)

26 Fowler-Nordheim tunneling Uniform tunneling through entire dielectric is possible V T -shift can be positive as well as negative Can be used for program anderase Requires high voltage and high capacitances Little power needed (~10 na/cell) Risks of this technique: Charge trapping in oxide Stress-induced leakage current Defect-related oxide breakdown FN

27 Uniform or drain-side FN tunneling Non-uniform: only for erasing; less demanding for the dielectric

28 Alternative: tunnel through interpoly oxide (erasing, combined with CHE program) Less demanding for the tunnel oxide Therefore less SILC and better retention More demanding for interpoly oxide Uses high voltage and low power

29 NOR and NAND flash technology

30 Flash reliability issues and scaling Flash reliability concerns: The regular reliability concerns of CMOS Oxide breakdown Interconnect problems (electromigration) Specific for Flash: Retention Endurance Scaling: Can we make the flash cell more compact? Dominant problem: scaling the dielectrics

31 Reliability issues Specific problems in non-volatile memories: Fast programming and erasing (~10-6 s) is done by controlled tunnelling, leads to oxide degradation (trapping) Functional requirements no charge leaking in stand by situation (up to s) distinguish 0 and 1 even after intensive use In a 10 MB memory, should every single bit be OK? Trade-off: reliability error detection & correction

32 Retention Ability to retain valid data for a prolonged period of time under storage conditions (non-volatile). Single Cell: timebefore change of 0.1% change in stored datawhile not under electrical stress Intrinsic retention Array of Cells: retention of the worst cell in the array before and after cycling defect related = Extrinsic retention Alzheimer s Law : V th E = + ( ) a ( t) Vth 0 Vth (0) Vth 0 exp ν t exp kt

33 Data retention prohibits tunnel oxide scaling 7-8 nm is the bare minimum

34 Retention: summary Retention = the ability to hold on to the charge Loss > 5 electrons per day is killing in the long run Mostly limited by defects in the tunnel oxide Retention can be compromised with error correction For thin oxides < 7 nm, the retention of Flash is intrinsically insufficient To test retention, measure at different T and field

35 Endurance (uithoudingsvermogen) Ability to perform even after a large number of program/erase cycles Showstoppers: Oxide breakdown Loss of memory window Shift in operating margin

36 Endurance: oxide breakdown A dielectric will break down when a certain amount of charge has crossed it: this amount is Q BD. Typical for good SiO 2 material: Q BD = 10 C/cm 2. Simple relation: n pe the number of program/erase cycles until breakdown ΔV fg the shift between the 0 and 1 state n pe = Q bd V Good engineering gives a grip on Q BD then, no problem A fg inj C

37 Endurance: window closing Fixed charges appear in the tunnel oxide after program/erase cycles Program/erase cycles

38 ITRS 2007: long-term vision on NVM

39 Retention vs. alterability

40 Device Simulator Needs If one needs to investigate, verify, and optimize designs for nonvolatile memories, such as EPROMs, EEPROM s, and FlashEEPROMs then you need a device simulator to account for a variety of physical effects such as band-to-band tunneling, Fowler-Nordheim tunneling, impact ionization, and floating gates. Self-consistent descriptions of these effects (not just postprocessing approximations) are required. Both steady-state and time-domain transient simulation capabilities are desirable. Time-domain capabilities provide self-consistent (rather than less accurate quasi-static) calculations of programming and erasing operations

41 Silvaco Capabilities These capabilities are incorporated in the robust general purpose device simulators HFIELDS-2Dand S-Pisces2B. Charge boundary conditions, Fowler-Nordheim tunneling and band-to-band tunneling are all self-consistently simulated. In addition, a newly developed numerical algorithm that greatly reduces the mesh sensitivity of calculated gate current is used. This mesh sensitivity limits the accuracy and reliability of some other programs that seek to simulate nonvolatile memory devices.

42 Cross-sections of NVM cells

43 Explanation of Various Effects Fowler-Nordheim Tunneling Lucky Electron Model Band to Band Tunneling

44 Some General Comments For sub-micrometer devices, due to smaller oxide thickness, there is significant conductance being measured on the gate contact. The finite gate current gives rise to the following effects: Negative => degradation in the device operating characteristics with time due to oxide charging; larger off-state power dissipation Positive => non-volatile memories utilize the gate current to program and erase charge on the floating contact FLASH, FLOTOX, EEPROM There are two different types of conduction mechanisms to the insulator layer: Tunneling: Fowler-Nordheim or direct tunneling process Hot-carrier injection: lucky electron model or Concannon model Electron is emitted into the oxide when it gains sufficient energy to overcome the insulator/semiconductor barrier. Similar to the lucky electron model, but assumes non-maxwellian high energy tail on the distribution function. Requires solution of the energy balance equation for carrier temperature.

45 Oxide Charging Electrons at the drain end of the channel have sufficient energy to overcome the barrier at the Si/SiO 2 interface and be trapped in the oxide Since the effect is cumulative, it limits the useful life of the device (LDD regions are used to reduce oxide charging) The various oxide charging mechanisms, that lead to threshold voltage shift, are summarized in the figure on the right Figure from textbook by Sze: Semiconductor device theory

46 Tunneling Currents Three types of tunneling processes are schematically shown below (courtesy of D. K. Schroder) V V φ ox = φ ox < φ B B B V ox > φ B t ox FN FN/Direct Direct For t ox 40 Å, Fowler-Nordheim (FN) tunneling dominates For t ox < 40 Å, direct tunneling becomes important I dir > I FN at a given V ox when direct tunneling active For given electric field: - I FN independent of oxide thickness - I dir depends on oxide thickness

47 Significance of Gate Leakage As oxide thickness decreases, the gate current becomes more important. It eventually dominates the off-state leakage current (I D at V G = 0 V) The drain current I D as a function of technology generation is shown below (courtesy of D. K. Schroder) 10-4 I on Current (A/µm) I G I off Technology Generation (nm)

48 Fowler-Nordheim Tunneling Φ B Φ B - eex E F 0 x-axis E F 0 a No applied bias With applied bias The difference between the Fermi level and the top of the barrier is denoted by Φ B According to WKB approximation, the tunneling coefficient through this triangular barrier equals to: T a 2 γ( x) dx 0 2m* exp where: ( x) = ( Φ eex) γ 2 ħ B

49 Fowler-Nordheim Tunneling (cont d) The final expression for the Fowler-Nordheim tunneling coefficient is: T 4 exp Important notes: 2m* Φ 3eEħ 3/ 2 B The above expression explains tunneling process only qualitatively because the additional attraction of the electron back to the plate is not included Due to surface imperfections, the surface field changes and can make large difference in the results Calculated and experimental tunnel current characteristics for ultra-thin oxide layers. (M. Depas et al., Solid State Electronics, Vol. 38, No. 8, pp , 1995)

50 Silvaco Implementation In Silvaco ATLAS, the Fowler-Nordheim tunneling currents are calculated using the following expressions: where: J J FN FP = F.AE E = F.AH E exp exp ( F.BE / E) ( F.BH / E) E => magnitude of the electric field in the oxide 2 2 F.AE, F.BE, F.AH and F.BH => model parameters that can be defined via the MODEL statement There are two different ways in which Fowler-Nordheim tunneling is implemented within the solution procedure: As a post-processing option => specify FNPP on the MODEL statement Within the self-consistent scheme => specify FNORD on the MODEL statement

51 Silvaco Implementation (cont d) The actual implementation scheme is as follows: Each electrode/insulator and each insulator/sc interface is divided into segments based upon the mesh For each SC/insulator segment, the tunneling current expressions given in the previous slide, are used to calculate J FN and J FP The as-calculated tunneling currents are then added to the metalinsulator segment using the following two criteria: Model one (default) => The segment that receives the current has to be on the path of the electric field vector at the SC/oxide interface. Model two (NEARFLG parameter on the MODEL statement) => The electrode/insulator segment that is nearest to the insulator/sc segment receives all the current

52 Lucky Electron Model Explained S oxide Gate P 4 D P 1 P 2 P 3 P 4 K.E. Φ B n + P n + 1 P 3 P 2 x 0 p-type SC substrate Description from: K. Hasnat et al., IEEE TED 43, 1264 (1996). substrate oxide gate P 1 => probability that the electron gains sufficient energy from the electric field to overcome the potential barrier P 2 => probability for redirecting collision to occur, to send the electron towards the SC/insulator interface P 3 => probability that the electron will travel towards the interface without loosing energy P 4 => probability that electron will not scatter in the image potential well

53 Mathematical Description The various probabilities described in the previous slide are calculated using: 1 ε 1 Φ = ε = B y x 1 exp d, P2 1, P3 = exp, P4 = exp λex λex 2λr ε λ λ P 0 λ λ r Φ B => scattering mean-free path => redirection mean-free path => barrier height at the SC-oxide interface Φ B = Φ 1/ 2 2 / 3 B0 αeox βeox ox Zero-field barrier height Barrier lowering due to image potential λ ox => mean-free path in the oxide (3.2 nm) Accounts for probability for tunneling The total gate current is then given by: I g = dxdy dεj Φ B n ( x, y) P P P P

54 Silvaco Implementation In the Silvaco ATLAS implementation of the lucky-electron model, the probabilities P 1 and P 2 have actually been merged together. (see description of the model and the various parameters that need to be specified on pages 3-76 to 3-79 via the MODEL statement). It is activated via the MODEL statement by the parameters HEI (hot electron injection) or HHI (hot hole injection) The implementation of the model is similar to the Fowler-Nordheim tunneling (see slide 9 for details). The Concannon s injection model Assumes non-maxwellian distribution function, which requires solution of the energy balance equations for the carrier temperature. The model is specified with the parameters N.CONCANNON and P.CONCANNON on the MODELS statement. Two other parameters of the MODEL statement, which affect the numerical integration of the current, are definable by the user: ENERGY.STEP (default 25 mev) and INFINITY parameter (upper limit of integration).

55 More on Silvaco Implementation The specification of one or more electrodes as floating is accomplished via the parameter FLOATING on the CONTACT statement Modeling of the correct coupling capacitance between the FG (floating gate) and the CG (control gate) is accomplished via the parameters: FLG.CAP additional capacitance per unit length between FG and CG ELE.CAP specifies the index of the (wider) control gate on the CONTACT statement During the write or erase cycles, the gate currents arise because of: hot-electron injection (HEI or N.CONCANNON) hot-hole injection (HHI or P.CONCANNON) Fowler-Nordheim tunneling (FNORD) band-to-band tunneling (BBT) Gate current assignment can be: - in the direction of highest contributing field (drift current) - geometrically closest electrode for diffusion current (NEARFL)

56 More on Silvaco Implementation (cont d) Additional parameters that has been specified in the EPROM example, in conjunction with the METHOD statement include: AUTONR Automated Newton-Richardson procedure that attempts to reduce the number of LU-decompositions per bias point PR.TOL Absolute tolerance for Poisson equation PX.TOL Relative tolerance for Poisson equation (P.TOL) CR.TOL Absolute tolerance for continuity equation CX.TOL Relative tolerance for continuity equation (C.TOL) Parameters specified in the EPROM example in conjunction with the SOLVE statement include: PREVIOUS Use previous solution as initial guess PROJECT Extrapolation from the last two solutions will be used as an initial approximation (guess) Q<n> Specifies charge on an electrode n QSTEP QFINAL Charge increment to be added to one or more electrodes Final charge for a set of bias increments

57 Different Effects Implementation in Silvaco Erase Cycle Band to Band Tunneling Threshold Voltage Shift Role of Control Voltage Programming Characteristics

58 Silvaco Example for Modeling Memories The following EEPROM simulations were generated using S-Pisces2Bto illustrate the effect of varying the tunnel oxide thickness from 75 to 120 Figure 1). The device structure was generated by SSuprem4. The channel length is 0.7 microns and the gate oxide thickness is 200 A.

59 Erase Characteristics Figure 2. EEPROM device simulation showing erase characteristics associated with different tunneling oxide thicknesses.

60 Importance of BBT Figure 3 illustrates the importance of accounting for band-to-band tunneling during erasure. The substrate current behavior during erasure cannot be determined accurately without accounting for tunneling effects in the model..

61 Threshold Voltage Shift Figure 4 shows threshold voltage shift as a function of the charge on the floating gate.

62 Gate Current Dependence on Control Voltage Figure 5 shows gate current dependence on the control voltage.

63 Programming Characteristics Figure 6, transient programming characteristics for different drain voltages, clearly demonstrates the strong dependence of programming times on drain-source voltage

64 Simulation Example Problem Statement Listing of the Code Simulation Results

65 Example: Write and Erase of an EPROM Threshold Voltage Before Programming Programming Cycle Threshold Voltage Shift = Q Tox/L Eox Erase cycle with Drain contact disconnected by adding a very large resistor in series The source electrode is ramped to 12.5 V

66 Threshold voltage before programming Floating gate Memory # Set workfunction for the poly gates, contact name=fgate n.polysilicon floating contact name=cgate n.polysilicon #Define some Qss... interface qf=3e10 models srh cvt hei fnord print nearflg impact selb ######### This is the Vt Test before programming ############# ############################################################## solve init method newton trap maxtraps=8 autonr log outf=eprmex01_2.log solve vdrain=0.5 solve vstep=0.5 vfinal=25 name=cgate comp=5.5e-5 cname=drain # plot idvg tonyplot eprmex01_2.log -s eprmex01_2.set # extract vt extract name="initial vt" ((xintercept(maxslope(curve(v."cgate",i."drain"))))-abs(ave(v."drain"))/2.0)

67 ######### This is the Programming/Writing Transient ########### ############################################################### # use zero carriers to get vg=12v solution models srh cvt hei fnord print nearflg method carriers=0 log off solve init solve vcgate=3 solve vcgate=6 solve vcgate=12 # now use 2 carriers models srh cvt hei fnord print nearflg impact selb method newton trap maxtraps=8 carriers=2 solve prev log outf=eprmex01_3.log master # ramp up drain voltage solve vdrain=5.85 ramptime=1e-9 tstep=1e-10 tfinal=1e-9 proj # keep voltages constant and perform transient programming solve tstep=1e-9 tfinal=5.e-4 # plot programming curve tonyplot eprmex01_3.log -set eprmex01_3.set # save the structure save outf=eprmex01_2.str

68 Ramping the Control gate Voltage with Zero carriers Doing the programming while Keeping the voltages the same

69 ######### This is the Vt Test After Programming ########### ########################################################### method newton trap maxtraps=8 autonr log outf=eprmex01_4.log master solve init solve vdrain=0.5 solve vstep=0.5 vfinal=25 name=cgate comp=5.5e-5 cname=drain # plot new idvg overlaid on old one tonyplot -overlay eprmex01_2.log eprmex01_4.log -set eprmex01_4.set # extract vt and vt shift extract name="final vt" ((xintercept(maxslope(curve(v."cgate",i."drain"))))-abs(ave(v."drain"))/2.0) extract name="vt shift" ($"final vt" - $"initial vt")

70 ######## This is the Erasing Test ###################### ######################################################## go atlas # select erasing models Erasing Cycle models cvt srh fnord bbt.std print nearflg \ F.BE=1.4e8 F.BH=1.4e8 impact selb contact name=fgate n.poly floating contact name=cgate n.poly interface qf=3e10 method carr=2 # get initial zero carrier solution solve init # ramp the floating gate charge method newton trap maxtraps=8 solve prev solve q1=-1e-16 solve q1=-5e-16 solve q1=-1e-15 solve q1=-2e-15 solve q1=-3.5e-15 solve q1=-5e-15 Source current # put a resistor on drain contact name=drain resistance=1.e20 # do Erasing transient method newton trap maxtraps=8 autonr c.tol=1.e-4 p.tol=1.e-4 log outf=eprmex01_5.log master solve vsource=12.5 tstep=1.e-14 tfinal=4.e-1 tonyplot eprmex01_5.log -set eprmex01_5.set