Half-circuit incremental analysis techniques

Transcription

1 6.012 Electronic Devices and Circuits Lecture 19 Differential Amplifier Stages Outline Announcements Handouts Lecture Outline and Summary Design Problem out tomorrow in recitation Review Singletransistor building block stages Common emitter/source: general purpose gain stage, workhorse Common base/gate: small R in, large R out, unity A i, same A v as CE/S Emitter/source follower: large R in, small R out, unity A v, same A i as CE/S Series and Shunt feedback: we'll see in special situations Differential Amplifier Stages Large signal behavior General features: symmetry, inputs, outputs, biasing (Symmetry is the key!) Large signal transfer characteristic Difference and commonmode signals Decomposing and reconstructing general signals Halfcircuit incremental analysis techniques Linear equivalent halfcircuits Difference and commonmode analysis Example: analysis of emittercoupled pair Clif Fonstad, 11/03 Lecture 19 Slide 1

2 The "midband"concept: frequency range of constant gain and phase Common emitter V v t r t g p gm v p g o v in v p C m C O C p g v out LOAD gnext v in I BIAS C O v out C E r IBIAS C E for common emitter stage with all the capacitors Biasing capacitors: typically in mf range (C O, C E, etc.) effectively shorts above w LO Device capacitors: typically in pf range V (C p, C m, etc.) effectively open until w HI Midband frequencies defined as w LO < w < w HI v t r t v g p in v p g m v p g o v out g l Common emitter for in midband range Note: g l = g LOAD g next Clif Fonstad, 11/03 Lecture 19 Slide 2

3 Summary of the stages (bipolar) Common emitter Common base Emitter follower Emitter degeneration (series feedback) Shunt feedback Voltage gain, A v g m g o g l Current gain, A i ( = g m r l ') b g l g o g l g m r ( = g [ g o g l ] m r l ') ª1 ª p [ b 1] [ g m g p ] ª1 b g l ª b r p b 1 g m g p g o g l g G m F g o G F g o g l Input resistance, R i Output resistance, R o r p r o Ê = 1 ˆ Á Ë g o ª [ b 1]r o r ' ª r r t p l b 1 ª r l ª b ª r p [ b 1]R F ª r o R F ª g mr F g l 1 G F g p G F 1 A v Ê r o R F Á = Ë 1 g o G F ˆ Clif Fonstad, 11/03 Lecture 19 Slide 3

4 Summary of the stages (MOSFET) Voltage gain, A v Current gain, A i Input resistance, R i Output resistance, R o Common source g m r l ' Ê r o = 1 ˆ Á Ë g o Common gate ª [ g m g mb ]r l ' ª1 1 Ï ª ªr [ g m g mb ] o 1 g m g mb g Ì o Ó g t Source follower Source degeneration (series feedback) Shunt feedback g m ª1 1 g m g o g l g m G F g o G F [ g m g o g l ] ª 1 g m ª r l R F ª r o ª g mr F g l G F R F G F 1 A v Ê r o R F Á = Ë 1 g o G F ˆ Clif Fonstad, 11/03 Lecture 19 Slide 4

5 Differential Amplifiers: emitter and sourcecoupled pairs V V v IN1 v OUT1 v OUT2 v IN2 v IN1 v OUT1 v OUT2 v IN2 I BIAS I BIAS V V Emittercoupled pair Sourcecoupled pair Clif Fonstad, 11/03 Lecture 19 Slide 5

6 Emittercoupled pair: large signal analysis Analysis: 3 KVL loops (see text) Result: Outputs only depend on difference between the two inputs, (v I1 v I2 ) a v O1 = V CC F R C I BIAS 1 e q [ v I 1 v I 2 ] kt { } a v O2 = V CC F R C I BIAS 1 e q [ v I 1 v I 2 ] kt { } v O = a F R C I BIAS tanh q v v I1 I 2 2kT Transfer characteristic is symmetrical Above: Circuit with large signal, FAR BJT model in place Right: Transfer characteristic Slope near origin = g m R C Clif Fonstad, 11/03 Lecture 19 Slide 6

7 Sourcecoupled pair: large signal analysis Above: Circuit with large signal, MOSFET model for saturation in place Analysis: 3 KVL loops (see text) Result: Outputs only depend on difference between the two inputs, (v I1 v I2 ) Ï K[ v IN1 v IN 2 ] 2 I BIAS v O1 = V DD R D 2 v O2 = V DD R D 2 Ì Ó Ï K v IN1 v IN 2 Ì Ó K [ 2 v v IN1 IN 2] 2 I BIAS K [ 2 v v IN1 IN 2] 4I BIAS K v IN1 v IN 2 2 4I BIAS K v IN1 v IN 2 2 v O = R K D 4I [ v IN1 v IN 2 ] BIAS 2 K v v IN1 IN 2 Transfer characteristic is symmetrical 2 Right: Transfer characteristic Slope near origin = g m R D Clif Fonstad, 11/03 Lecture 19 Slide 7

8 Differential Amplifier Analysis difference and commonmode signals Any pair of signals can be decomposed into a portion that is the identical in both, and a portion that is equal, but opposite in both. For example, if we have two voltages, v 1 and v 2, we can define a commonmode signal, v C, and a differencemode signal, v D, as: 2 v D [ v 1 v 2 ] v C v 1 v 2 In terms of these two voltages, we can write v 1 and v 2 as: v 1 = v C v D 2 v 2 = v C v D 2 In incremental analysis of linear amplifiers we will decompose our inputs into difference and commonmode inputs: 2 v id [ v in1 v in2 ] v in1 v in2 We will apply v id to the circuit and get v od (= A vd v id ), and then apply to the circuit to get v oc (= A vc ). Then we will reconstruct our outputs: v out1 = v oc v od 2 = A vc A vd v id 2 v out2 = v oc v od 2 = A vc A vd v id 2 Clif Fonstad, 11/03 Lecture 19 Slide 8

9 Differential Amplifier Analysis incremental analysis exploiting symmetry and superposition v in1 Linear equivalent circuit (symmetrical) v in2 v out1 v out2 v in1 v in2 v out1 v out2 Clif Fonstad, 11/03 Lecture 19 Slide 9

10 Differential Amplifier Analysis incremental analysis exploiting symmetry and superposition v id v id v id v od No voltage on common links, so incrementally they are grounded. v od v od = A vd v id v oc No current in common links, so incrementally they are open. v oc v oc = A vc Clif Fonstad, 11/03 Lecture 19 Slide 10

11 Looking at a complicated circuit: Lesson I Find the biasing circuitry and represent it symbolically Consider the following example: 1.5 V Q 1 A Q 2 Q 3 Q 4 Q 5 Q 8 Q 10 Q 11 A Q 23 Q 9 I BIAS5 R 1 B v IN1 B Q 7 Q 6 Q 19 v IN2 B R 2 R 3 Q 12 Q 13 Q 14 Q 15 Q 20 B Q B 21 Q B 22 Q 24 Q 16 Q 17 v OUT Q 18 I BIAS1 I BIAS2 I BIAS3 I BIAS4 I BIAS6 Circuitry providing the V REF 's 1.5 V 8 of the 24 transistors are "only" used for biasing the other 16 transistors! If we get them out of the picture for awhile, the circuit looks simpler: Clif Fonstad, 11/03 Lecture 18 Slide 11

12 Looking at a complicated circuit: Lesson I, cont. segregating out the biasing circuitry Indicating the current sources symbolically lets you focus on the action: 1.5 V Q 2 Q 3 Q 4 Q 5 Q 8 Q 10 Q 11 I BIAS5 Q 9 v IN1 Q 6 Q 7 R 2 R 3 Q 12 Q 13 v IN2 Q 14 Q 15 Q 16 Q 17 v OUT I BIAS1 I BIAS2 I BIAS3 I BIAS4 I BIAS6 1.5 V 16 transistors left. In Lessons II and III we reduce the number to 5! Stay tuned Clif Fonstad, 11/03 Lecture 18 Slide 12

13 Differential Amplifier Analysis an example of half circuit 1.5 V reduction Q 2 Q 3 Lee load Q 4 Q 5 Q 8 Q 10 Current mirror load Q 11 Q 9 I BIAS5 v IN1 Q 6 Q 7 R 2 R 3 Q 12 Q 13 v IN2 Q 14 Q 15 Q 16 Q 17 v OUT I BIAS1 I BIAS2 I BIAS3 I BIAS4 I BIAS6 1.5 V v id /2 r elldm Q 9 R Q 16 3 Q 6 Q 12 r oq22 r ecmdm Q 14 r oq23 v od r ellcm r ecmcm r oq23 Q 9 R Q 16 3 Q 6 Q 12 2r oq19 r oq22 Q 14 2r oq21 v oc Differencemode half circuit Commonmode half circuit Clif Fonstad, 11/03 Lecture 19 Slide 13

14 6.012 Electronic Devices and Circuits Lecture 19 Differential Amplifier Stages Summary Differential Amplifier Stages Large signal behavior General features: two transistors highly symmetrical two inputs, two outputs (an emittercoupled, or sourcecoupled, pair) (however, one input can be zero) biased by single current source Large signal transfer characteristics: only depends on v IN1 v IN2 Difference and commonmode signals Differencemode: v ID = v IN1 v IN2 Commonmode: v IC = (v IN1 v IN2 )/2 Reconstruction: v IN1 = v IC v ID /2, v IN2 = v IC v ID /2 Halfcircuit incremental analysis techniques Exploiting symmetry and superposition Differencemode lin. equiv. halfcircuit: links are grounded Commonmode lin. equiv. half circuit: links are cut, open circuited Approach: 1. identify common and differencemode half circuits 2. calculate common and differencemode signals 3. analyze differencemode halfcircuit (each halfcircuit is one of 4. analyze commonmode halfcircuit our known buildingblocks) 5. reconstruct signals Clif Fonstad, 11/03 Lecture 19 Slide 14