Fault Tolerant Computing CS 530 Fault Modeling

Transcription

1 CS 53 Fault Modeling Yashwant K. Malaiya Colorado State University Fault Modeling Why fault modeling? Stuck-at / fault model The single fault assumption Bridging and delay faults MOS transistors and CMOS Switch-level fault model Stuck-on/open Shorts and IDDQ 2

2 Fault Modeling Fault Model: a set of assumed faults in a system such that testing for them will test for most faults of a specific class. Used for test generation, simulation and quality evaluation. Hide complexities of actual defects. Infinitely many defects possible. Based on past knowledge of defect modes and modeling experience. 3 Common Fault Models No model: test exhaustively Hardware fault models: Gate level: stuck-at / bridging delay faults Transistor level: stuck on/open Definition? bridging Functional fault models Software fault model Is there one? Kind of 4 2

3 Failure mechanisms in hardware Temporary Permanent Opens: broken connection, also near-opens Shorts: unwanted connection, also near shorts Can be seen Imperfect devices Digital impairment Analog impairments like excessive delays 5 Stuck-at / Model Classical model, well developed results/methods May not describe many defects in today s VLSI, still a nice way of structural probing. Model: any one or more of these may be stuck at or : a gate input, a gate output, a primary input. Justification: many lower level defects can be shown to have an equivalent effect. 6 3

4 Stuck-at / Example x x2 x3 a b AND AND c z X2 s-a- z = x+x3 a s-a- z = x+x2x3 b s-a- z = xx2+x3 c s-a- z = z s-a- z = Find a test vector for x2 s-a-: Input = (x,x2,x3) = (,,) Output = normally if faulty 7 Single Fault Assumption Assumption: only one fault is present at a time. Significantly reduces complexity. Good for fault detection: complete single stuck test set will detect almost all multiple faults. Not good for fault location. How many multiple faults? Assume k lines 3 states per line: normal, s-a-, s-a- Total 3 k - faulty situations (k=, total.3x 477) 8 4

5 Bridging (Short) Fault Model Common assumption: only nearby lines can be bridged Model: Two lines x and y bridged can cause both to take the value x AND y AND-bridging (-dominance) x y -bridging (-dominance) Depends on technology, transistor dimensions etc. 9 Bridging Faults x x2 Z = x+x2 With AND bridging Z = (xx2) + (xx2) = xx2 x3 Z2 = x2+x3 Z2 = (xx2) + x3 Feedback bridging / AND / / Oscillations: odd inversions, Sufficient delay Settling at intermediate voltage level 5

6 Delay Fault Model Excessive path delay or gate delay Signals may be sampled before stabilization.2ns. ns Reg.2ns Clock AND.2.8 Reg slack Normal.6ns AND Max prop delay c.2ns Fault c.2 ns MOS Transistors N-channel = open = closed P-channel = closed = open 2 6

7 CMOS N Gate V DD =H A= off B= on Output= verify on off Gnd=L NAND? 3 Switch-level Fault Model () Model: A transistor may be stuck-open Stuck-on NA V DD PA PB NB PB stuck-open? PA stuck-open: output effectively s-a- NA stuck-open: To sensitize output (A,B)=(,) Normal output: Faulty output: high imp: previous value: sequential behavior! Needed test-pair T (,) output= (initialize) T2 (,) normal if faulty test 4 7

8 Switch-level Fault Model (2): Stuck-ON V DD Assume PA is stuck-on A B NA PA PB NB (A,B)=(,) normal out= faulty out=? Depends on relative resistances (dimensions etc) Low resistance between V DD and Gnd: very high supply current (I DDQ ) Gnd 5 Shorts and IDDQ H on? Logical value can not be predicted in general. off Very high supply current (I DDQ ) H L short Generally I DDQ very effective for detecting some defects. off? on L 6 8