Recent Progress and Challenges for Relay Logic Switch Technology

Transcription

1 Recent Progress and Challenges for Relay Logic Switch Technology Tsu-Jae King Liu Louis Hutin, I-Ru Chen, Rhesa Nathanael, Yenhao Chen, Matthew Spencer and Elad Alon Electrical Engineering and Computer Sciences Department University of California, Berkeley, CA USA June 12, 2012 Symposia on VLSI Technology and Circuits

2 Introduction Why relays? Relay-based IC design Recent Progress Current Challenges Conclusion Outline Slide 1

3 Vision of the Future: Swarms of Electronics Smart Grid Traffic management Smart Buildings Infrastructure maintenance Emergence of Ambient Intelligence Sense/monitor, communicate, and react to the environment Jan Rabaey, ASPDAC 2008 Slide 2

4 CMOS Voltage Scaling Drain Current I d scaling V T, V DD S > 60mV/dec Gate Voltage V g Normalized Energy/cycle E tot E dyn E leak V DD (V) Scaling supply voltage (V DD ) reduces circuit speed Scaling threshold voltage (V T ) increases leakage Slide 3

5 Why Relays? OFF State Measured I-V Characteristic Source t gap Gate ON State Drain tdimple F Elec Zero OFF-state current (I OFF ); abrupt switching Turns on by electrostatic actuation when V GS V PI Turns off by spring restoring force when V GS V RL Slide 4

6 Relay Endurance Endurance increases exponentially with decreasing V DD, and linearly with decreasing C L Endurance is projected to exceed V H. Kam et al., IEDM 2010 Slide 5

7 4-Terminal (4-T) Relay for Digital Logic Isometric View: AA cross-section: OFF state Drain A Body Gate Oxide Drain Gate Body insulator Source substrate Gate Body A Source AA cross-section: ON state Channel I DS Voltage applied between the gate and body brings the channel into contact with the source and drain. Folded-flexure design relieves residual stress. Gate oxide layer insulates the channel from the gate. R. Nathanael et al., IEDM 2009 Slide 6

8 4-T Relay I D -V G Characteristics Plan View SEM of 4-T Relay 20 μm I DS (A) (a) 1E-02 1E-04 1E-06 1E-08 1E-10 1E-12 1E-14 V B = 9V V B = 0V V D = 2V V S = 0V V GS (V) Zero I OFF and abrupt switching behavior observed Hysteresis is due to pull-in mode operation (t dimple > t gap /3) and contact surface adhesion. R. Nathanael et al., IEDM 2009; V. Pott et al., Proc. IEEE 2010 Slide 7

9 Digital IC Design with Relays 4 gate delays 1 mechanical delay CMOS: delay is set by electrical time constant Quadratic delay penalty for stacking devices Buffer & distribute logical/electrical effort over many stages Relays: delay is dominated by mechanical movement Can stack ~100 devices before t elec t mech Implement relay logic as a single complex gate F. Chen et al., ICCAD 2008 Slide 8

10 Relay-Based VLSI Building Blocks In collaboration with V. Stojanović (MIT) and D. Marković (UCLA) F. Chen et al., ISSCC 2010 Slide 9

11 Relay Carry Generation Circuit Demonstrates propagate-generate-kill logic as a single complex gate F. Chen et al., ISSCC 2010 Slide 10

12 Energy-Delay Comparison with CMOS Energy (fj) Delay (ns) 90nm relay vs. CMOS adders and multipliers: >2-100 energy higher delay M. Spencer et al., JSSC 2011; H. Fariborzi et al., ESSCIRC 2011 Slide 11

13 Introduction Recent Progress Outline Relay scaling Multi-input/multi-output relay designs Current Challenges Conclusion Slide 12

14 Structural Layer Requirements To reduce V PI, the effective spring constant (k eff ) and actuation gap thickness (t gap ) must be reduced. where Need to reduce the structural layer thickness (h) Strain gradient causes out-of-plane bending before release after release 1 2 z: tip deflection : radius of curvature M: bending moment Need very low strain gradient Slide 13

15 Structural Film Development Movable Plate (Gate) Source 5µm Drain Thin TiN + poly-si 0.4 Ge 0.6 bi-layer stack: Tensile TiN compensates strain gradient in Si 0.4 Ge 0.6 Body Interferometry topograph shows low strain gradient of /µm (~10x improvement) I-R. Chen et al., ECS Spring Meeting 2012 Slide 14

16 Single-Gate, Dual-Source/Drain Relay Plan-View SEM Measured I-V Circuit Symbol Drain 1 Drain 2 Gate Body Temperature Dependence: 0 Source 1 Source V PI / V RL [V] T [ C] V PI V RL I-R. Chen et al., ECS Spring Meeting 2012 Slide 15

17 Single-Gate Relay Inverter/Buffer V DD =1V V B_HIGH =13V V IN V OUT (INV) V OUT (BUF) V B_LOW = 12V (a) (b) V IN (V) V OUT (V) GND =0V INV BUF V OUT V OUT Time (s) R. Nathanael et al., VLSI-TSA 2012 Slide 16

18 Dual-Gate, Dual Source/Drain Relay Bottom (Gate) Electrode Layout Circuit Symbol Drain 1 Drain 2 Gate 1 Body Gate 2 Gate electrodes are interdigitated to ensure that each gate has equal influence on the movable body Source 1 Source 2 R. Nathanael et al., VLSI-TSA 2012 Slide 17

19 Measured V PI and V RL of a Dual-Gate Relay Gate 1 V PI, V RL (V) Gate V PI V RL V DS =1.5V, V B =0V [0, 1] [1, 0] [1, 1] Input [V IN1, V IN2 ] 1 V G Each gate has equal influence Depending on V B, relay can be actuated using one or two gate electrodes R. Nathanael et al., VLSI-TSA 2012 Slide 18

20 Dual-Gate Relay Circuit: AND/NAND V IN1 V IN2 V DD =8V GND =0V V B_LOW = 4V V OUT (AND) V OUT (NAND) V B_HIGH =15V (a) (b) (c) V IN1 (V) V IN2 (V) V OUT (V) NAND AND V OUT V OUT Time (s) R. Nathanael et al., VLSI-TSA 2012 Slide 19

21 Dual-Gate Relay Circuit: OR/NOR V IN1 V IN2 V DD =8V GND =0V V B_LOW = 6V V OUT (OR) V OUT (NOR) V B_HIGH =12V (a) (b) (c) V IN1 (V) V IN2 (V) V OUT (V) NOR OR V OUT V OUT Time (s) R. Nathanael et al., VLSI-TSA 2012 Slide 20

22 Introduction Recent Progress Current Challenges Contact resistance Surface adhesion Conclusion Outline Slide 21

23 Tungsten Contact Resistance Evolution RON [kω] khz 5 khz 25 khz Joule heating occurs when the relay is on Current Contacting surfaces oxidize when the relay is turned off E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 Number of Switching Cycles Surface oxide layers result in increased R ON Y. Chen et al., IEEE/ASME J-MEMS 2012 Slide 22

24 Stiction: The Ultimate Relay Scaling Limiter Hysteresis voltage (V PI -V RL ) scales with V PI : ignoring surface adhesion force Adhesive force reduces with contacting region area: XSEM of Contact Dimple Extracted from measured V PI,V RL (W) (W) J. Yaung et al., to be published 0.04 um 2 Slide 23

25 Introduction Recent Progress Current Challenges Conclusion Outline Slide 24

26 Conclusion Relays have zero I OFF and can incorporate multiple input/output electrodes potentially can achieve lower energy per operation and greater functionality per device than CMOS for digital logic applications. Practical challenges remain to be solved: Contact surface oxidation Minimization of adhesion force within R ON limits Development of ultra-thin structural films with very low strain gradient Slide 25

27 Collaborators: Acknowledgments Fred Chen, Hossein Fariborzi, Prof. Vladimir Stojanović (MIT) Chengcheng Wang, Kevin Dwan, Prof. Dejan Marković (UCLA) Funding sources: DARPA/MTO NEMS Program SRC/DARPA Focus Center Research Program NSF Center for Energy Efficient Electronics Science (E3S) NSF Center of Integrated Nanomechanical Systems (COINS) Berkeley Wireless Research Center Device fabrication support: UC Berkeley Marvell Nanofabrication Laboratory SVTC Technologies & SPTS Technologies Slide 26