COMBINATIONAL CIRCUITS

Transcription

1 OMINTIONL IRUIT pplcatons Half dder ssumpton : Two one-bt bnary varables and The truth table of the Half dder Parallel dder for -bt varables H Implementaton of the Half dder Least gnfcant t L H We need arry nput for these 1 1 H 1 1 Most gnfcant t M H 1

2 OMINTIONL IRUIT pplcatons Full dder ( ) F o o o ( ) o The truth table of the Full dder H H Implementaton of full adder wth half adder and an OR gate o

3 OMINTIONL IRUIT pplcatons Full dder In general ( ) F L -1 F -1 F -1 F M

4 OMINTIONL IRUIT pplcatons Four-stage Rpple arry Parallel dder (pseudoparallel) 1 1 o F o F o1 F 1 o H 1 P G P 1 P G t PDgate Note! Propagaton Delay n arry Out arry In han The longest propagaton delay tme n an adder s the tme t takes the carry to propagate through the full adder. n-bt adder There are n gate levels for the carry to propagate from nput to output.

5 OMINTIONL IRUIT pplcatons arry Lookahead Logc for Parallel dder P G P 1 P G t PDgate There are n gate levels for the carry to propagate from nput to output. P G arry Propagate arry Generate Ths Implementaton leads to the Rpple arry. "Low speed" ssumpton : We have -bt parallel adder um and arry outputs : Input 1 G P P 1 G P ( G P ) G1 P1 G P1 P arry G1 P1 1 G1 P1 G P G P G1 P P1 G P P1 P where, 1,, These oolean functons can be mplemented wth -level OP form. arry Lookahead Generator Where P P1 1 1 P 5

6 OMINTIONL IRUIT pplcatons arry Lookahead Logc for Parallel dder arry Lookahead Generator for 1, and arry Lookahead Generator P G P P 1 G 1 G arry Lookahead Generator P 1 G 1 P G 1 P G 1 6

7 OMINTIONL IRUIT pplcatons arry Lookahead Logc for Parallel dder P G P G arry Lookahead Generator P P 1 1 P G P 1 G 1 P 1 P P 1 1 G P Four-bt dder wth arry Lookahead 7

8 OMINTIONL IRUIT pplcatons nary dder-ubtractor when U 1 when U V o8 F7 7 o F1 o1 1 F ssumpton : We have n-bt dder-ubtractor U If the number are consdered to sgned, the V bt detects an overflow. V after addton or subtracton, then no overflow occurred and the n-bt result s correct. V 1, then the result contans n1 bts, but only the rghtmost n bts ft n the space avalable, so an overflow has occurred. 8

9 OMINTIONL IRUIT pplcatons Magntude omparator ssumpton : We have two n-bt numbers and and are Equal where,..., n 1 where,..., n 1 and are Equal f 1 for all pars. Y n 1 n 1 > < Example : n 1 1 Y Implementaton of the Equal functon 9

10 > Y > Y < < OMINTIONL IRUIT pplcatons Magntude omparator ssumpton : We have two n-bt numbers and > < 1

11 OMINTIONL IRUIT pplcatons Magntude omparator ssumpton : We have two -bt numbers and > < Four-bt magntude comparator 11

12 OMINTIONL IRUIT pplcatons Magntude omparator 785 Truth table > > < 785 < 1

13 OMINTIONL IRUIT pplcatons Magntude omparator 785 y cascadng the 785 -bt magntude comparator, we can construct the 1-bt magntude comparator. > > < < 7 7 > > < 785 < > > < 785 < Outputs 1

14 OMINTIONL IRUIT pplcatons Drvng the N dgt 7-segment dsplay N n 7-segment drver logc ombnatonal logc n-to- n decoder Vcc The dgt number n ommon anodes Quadruble n -to-1 lne muxer The value of dgt (D) D to 7-segment Desmal ponts uppose that we mplement the multplexers wth three-state buffers.? Read Next lde 1

15 OMINTIONL IRUIT pplcatons Drvng the dgt 7-segment dsplay D ounter D ounter 1 D ounter D ounter D a D to 7 seg. elect dgt D D1 g To Drver Transstors base DP DPs DP1 DP DP 15

16 OMINTIONL IRUIT pplcatons dgt 7-segment dsplay Vcc elect Dgt a b c d e f g dp a b c d e f g dp ctvate segments ctvate Desmal Ponts 16

17 The End 17