Module #6: Combinational Logic Design with VHDL Part 2 (Arithmetic)

Transcription

1 ECOM4311 Dgtal Systems Desgn : Combnatonal Logc Desgn wth VHDL Part 2 (Arthmetc) - A crcut that compares dgtal values (.e., Equal, Greater Than, Less Than) Agenda Adders (Rpple Carry, Carry-Look-Ahead) 3. Subtracton 4. Multplcaton 5. Fxed Pont, Floatng Pont numbers Assgnment Read Chapter 3 - We are consderng Dgtal (Analog comparators also exst) - Typcally there wll be 3-outputs, of whch only one s asserted - Whether a bt s EQ, GT, or LT s a Boolean expresson - A 2-Bt Dgtal Comparator would look lke: (A=B) (A>B) (A<B) A B EQ GT LT EQ = (AB)' GT = A LT = A' ECOM4311 Dgtal Systems Desgn Page 1 ECOM4311 Dgtal Systems Desgn Page 2 Non-Iteratve Non-Iteratve - "Iteratve" refers to a crcut made up of dentcal blocks. The frst block performs ts operaton whch produces a result used n the 2nd block and so on. - Ths can be thought of as a "Rpple" effect - Iteratve crcuts tend to be slower due to the rpple, but take less area "Greater Than" - We can start at the MSB (n) and check whether A n >B n. - If t s, we are done and can gnore the rest of the LSB's. - If t s NOT, but they are equal, we need to check the next MSB bt (n-1) - Non-Iteratve crcuts consst of combnatonal logc executng at the same tme " - Snce each bt n a vector must be equal, the outputs of each bt's compare can be AND'd - To ensure the prevous bt was equal, we nclude t n the next LSB's logc expresson. - For a 4-bt comparator: EQ = (A3B3)' (A2B2)' (A1B1)' (A0B0)' ECOM4311 Dgtal Systems Desgn Page 3 ECOM4311 Dgtal Systems Desgn Page 4 Non-Iteratve Non-Iteratve - Steps - GT = A n n ' (ths s ONLY true f A n >B n ) - If t s NOT GT, we go to the n-1 bt assumng that A n = B n : (A n B n - We consder A n-1 >B n-1 only when A n = B n [.e., (A n B n A n-1 n-1 ') ] - We contnue ths process through all of the bts "Less - Snce we assume that f the vectors are ether EQ, GT, or LT, we can create LT usng: LT = EQ' - Ex. 4-bt comparator GT = (A3B3') + (A3B3)' (A2B2') + (A3B3)' (A2B2)' (A1B1') + (A3B3)' (A2B2)' (A1B1)' (A0B0') ECOM4311 Dgtal Systems Desgn Page 5 ECOM4311 Dgtal Systems Desgn Page 6

2 Iteratve n VHDL - We can buld an teratve comparator by passng sgnals between dentcal modules from MSB to LSB ex) module for 1-bt comparator EQ out = (AB)' EQ n - EQ out s fed nto the EQ n port of the next LSB module - Structural Model entty comparator_4bt s port (In1, In2 : n STD_LOGIC_VECTOR (3 downto 0); EQ, LT, GT : out STD_LOGIC); end entty comparator_4bt; archtecture comparator_4bt_arch of comparator_4bt s - The frst teratve module has EQ n set to '1' sgnal Bt_Equal : STD_LOGIC_VECTOR (3 downto 0); sgnal Bt_GT : STD_LOGIC_VECTOR (3 downto 0); sgnal In2_n : STD_LOGIC_VECTOR (3 downto 0); sgnal In1_and_In2_n : STD_LOGIC_VECTOR (3 downto 0); sgnal EQ_temp, GT_temp : STD_LOGIC; ECOM4311 Dgtal Systems Desgn Page 7 ECOM4311 Dgtal Systems Desgn Page 8 n VHDL n VHDL - Structural Model - Structural Model component xnor2 port (In1,In2: n STD_LOGIC; Out1: out STD_LOGIC); component or4 port (In1,In2,In3,In4: n STD_LOGIC; Out1: out STD_LOGIC); component nor2 port (In1,In2: n STD_LOGIC; Out1: out STD_LOGIC); component and2 port (In1,In2: n STD_LOGIC; Out1: out STD_LOGIC); component and3 port (In1,In2,In3: n STD_LOGIC; Out1: out STD_LOGIC); component and4 port (In1,In2,In3,In4: n STD_LOGIC; Out1: out STD_LOGIC); component nv1 port (In1: n STD_LOGIC; Out1: out STD_LOGIC); begn -- "Equal" Crcutry XN0 : xnor2 port map (In1(0), In2(0), Bt_Equal(0)); XN1 : xnor2 port map (In1(1), In2(1), Bt_Equal(1)); XN2 : xnor2 port map (In1(2), In2(2), Bt_Equal(2)); XN3 : xnor2 port map (In1(3), In2(3), Bt_Equal(3)); AN0 : and4 port map (Bt_Equal(0), Bt_Equal(1), Bt_Equal(2), Bt_Equal(3), Eq); AN1 : and4 port map (Bt_Equal(0), Bt_Equal(1), Bt_Equal(2), Bt_Equal(3), Eq_temp); -- 1st level of XNOR tree -- 2nd level of "Equal" Tree ECOM4311 Dgtal Systems Desgn Page 9 ECOM4311 Dgtal Systems Desgn Page 10 n VHDL n VHDL - Structural Model - Structural Model -- "Greater Than" Crcutry IV0 : nv1 port map (In2(0), In2_n(0)); IV1 : nv1 port map (In2(1), In2_n(1)); IV2 : nv1 port map (In2(2), In2_n(2)); IV3 : nv1 port map (In2(3), In2_n(3)); -- creatng In2' OR0 : or4 OR1 : or4 port map (In1_and_In2_n(3), Bt_GT(2), Bt_GT(1), Bt_GT(0), GT); port map (In1_and_In2_n(3), Bt_GT(2), Bt_GT(1), Bt_GT(0), GT_temp); AN2 : and2 port map (In1(3), In2_n(3), In1_and_In2_n(3)); -- creatng In1 & In2' AN3 : and2 port map (In1(2), In2_n(2), In1_and_In2_n(2)); AN4 : and2 port map (In1(1), In2_n(1), In1_and_In2_n(1)); AN5 : and2 port map (In1(0), In2_n(0), In1_and_In2_n(0)); AN6 : and2 port map (Bt_Equal(3), In1_and_In2_n(2), Bt_GT(2)); AN7 : and3 port map (Bt_Equal(3), Bt_Equal(2), In1_and_In2_n(1), Bt_GT(1)); AN8 : and4 port map (Bt_Equal(3), Bt_Equal(2), Bt_Equal(1), In1_and_In2_n(0), Bt_GT(0)); -- "Less Than" Crcutry ND0 : nor2 port map (EQ_temp, GT_temp, LT); end archtecture comparator_4bt_arch; ECOM4311 Dgtal Systems Desgn Page 11 ECOM4311 Dgtal Systems Desgn Page 12

3 Comparator Sgned - We dscussed Structural (Unsgned) - We can also descrbe behavorally - Sgned Comparator. - Unsgned Comparator. ECOM4311 Dgtal Systems Desgn Page 13 ECOM4311 Dgtal Systems Desgn Page 14 Carry Rpple Adder Comparator Unsgned Addton Half Adder - One bt addton can be accomplshed wth an XOR gate (modulo sum 2) Notce - The - Ths - It ECOM4311 Dgtal Systems Desgn Page 15 ECOM4311 Dgtal Systems Desgn Page 16 Carry Rpple Adder Carry Rpple Adder Addton Full Adder Addton Carry Rpple Adder - To Cn A B Cout Sum Sum = A B Cn Cout = Cn + ACn Cascadng Full Adders together wll allow the to propagate (or Rpple) through the crcut - Ths confguraton s called a Carry Rpple Adder - You could also use two "Half Adders" to accomplsh the same thng ECOM4311 Dgtal Systems Desgn Page 17 ECOM4311 Dgtal Systems Desgn Page 18

4 Carry Rpple Adder Carry Rpple Adder Addton Carry Rpple Adder Addton Carry Rpple Adder - What s the delay through the Full Adder? - What s the delay through the entre teratve crcut? - Each Full Adder has the followng logc: Sum = A B Cn Cout = Cn + ACn - t Full-Adder wll be the longest combnatonal logc delay path n the adder - The delay of the whole Carry Rpple Adder s t RCA = n Full-Adder - the delay ncreases lnearly wth the number of bts - dfferent topologes wthn the full-adder to reduce delay (t) wll have a (nt) effect ECOM4311 Dgtal Systems Desgn Page 19 ECOM4311 Dgtal Systems Desgn Page 20 Improvng Adder Performance Carry Rpple Adder VHDL Code Carry kll: Carry propagate: Carry generate: Adder equatons k x y p x y g x y x y c s c s p c c 1 g p c ECOM4311 Dgtal Systems Desgn Page 21 ECOM4311 Dgtal Systems Desgn Page 22 Addton Carry Look Ahead Adder Addton Carry Look Ahead Adder - To avod the rpple, we can buld a Carry Look-Ahead Adder (CLA) - Ths crcut calculates the carry for all Full-Adders at the same tme Propagate "p", an adder () wll propagate (or pass through) a carry n (C ) dependng on nput condtons A and B, : - We defne the followng ntermedate stages of a CLA: Generate "g", an adder () generates a carry out (C +1 ) under nput condtons A and B ndependent of A -1, B -1, or Carry In (C ) A B C we can say that: g = A remember, g does NOT consder carry n (C ) C A B C p s defned when there s a carry n, so we gnore the row entres where C = f we only look at the C =1 rows we can say that: p = (A +B C ECOM4311 Dgtal Systems Desgn Page 23 ECOM4311 Dgtal Systems Desgn Page 24

5 Addton Carry Look Ahead Adder Addton Carry Look Ahead Adder - Sad another way, Adder() wll "Generate" a Carry Out (C +1 ) f: g = A and t wll "Propagate" a Carry In (C ) when p = (A +B C - We can elmnate ths dependence by recursvely expandng each Carry Equaton ex) 4 bt Carry Look Ahead Logc C 1 = g 0 +p 0 0 (2-Level Product-of-Sums) - A full expresson for the Carry Out (C +1 ) n terms of p and g s gven by: C 2 = g 1 +p 1 1 C 2 = g 1 +p 1 g 0 +p 0 0 ) C 2 = g 1 +p 1 g 0 +p (2-Level Product-of-Sums) C +1 = g +p - Ths s good, but we stll generate Carry's dependant on prevous stages (-1) of the teratve crcut C 3 = g 2 +p 2 2 C 3 = g 2 +p 2 g 1 +p 1 g 0 +p ) C 3 = g 2 +p 2 g 1 +p 2 1 g 0 +p (2-Level Product-of-Sums) ECOM4311 Dgtal Systems Desgn Page 25 ECOM4311 Dgtal Systems Desgn Page 26 Addton Carry Look Ahead Adder Addton Carry Look Ahead Adder ex) 4 bt Carry Look Ahead Logc C 4 = g 3 +p 3 3 C 4 = g 3 +p 3 g 2 +p 2 g 1 +p 2 1 g 0 +p ) C 4 = g 3 +p 3 g 2 +p 3 2 g 1 +p g 0 +p (2-Level Product-of-Sums) - Ths gves us logc expressons that can generate a next stage carry based upon ONLY the nputs to the adder and the orgnal carry n (C 0 ) - The Carry Look Ahead logc has 3 levels 1) g and p logc 2) product terms n the C equatons 3) sum terms n the C equatons - The Sum bts requre 2 levels of Logc 1) A B C NOTE: A Full Adder made up of 2 Half Adders has 3 levels. But the 3rd level s used n the creaton of the Carry Out bt. Snce we do not use t n a CLA, we can gnore that level. - So a CLA wll have a total of 5 levels of Logc ECOM4311 Dgtal Systems Desgn Page 27 ECOM4311 Dgtal Systems Desgn Page 28 Addton Carry Look Ahead Adder Addton Carry Look Ahead Adder - The 5 levels of logc are fxed no matter how many bts the adder s (really?) - In realty, the most sgnfcant Carry equaton wll have +1 nputs nto ts largest sum/product term - Ths means that Fan-In becomes a problem snce real gates tend to have less than 4-6 nputs - In the worst case, the logc Fan-In would be 2. Even n ths case, the delay assocated wth the Carry Look Ahead logc would be proportonal to log 2 (n) - Area and Power are also concerns wth CLA's. Typcally CLA's are used n computatonally ntense applcatons where performance outweghs Power and Area. - When the number of nputs gets larger than the Fan-In, the logc needs to be broken nto another level ex) A+B+C+D+E = (A+B+C+D)+E ECOM4311 Dgtal Systems Desgn Page 29 ECOM4311 Dgtal Systems Desgn Page 30

6 Fast-Carry-Chan Adder Also called Manchester adder Desgn: Carry Look Ahead Adder VHDL x y x y +V p g p k c c c +1 c Xlnx FPGAs nclude ths structure s s ECOM4311 Dgtal Systems Desgn Page 31 ECOM4311 Dgtal Systems Desgn Page 32 Carry Look Ahead Adder VHDL Carry Look Ahead Adder VHDL ECOM4311 Dgtal Systems Desgn Page 33 ECOM DIGITAL SYSTEMS DESIGN Lecture #22 Page 34 Adders n VHDL Consderatons - (+) and (-) are not defned for STD_LOGIC_VECTOR - The Package STD_LOGIC_ARITH gves two data types: UNSIGNED (3 downto 0) := "1111"; SIGNED (3 downto 0) := "1111"; these are stll resolved types (STD_LOGIC), but the equalty and arthmetc operatons are slghtly dfferent dependng on whether you are usng Sgned vs. Unsgned - when addng sgned and unsgned numbers, the type of the result wll dctate how the operands are handled/converted - f assgnng to an n-bt, SIGNED result, an n-1 UNSIGNED operand wll automatcally be converted to sgned by extendng ts vector length by 1 and fllng t wth a sgn bt (0) ECOM4311 Dgtal Systems Desgn Page 35 ECOM4311 Dgtal Systems Desgn Page 36

7 Adders n VHDL Adders n VHDL ex) A,B : n UNSIGNED (7 downto 0); C : n SIGNED (7 downto 0); D : n STD_LOGIC_VECTOR (7 downto 0); S : out UNSIGNED (8 downto 0); T : out SIGNED (8 downto 0); U : out SIGNED (7 downto 0); S(7 downto 0) <= A + B; -- 8-bt UNSIGNED addton, not consderng Carry S <= ('0' & A) + ('0' & B); -- manually ncreasng sze of A and B to nclude Carry. Carry wll be kept n S(9) T <= A + C; -- T s SIGNED, so A's UNSIGNED vector sze s ncreased by 1 and flled wth '0' as a sgn bt U <= C + SIGNED(D); U <= C + UNSIGNED(D); -- D s converted (consdered) to SIGNED, -- not ncreased n sze -- D s converted (consdered) to UNSIGNED, -- not ncreased n sze ECOM4311 Dgtal Systems Desgn Page 37 ECOM4311 Dgtal Systems Desgn Page 38 Multplers Multplers Multplers "Shft and Add" Multplers - bnary multplcaton of an ndvdual bt can be performed usng combnatonal logc: A * B P we can say that: P = A example of Bnary Multplcaton usng our "by hand" method multplcand x 13 x multpler these are the ndvdual multplcands _ the fnal product s the sum of all multplcands - for mult-bt multplcaton, we can mmc the algorthm that we use when dong multplcaton by hand. - ths s called the "Shft and Add" algorthm S - Ths s smple and straght forward. BUT, the addton of the ndvdual multplcand products requres as many as n-nputs. - We would really lke to re-use our Full Adder crcuts, whch only have 3 nputs. ECOM4311 Dgtal Systems Desgn Page 39 ECOM4311 Dgtal Systems Desgn Page 40 Multplers Multplers "Shft and Add" Multplers "Shft and Add" Multplers - We can perform the addtons of each multplcand after t s created - Ths s called a "Partal Product" - Graphcal vew of product terms and summaton - To keep the algorthm consstent, we use "0000" as the frst Partal Product Orgnal multplcand x Orgnal multpler Partal Product for 1st multply Shfted Multplcand for 1st multply Partal Product for 2nd multply Shfted Multplcand for 2nd multply Partal Product for 3rd multply Shfted Multplcand for 3rd multply Partal Product for 4th multply Shfted Multplcand for 4th multply the fnal product s the sum of all multplcands ECOM4311 Dgtal Systems Desgn Page 41 ECOM4311 Dgtal Systems Desgn Page 42

8 Multplers Multplers "Shft and Add" Multplers "Sequental" Multplers - Graphcal Vew of nterconnect for an 8x8 multpler. Note the Full Adders - The man speed lmtaton of the Combnatonal "Shft and Add" multpler s the delay through the adder chan. - In the worst case, the number of delay paths through the adders would be [n + 2(n-2)] ex) 4-bt = 8 Full Adders 8-bt = 20 Full Adders - We can decrease ths delay by usng a regster to accumulate the ncremental addtons as they take place. - Ths would reduce the number of operaton states to [n-1] ECOM4311 Dgtal Systems Desgn Page 43 ECOM4311 Dgtal Systems Desgn Page 44 Multplers Multplers "Carry Save" Multplers "Carry Save" Multplers - Another trck to speed up the multplcaton s to break the carry chan - We can run the 0th carry from the frst row of adders nto adder for the 2nd row - A fnal stage of adders s needed to recombne the carres. But ths reduces the delay to [n+(n-2)] ECOM4311 Dgtal Systems Desgn Page 45 ECOM4311 Dgtal Systems Desgn Page 46 Sgned Multplers Sgned Multplers Multplers Convert to Postve - We leaned the "Shft and Add" algorthm for constructng a combnatonal multpler - One of the smplest ways s to frst convert any negatve numbers to postve, then use the unsgned multpler - But ths only worked for unsgned numbers - The sgn bt s added after the multplcaton followng: - We can create a sgned multpler usng a smlar algorthm pos x pos = pos pos x neg = neg neg x pos = neg neg x neg = pos Remember 0=pos and 1=neg n 2's comp so ths s an XOR ECOM4311 Dgtal Systems Desgn Page 47 ECOM4311 Dgtal Systems Desgn Page 48

9 Sgned Multplers Sgned Multplers 2's Comp Multpler 2's Comp Shft and Add Multplers - Remember that n a "Shft and Add', we created a shfted multplcand - The shfted multplcand corresponded to the weght of the multpler bt - We can use ths same technque for 2's comp rememberng that - the MSB of a 2's comp # s -2 (n-1) - We can perform the addtons of each multplcand after t s created - Ths s called a "Partal Product" - To keep the algorthm consstent, we use "0000" as the frst Partal Product - We also must remember that 2's comp addton must - be on same-szed vectors - the carry s gnored - We can make partal products the same sze as shfted multplcands by dong a "2's comp sgn ex) 1011 = = Snce the MSB has a negatve weght, we NEGATE the shfted multplcand for that bt pror to the last addton Orgnal multplcand x Orgnal multpler Partal Product for 1st multply w/ Sgn Extenson Shfted Multplcand for 1st multply w/ Sgn Extenson Partal Product for 2nd multply w/ Sgn Extenson Shfted Multplcand for 2nd multply w/ Sgn Extenson Partal Product for 3rd multply w/ Sgn Extenson Shfted Multplcand for 3rd multply w/ Sgn Extenson Partal Product for 4th multply w/ Sgn Extenson NEGATED Shfted Multplcand for 4th multply w/ Sgn Ext the fnal product s the sum of all multplcands gnore Carry Out ECOM4311 Dgtal Systems Desgn Page 49 ECOM4311 Dgtal Systems Desgn Page 50 Dvson Dvson Dvson - "Repeated Subtracton" Dvson - "Shft and Subtract" - \ - We need to develop an algorthm to perform a dvson. - Dvson s smlar to multplcaton, but nstead of "Shft and Add", we "Shft and Subtract" - A smple algorthm to dvde s to count the number of tmes you can subtract the dvsor from the dvdend - Ths s slow, but smple - The number of tmes t can be subtracted wthout gong negatve s the "Quotent" - If the subtracted value results n a zero/negatve number, whatever was left pror to the subtracton s the "Remander" ECOM4311 Dgtal Systems Desgn Page 51 ECOM4311 Dgtal Systems Desgn Page 52 Fxed-Pont Numbers Postonal Notaton Many applcatons use non-ntegers especally sgnal-processng apps Fxed-pont numbers allow for fractonal parts represented as ntegers that are mplctly scaled by a power of 2 can be unsgned or sgned In decmal In bnary Represent as a bt vector: bnary pont s mplct ECOM4311 Dgtal Systems Desgn Page 53 ECOM4311 Dgtal Systems Desgn Page 54

10 Unsgned Fxed-Pont Sgned Fxed-Pont n-bt unsgned fxed-pont m bts before and f bts after bnary pont n-bt sgned 2s-complement fxed-pont m bts before and f bts after bnary pont x m1 0 1 f xm 12 x0 2 x 12 x f 2 x m1 0 1 f xm 12 x0 2 x 12 x f 2 Range: 0 to 2 m 2 f Precson: 2 f m 0, gvng fractons only e.g., m = 2: Range: 2 m1 to 2 m1 2 f Precson: 2 f E.g., , sgned fxed-pont, m = = = ECOM4311 Dgtal Systems Desgn Page 55 ECOM4311 Dgtal Systems Desgn Page 56 Choosng Range and Precson Fxed-Pont n VHDL Choce depends on applcaton Use std_logc lbrares wth mpled scalng Need to understand the numercal behavor of computatons performed some operatons can magnfy quantzaton errors In DSP fxed-pont range affects dynamc range precson affects sgnal-to-nose rato Use proposed fxed_pkg package Currently beng standardzed by IEEE Types ufxed and sfxed Arthmetc operatons, reszng, converson Perform smulatons to evaluate effects lbrary eee_proposed; use eee_proposed.fxed_pkg.all; entty fxed_converter s port ( nput : n ufxed(5 downto -7); output : out sfxed(7 downto -7) ); end entty fxed_converter; ECOM4311 Dgtal Systems Desgn Page 57 ECOM4311 Dgtal Systems Desgn Page 58 Fxed-Pont Operatons Floatng-Pont Numbers Just use nteger hardware e.g., addton: Smlar to scentfc notaton for decmal f f f x y ( x2 y2 ) / 2 a a a a x 0 10-bt adder e.g., , Allow for larger range, wth same relatve precson throughout the range a 3 x 7 x 8 s 0 c Ensure bnary ponts are algned b b 3 x 9 y 0 y 7 s 7 s 8 s 9 c 3 c 4 c b 4 b 5 y 8 y 9 mantssa radx exponent ECOM4311 Dgtal Systems Desgn Page 59 ECOM4311 Dgtal Systems Desgn Page 60

11 IEEE Floatng-Pont Format s: sgn bt (0 non-negatve, 1 negatve) Normalze: 1.0 M < 2.0 M always has a leadng pre-bnary-pont 1 bt, so no need to represent t explctly (hdden bt) e bts s exponent x M 2 E m bts mantssa ( 1 s) 1. mantssa2 Exponent: excess representaton: E + 2 e1 1 e exponent Floatng-Pont Range Exponents and reserved Smallest value exponent: E = 2 e1 + 2 mantssa: M = 1.0 Largest value exponent: E = 2 e1 1 mantssa: M 2.0 Range: 2 e1 2 2 x 2 e1 2 ECOM4311 Dgtal Systems Desgn Page 61 ECOM4311 Dgtal Systems Desgn Page 62 Example Formats Denormal Numbers IEEE sngle precson, 32 bts e = 8, m = 23 7 decmal dgts Applcaton-specfc, 22 bts e = 5, m = 16 5 decmal dgts Exponent = hdden bt s 0 x M 2 E Smaller than normal numbers allow for gradual underflow, wth dmnshng precson Mantssa = ( 1 s) 0. mantssa2 e x M 2 E ( 1 s) e ECOM4311 Dgtal Systems Desgn Page 63 ECOM4311 Dgtal Systems Desgn Page 64 Infntes and NaNs Floatng-Pont Operatons Exponent = , mantssa = Infnty Can be used n subsequent calculatons, avodng need for overflow check Exponent = Not-a-Number (NaN) Indcates llegal or undefned result e.g., 0.0 / 0.0 Can be used n subsequent calculatons Consderably more complcated than nteger operatons E.g., addton unpack, algn bnary ponts, adjust exponents add mantssas, check for exceptons round and normalze result, adjust exponent Combnatonal crcuts not feasble Ppelned sequental crcuts ECOM4311 Dgtal Systems Desgn Page 65 ECOM4311 Dgtal Systems Desgn Page 66

12 Floatng-Pont n VHDL Use proposed float_pkg package Currently beng standardzed by IEEE Types float, float32, float64, float128 Arthmetc operatons, reszng, converson Not lkely to be syntheszable Rather, use to verfy results of hand-optmzed crcuts ECOM4311 Dgtal Systems Desgn Page 67