A Low Error and High Performance Multiplexer-Based Truncated Multiplier

Transcription

1 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 1, DECEMBER A Low Error and Hgh Performance Multplexer-Based Truncated Multpler Chp-Hong Chang and Rav Kumar Satzoda Abstract Ths paper proposes a novel adaptve pseudo-carry compensaton truncaton (PCT) scheme, whch s derved for the multplexer based array multpler. The proposed method yelds low average error among exstng truncaton methods. The new PCT based truncated array multpler outperforms other exstng truncated array multplers by as much as 5% n terms of slcon area and delay, and consumes about 40% less dynamc power than the full-wdth multpler for 3-bt operaton. The proposed truncaton scheme s appled to an mage compresson algorthm. Due to ts low truncaton error, the mean square errors (MSE) of varous reconstructed mages are found to be comparable to those obtaned wth full-precson multplcaton. Index Terms Computer arthmetc, dgtal multpler, truncated multpler, truncaton scheme, VLSI desgn. I. INTRODUCTION Multplcaton s a fundamental arthmetc operaton used pervasvely n dgtal sgnal processng (DSP) applcatons lke flterng, convoluton, and compresson [1]. From VLSI perspectve, snce a full-wdth dgtal multpler receves two sngle precson operands to produce a double precson output, t greatly benefts from truncaton for applcatons wth a lmted-precson datapath. Due to the noteworthy hardware reducton, the dynamc power dsspaton can also be proportonally reduced wthout havng to resort to sophstcated power reducton technques. Several truncaton schemes have been proposed for fast dgtal multplers [] [10]. The schemes proposed n [3] and [4] gnore the least sgnfcant n columns n the partal product (pp) bt matrx obtaned from an n n-bt multplcaton. A small amount of addtonal hardware s added to compensate for the truncaton errors. These methods generally produce hgh error for the truncated product. The second category of truncaton schemes preserves the hardware used to compute k addtonal pp bts beyond the ulp of the truncated product [5] [9]. In [5], Schulte et al. ntroduces a constant-correcton truncaton (CCT) scheme where a non-zero dc component s added based on specfc values of n and k, to Columns (n 0 1) to (n 0 k) of the pp matrx. In [6], a data-dependent varable correcton truncaton scheme (VCT) s proposed where the most sgnfcant pp bts from the (n 0 k 0 1) th column are stacked over the (n 0 k) th column and a constant bas of 1 s added n Columns (n 0 ) to (n 0 k) [7]. In ths paper, we propose a novel truncaton scheme for the multplexer based array multpler [11]. A bref antecedent of ths work was presented n [10]. The proposed method acheves lower average and spread of errors by means of an adaptve pseudo carry compensaton and a smple determnstc constant bas that s ndependent of k. By explotng the symmetry of the multplexer-based array multpler, the pp bts generated by the multplexers n our truncated multpler can be accumulated n a carry-save format to further reduce the area and mprove the speed over other truncated array multplers. Manuscrpt receved December 3, 008; revsed Aprl 4, 009. Frst publshed September, 009; current verson publshed November 4, 010. The authors are wth the Nanyang Technologcal Unversty, School of Electrcal and Electronc Engneerng, Sngapore (e-mal: echchang@ntu. edu.sg; rksatzoda@ntu.edu.sg). Dgtal Object Identfer /TVLSI Fg. 1. Truncated multplexer matrx for an 8 8-bt multpler; (= 8) most sgnfcant columns and (= ) addtonal columns of multplexers are ndcated; multplexers n the ( 1) column = 5 are replaced wth AND cells correspondng to the carry sgnals. II. NEW TRUNCATED MULTIPLICATION SCHEME The product of two n-bt postve ntegers X = x x n0...x 1 x 0 and Y = y y n0...y 1y 0 s a n-bt product P = XY. In [7], the numbers are assumed to be fractonal n ther error analyss and the nputs and output are scaled by a factor of 0n and 0n, respectvely. For multplexer-based array multpler [11], two new varables X = x n0x n03 111x 0 and Y = y n0y n03 111y 0 are defned such that P = fx + x gfy + y g = (x 1 y ) + M (1) =0 where M = x 1 Y + X 1 y. M can be mplemented as a multplexer wth x and y as select sgnals. M =0, X, Y and X + Y when x y = \00", 01, 10 and 11, respectvely. (1) can be realzed by a multplexer array shown n [11, Fg. 3]. Wthout loss of generalty, our proposed truncated scheme can be explaned wth the help of a truncated multplexer matrx of Fg. 1 wth n =8and k =, where k s the number of partal product (pp) columns to be kept beyond the wdth, n of the truncated product. Usng VCT scheme, the multplexers from Column 5 (.e., n 0 k 0 1) wll be stacked on Column 6 (.e., n 0 k). However, the product bt n Column 6 s dependent on the carry s generated from Column 5 nto Column 6 rather than the sum of ts pp bts. Drectly stackng the pp bts of Column 5 onto Column 6 can also create excessve error due to the carry propagated nto Column 7 (.e., n 0 k +1). From the defnton of M, f both x and y are 1 s, then the sum of X and Y s selected. If the select sgnals of all the multplexers n Column 5 are 1 s, then the sums of the multplexer nputs,.e., s 0, s 1, and s, are selected. In the worst case, the carry sgnals, c 0 = x 0 1 y 0, c 1 = x 1 1 y 1, and c = x 1 y are obtaned. Our dea s to add the carry sgnals generated from the nputs to the multplexers n the (n 0 k 0 1) th column to the (n 0 k) th column. The error s reduced as only the necessary carry s from the (n0k 01) th column are added to the (n0k) th column. The error s stll present, though, because of the assumpton that all select sgnals of the multplexers n the () th are 1. Ths approach s, however, closer to the carry propagaton n full-wdth multpler as opposed to VCT /$ IEEE

2 1768 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 1, DECEMBER 010 To mnmze the truncaton error for an unsgned nteger multplcaton, a new pseudo-carry compensated truncaton (PCT) scheme consstng of an adaptve compensaton crcut and a fxed bas s proposed. Hardware reducton s acheved by retanng only the n+k most sgnfcant columns of the multplexer matrx. The reducton error s adaptvely compensated by addng the carry s that are generated from the summaton of the multplexer nputs from the () th column,.e., c = x 1 y for f0; 1;...; d(n 0 k)=e 01g to the (n 0 k) th column. The roundng error s compensated by addng a fxed bas of 0.5 LSB, rrespectve of the values of n and k. Ths roundng constant can be added by smply nsertng a one n the (n 0 1) th column. Fnally, the n-bt truncated product, P t, wth ts least sgnfcant bt weghted 0, s gven by P t = =r + r01 =0 M 0n + =b r01 c M t r0n + =b c (x 1 y ) 0n (x 1 y ) r0n + 01 () where r = n 0 k, M t = x 1 Y t + X t 1 y, Y t = y 01y 0 111y r0, and X t = x 01x 0 111x r0. M t can be consdered as a truncated expresson for M wth truncated X t and Y t. In Fg. 1, M t3, M t4, and M t5 are the truncated multplexer rows correspondng to M 3, M 4, and M 5. It should be noted that P t of P t corresponds to P n+ of the full-wdth multpler s product, P. In order to derve the average error of the proposed PCT scheme, each nput bt x and y s assumed to have equal probablty. The probablty that the output of a -nput AND gate s a one s P a (x ;y )= P x P y =0:5. For a 4-to-1 multplexer, however, the output, f dependent on the select sgnals, s 1 and s and the nputs, 1,, 3, and 4 s gven by f = s 1 1 s s 1 1 s 1 + s 1 1 s s 1 1 s 1 4: (3) Snce s 1 and s are mutually exclusve, f all the data and select sgnals are equally probable to be 1 or 0, the probablty of f beng a one s P f = 0:5. However, ths assumpton does not hold for the multplexers n Fg. 1. Two types of multplexers wth constant nputs are used. Type-1 multplexer conssts of four data nputs, x, y, s, and 0, and two select sgnals, x j, y j n any permutable order. Snce the constant nput has a probablty of 0, the probablty that ths multplexer outputs a one reduces to P f1 =0:375. Type- multplexer comprses four data nputs, 0, 0, 0, and c, and two select sgnals, x j and y j. The data nput, c can be wrtten as c = x 1y +(x +y )1c 01 and ts expected value s gven by P c = P x 1y + P (x +y )1c 0 P (x 1y )1(x +y )1c =0:5 + 0:75P c 0 0:5 1 0:75P c =0:5 + 0:565P c : (4) Unrollng the above carry probablty equaton generates a geometrc progresson seres wth a common rato of Ths sum approaches rapdly. Therefore, P c s assumed an asymptotc value of and the probablty that a type- multplexer outputs a one s P f =0:143. Let 1 and be the pp bts generated respectvely by the type-1 and type- multplexers n the th column of the multplexer matrx. If we normalze the weghts of the pp bts of the truncated multplexer matrx to the ulp of the truncated product so that the LSB of the fullwdth product wth column ndex =0s weghted 0n, the expected values of 1 and are gven by E [ 1 ]= 1 = P f1 0n E [ ]= = P f 0n (5) where f0; 1;...;n0 k 0 1g. Smlarly, the expected value of the output of an AND gate n the th column s gven by E [ and ]= and = P a 0n 8 f0; 1;...;n0 k 0 1g: (6) These expected values can be used to compute the followng. Reducton Error: Elmnaton of the multplexers and AND gates n the least sgnfcant n 0 k columns of the multplexer matrx of full-wdth multpler leads to reducton error. Each even column, except Column 0, has one type- multplexer, one AND gate and some even number of type-1 multplexers. Column 0 conssts of only an AND gate. On the other hand, each odd column possesses some odd number of type-1 multplexers only. The values of even and odd depend on the column number,, where even = odd = d=e. The expected value, E(mux1) reduce of the reducton error contrbuted by neglectng type-1 multplexers n any even column, except =0s gven by E(mux1) reduce = even 1 = P f1 0n : (7) Smlarly, the expected value of the error due to type- multplexer and AND gate, E(mux^) reduce n any even column except column 0 s gven by E(mux^) reduce = + and =(P f + P a) 0n : (8) The expected error for the 0-th column s just equal to and. Snce the th odd column has odd = d=e of type-1 multplexers, the expected error, E(odd) reduce of elmnatng the th odd column s gven by E(odd) reduce = odd 1 = P f1 0n 8 odd : (9) From (7) (9), the total reducton error, E reduce, due to the elmnaton of Columns 0 to n 0 k 0 1 s gven by E reduce = 0n P a ; =0 = P f1 + P f + P a 0n ; 8 even P f1 0n ; 8 odd : (10) Roundng Error: The expected value of P 0 s 0.5 but the expected value of P quckly approaches 0.5 as ncreases. Snce k s small, a unform probablty of 0.5 can be assumed for P n0k to P. Thus, the expected value of error, E round, nduced by gnorng the product bts n the addtonal k columns s gven by E round =0:5 =n0k 0n =0:5 k j=1 0j : (11) Total Error Before Compensaton: From (10) and (11), the expected value of the total error s defned as E total = 0(E round + E reduce ): (1) The reducton and roundng errors are assumed to be negatve. The correcton bas s assumed to be postve to counteract the total error so that the mean error approaches zero.

3 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 1, DECEMBER Correcton: The carry sgnals from the (n 0 k 0 1) th column are added to the (n 0 k) th column. The carry bt s obtaned by a logcal AND operaton,.e., c = x 1 y. Hence the probablty of c beng a one s P c = P xp y =0:5. Besdes, a correcton constant of half-lsb s added. Thus, the entre compensaton has an expected value of C =0:5 + n 0 k P c 0k : (13) From (10) (13), the mean error of the truncated multpler, E avg, s gven by E avg = E total + C = 0(E round + E reduce )+C: (14) For the computaton of varance, we assume that the reducton and roundng errors are ndependent [5]. Ths assumpton gves an underestmate of the actual varance. For the th column, where 0 <<n0k, the varances 1,, and and respectvely of the output of type-1 multplexer, type- multplexer and AND gate are gven by 1 = (0n) ; 1 = 6 49 (0n) ; and = 3 16 (0n) : (15) In an even column, except =0, the varance s due to d=e number of type-1 multplexers, one type- multplexer and one AND gate,.e., even = d=e1 + + and.for = 0, the varance s due to an AND gate,.e., and. The varance of the reducton error by elmnatng an th odd columns s contrbuted by d=e number of type-1 multplexers. So the varance of the total reducton error by elmnatng Columns 0 to n 0 k 0 1 s reduce = n ; =0 = (0n); 8 even (0n); 8 odd : (16) The varance of the roundng error s defned as the mean square dfference between the roundng correcton constant and the value of the truncated bts [5]. Roundng correcton constant C round s added to compensate for the total error and s equal to the dfference between the correcton, C and the total reducton error E reduce 01 round = 0k (C round 0 q 1 0k ) : (17) q=0 Hence the varance of the total error s gven by total = round + reduce: (18) The error hstogram obtaned by an exhaustve smulaton wth all nput combnatons of an 8-bt proposed truncated multpler for k = s shown Fg.. The Gaussan curve wth the theoretcal mean and varance follows the best-ft Gaussan to the error hstogram, whch valdate the accuracy of our error analyss. In Table I, we compare the average errors E avg and varances of PCT aganst CCT and VCT for n = 8, 1, and 16 and k =, 3, and 4. The archtectures for n = 8 were smulated exhaustvely for all possble nput vectors. However, for n = 1and n = 16, an exhaustve smulaton s not feasble and two mllon pseudo-random nput vectors were generated to smulate these archtectures. Besdes, we also compare PCT aganst the average errors and varances of the truncaton schemes reported n [1] and [13]. The average errors of [13] are avalable for n =8wth k =1and k =only. For n =1and 16, the average errors were provded n [13] wthout ndcatng ther k values. From Table I, the proposed PCT scheme has lower mean and Fg.. Comparson of expermental result hstogram for =8and = and the Gaussan curve generated from the theoretcal mean and varance. NA: Not avalable TABLE I COMPARISON OF AND varance for most values of n and k and the mert s more sgnfcant for k >. In cases where t s nferor, the error magntudes are stll comparable. Usng the same percentage relatve average error measure as n [8] for k =, our proposed PCT scheme produces a relatve average error of.55% and 1.4% over the drect-truncated structure for n =8and 16, respectvely. These values are nearly 4.4 tmes lower than the correspondng relatve average errors of [8]. III. CS-MUX IMPLEMENTATION OF PSEUDO-CARRY COMPENSATION TRUNCATED MULTIPLIER Fg. 3 shows the carry-saved multplexer (CS-MUX) array mplementaton of the PCT scheme for n =8and k =. The outputs from each row of multplexers n Fg. 1 are added n a carry-save format usng full adders (FAs) and half adders (HAs). These FAs and HAs are combned wth 4-to-1 multplexers to gve FMUX and HMUX. Except the multplexer cells n the boundary, cells n the nteror of the carry-save array archtecture receve an addtonal sum sgnal from a precedng multplexer cell. Therefore, HMUX cells are placed at the boundary and FMUX cells are placed n the nteror of the array. The outputs from the topmost multplexer and the AND gate n every even column of the multplexer matrx n Fg. 1 are summed n an SA cell. These basc cells are smlar to those shown n [11] and are llustrated n Fg. 3. rpple carry adders (RCAs) are used to add the fnal sum and

4 1770 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 1, DECEMBER 010 TABLE II DELAY-AREA-POWER COMPARISON OF PCT AND VCT Fg. 3. Unsgned sgned PCT multpler archtecture for =8and = wth ts components HMUX, FMUX, SA. TABLE III IMAGE COMPRESSION METRICS carry. In addton, the MA cell at the lower left corner of the CS-MUX archtecture s equvalent to a smplfed SA cell wth one FA and one HA. The RCA on the left end s substtuted by a FOA cell to logcally OR the two carres from the FA and MA cells to produce the MSB, p t(). The adaptve error compensaton s realzed by the AND cells on the top rght, and the fxed correcton bas s realzed wth an nput 1 placed on the leftmost HMUX n the frst row. The CS-MUX array mplementaton can be extended to the sgned PCT multplcaton. (1) can be modfed to (19) when two n-bt sgned ntegers X and Y n s complement form are consdered, as n [11] n0 P = XY = (x 1 y ) + M 0 M : (19) =0 Equatons (1) and (19) dffer only by the negatve M. Thus, the outputs from the last row correspondng to the term, M are to be subtracted. To account for the negatve M, the outputs of the HMUX cells that le on the left boundary of Fg. 3 are nverted. The two 1 s to be added to the (n 0 ) th column of the multplexer matrx of Fg. 1 for the subtracton are equvalent to two 0.5 LSBs for the n-bt normalzed truncated product. The correcton bas for the roundng error to be added n the () th column s equvalent to 0.5 LSB of the truncated product. They total up to 1 LSB of the truncated product. A smple chan of HAs can be used to add ths constant 1 to the LSB of the fnal truncated product obtaned from the row of RCAs n Fg. 1. The error analyss descrbed n Secton II s stll vald for the sgned PCT multplcaton. IV. RESULTS AND DISCUSSION Snce the sgned PCT multpler has comparable hardware complexty as ts unsgned verson, t s suffcent to compare only the unsgned varants of the truncated multplers. The archtectures were descrbed usng structural VHDL and syntheszed and optmzed by Synopsys Desgn Compler usng the same TSMC 0.18-m CMOS standard cell lbrary. The nput and output loads were set to 0.8 pf for all desgns. The synthess results of varous truncated multplers for n = 16and 3, and k = to 5 are shown n Table II. Our proposed truncated multpler consumes less slcon area than VCT array multplers consstently for all values of n and k. The area savngs of our proposed truncated multpler for n =16vares between 14% to 0% when t s collated wth VCT array multpler. When the nput wordlength ncreases to n = 3, the proposed truncated multpler occupes 1% to 8% less area than VCT multpler. It s worth notng that PCT multpler wth k =saves 33% and 41.5% of slcon area over ts full-wdth counterpart for n =16and n =3, respectvely, although ther speeds are comparable. In terms of crtcal path delay, the proposed PCT multpler s faster than the VCT array multpler by 1% and 7% for n = 16 and 3, respectvely. We have also technology mapped, optmzed and smulated the redundant bnary fxed-wdth multpler codes for n = 10 provded by the author of [1] usng the same standard cell lbrary and smulaton setup. The archtecture of [1] s found to be 13% faster than our PCT multpler but consume 65% more area than our desgn. The average power dsspatons of dfferent archtectures were smulated by Synopsys Power Compler [14] usng a Monte Carlo model [15]. Ths statstcal method provdes a good confdence that the estmated average power s bound wthn a gven error [14] wthout the need for an exhaustve smulaton of all nput vectors. Table II shows the mean dynamc power dsspatons wth a confdence level of 90% and an error bound of 3% for 16-bt truncated multplers and 5% for 3-bt truncated multplers for k 8. The proposed truncated multpler dsspates slghtly more dynamc power but no more than 5% above the VCT truncated multplers for all n and k. It stll consumes a noteworthy 35% and 4% lower power than ts full-wdth counterpart for n = 16and 3, respectvely. In terms of leakage power, the proposed PCT multpler s lower than VCT multpler by as much as 8%. The proposed truncated multplcaton scheme s appled to a DCTbased mage compresson algorthm, JPEG [16]. 1-bt multplcatons are used n the compresson and decompresson operatons. Table III shows the mean square errors (MSE) of three mages wth varous compresson ratos (CR) obtaned by usng the full-wdth (FW) multpler and the proposed PCT multpler wth k =and 6. The devatons n peak sgnal-to-nose rato (PSNR) are less than 1 db even for k =. The 1-bt s complement truncated multpler wth k = also saves about 30% area and 14% power over ts full-wdth counterpart at the same speed of operaton.

5 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 1, DECEMBER V. CONCLUSION The effcency of dgtal multplcaton can be mproved tremendously by truncaton methods provded precse outputs are not requred for the operaton. Ths paper proposed a new multplexer based truncaton scheme wth lower average and mean square errors than exstng truncaton methods. Its VLSI mplementaton on TSMC 0.18 m technology shows an area reducton over exstng truncated array multplers by at least 14% and 1% n 16- and 3-bt multplcatons, respectvely. It also runs faster than the VCT multpler by more than 1% wth comparable dynamc power dsspaton. When the new truncated multplcaton was ncorporated nto JPEG mage compresson, the dfferences n PSNR of the reconstructed mages were wthn 1 db from those obtaned wth full-precson multplcaton. REFERENCES [1] U. M. Baese, Dgtal Sgnal Processng Wth Feld Programmable Gate Arrays. Berln, Germany: Sprnger, 004. [] V. Mahalngam and N. Ranganathan, An effcent and accurate logarthmc multpler based on operand decomposton, n Proc. VLSI Des., Jan. 006, p. 6. [3] N. Yoshda, E. Goto, and S. Ichkawa, Pseudorandom roundng for truncated multplers, IEEE Trans. Computers, vol. 40, no. 9, pp , Sep [4] J. M. Jou, S. R. Kuang, and R. D. Chen, Desgn of low-error fxed wdth multplers for DSP applcatons, IEEE Trans. Crcuts Syst. II, Analog Dgt. Sgnal Process., vol. 46, no. 6, pp , Jun. 99. [5] M. J. Schulte and E. E. Swartzlander, Jr., Truncated multplcaton wth correcton constant, n Proc. IEEE Workshop VLSI Sgnal Process. VI, Oct. 1993, pp [6] E. J. Kng and E. E. Swartzlander, Jr., Data-dependent truncaton scheme for parallel multplers, n Proc. 31st Aslomar Conf. Sgnals, Syst. Comput., Nov. 1997, vol., pp [7] M. J. Schulte, J. E. Stne, and J. G. Jansen, Reduced power dsspaton through truncated multplcaton, n Proc. IEEE Alessandro Volta Memoral Workshop Low-Power Des., Mar. 1999, pp [8] L. -D. Van and C. -C. Yang, Generalzed low-error area-effcent fxedwdth multplers, IEEE Trans. Crcuts Syst. I, Reg. Papers, vol. 5, no. 8, pp , Aug [9] Y. C. Lm, Sngle-precson multpler wth reduced crcut complexty for sgnal processng applcatons, IEEE Trans. Comput., vol. 41, no. 10, pp , Oct [10] C. H. Chang, R. K. Satzoda, and S. Sekar, A novel multplexer based truncated array multpler, n Proc. IEEE Int. Symp. Crcuts Syst. (ISCAS), Kobe, Japan, May 005, pp [11] K. Z. Pekmestz, Multplexer-based array multplers, IEEE Trans. Comput., vol. 48, no. 1, pp. 15 3, Jan [1] T. B. Juang and S. F. Hsao, Low-error carry-free fxed-wdth multplers wth low-cost compensaton crcuts, IEEE Trans. Crcuts Syst. II, Exp. Brefs, vol. 5, no. 6, pp , Jun [13] K. J. Cho, K. C. Lee, J. G. Chung, and K. K. Parh, Desgn of low-error fxed-wdth modfed Booth multpler, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 1, no. 5, pp , May 004. [14] R. K. Satzoda, C. H. Chang, and T. Srkanthan, Monte Carlo statstcal analyss for power smulaton n Synopsys desgn compler, presented at the Synopsys Users Group Conf., Sngapore, Jun. 006 [Onlne]. Avalable: [15] R. Burch, F. N. Najm, P. Yang, and T. N. Trck, A Monte Carlo approach for power estmaton, IEEE Trans. Very Large Scale Integr. Syst., vol. 1, no. 1, pp , Mar [16] D. Salomon, Data Compresson The Complete Reference, nd ed. New York: Sprnger-Verlag, 000.