Implementation and Study of Reversible Binary Comparators

Transcription

1 Implementaton and Study of Reversble Bnary Comparators Harth M, C Vasanthanayak Abstract Reversble logc contans a feature of recoverng bt loss from unque nput-output mappng. Usng tradtonal (rreversble) logc gates always lead to energy dsspaton because of loss of nformaton bts. Thus the recoverng bt loss feature of reversble logc reduces power dsspaton. Ths wll eventually lead to hgher denstes and speed. Comparators are used n most of the dgtal computaton systems lke mcro controllers and mcroprocessors, communcaton systems, encrypton and decrypton devces and many more. Ths extensve use of comparators demands low power and hgh speed. For meetng ths demand, many reversble comparators are beng proposed. In ths paper, four effcent reversble comparators are mplemented and ther performance s analyzed. A comparatve study has been done and the best performer s determned. Index Terms Bnary comparators, reversble Logc, quantum computng I. INTRODUCTION One of the serous problem faced by today s computer chps s power dsspaton and therewth heat generaton. The fundamental reason for power dsspaton came nto lght from the observatons made by Landauer n 96 []. Landauer proved that usng tradtonal (rreversble) logc, gates always lead to energy dsspaton. More precsely, exactly kt log 2 Joules of energy s dsspated for each nformaton bt lost durng the rreversble operaton (where k s the Boltzmann constant and T s the temperature). Whle ths amount of power currently does not sound sgnfcant, t may become crucal consderng the fact that mllons of operatons are performed and thereby leadng to loss of lot of nformaton bts. Bennett showed that energy dsspaton s reduced or even elmnated f computaton becomes nformaton-loss less [2]. The amount of energy dsspated n a system has a drect relatonshp to the number of bts erased durng computaton. Reversble computaton n a system can be performed only when the system conssts of reversble gates. These crcuts generate a unque output vector from each nput vector, and vce-versa. In a reversble crcut, there s a one-to-one mappng between nput and output vectors [3], [4]. The extreme mportance of Bennett s theorem [2] les n the fact that every future technology would have to use reversble gates to reduce power. Comparson of bnary numbers fnds dverse range of applcatons n general purpose mcroprocessors, communcaton systems, encrypton devce, sortng networks etc.. In tradtonal bnary comparators, tradtonal (rreversble) logc gates are used and t dsspate power as nformaton bts are lost. Reversble Bnary comparators dsspates less power. Due to ts sgnfcance, several reversble comparator crcuts have been proposed. An effcent reversble logc crcut should be desgned wth mnmum number of gates, Constant nputs, Garbage outputs and Quantum cost [5]. In ths work, four exstng effcent reversble bnary comparators are mplemented and analyzed. From comparson of parameters lke power, area, delay, mnmum number of gates, Constant nputs, Garbage outputs and Quantum cost, the best one s dentfed. Thus adng the researchers n choosng a sutable comparator. The paper s organzed wth the followng sectons: Secton II descrbes reversble gates and the defntons of parameters beng compared. Secton III gves detals about four reversble comparators. Secton IV gves the comparsons of all the reversble comparator crcuts. Fnally, the paper s concluded n Secton V. II. BASIC DEFINITIONS AND LITERATURE OVERVIEW A. Reversble Gates Reversble gates are gates that have the same number of nputs and outputs and are one-to-one mappngs between vectors of nputs and outputs, thus the vector of nput values can be always unquely reconstructed from the vector of output values. Fg. shows a k x k reversble gate. Fg. : k x k Reversble gate The reversble gates used n ths paper are: ) NOT Gate NOT gate [Fg. 2] s the smplest reversble gate wth zero Quantum cost. It s a x reversble gate. 2) FEYMAN Gate Fg 2: NOT gate Fg. 3 shows a 2 x 2 Feynman gate [6]. Quantum cost of a Feynman gate s. Harth M, Department of Electroncs and Communcaton Engneerng, Government College of Technology,Combatore, Inda, C Vasanthanayak, Department of Electroncs and Communcaton Engneerng, Government College of Technology, Combatore, Inda, Fg. 3: FEYMAN Gate 890

2 3) TOFFOLI Gate Toffol gate (Fg. 4) [7] whch s a 3x 3 gate wth nputs (A, B, C) and outputs P = A, Q = B, R = AB C. It has Quantum cost 5. 4) PERES Gate Fg. 4: TOFFOLI Gate Peres gate [8] whch s a 3 x 3 gate havng nputs (A,B,C) and outputs P = A; Q = A B; R = AB C. It has Quantum cost 4. Fg. 7: BJS Gate 5) TR Gate Fg. 5: PERES Gate TR gate [9] s a 3 x 3 gate and ts logc crcut and ts quantum mplementaton s as shown n the Fg.6. It has quantum cost 6. 6) BJS Gate Fg. 6: TR Gate BJS gate [0] s a 4 x 4 gate wth nputs (A, B, C, D) and outputs Q AC A, R AC AB, P A, B S A B C D. It has a quantum cost of 6. 7) HLN Gate HLN gate [0] s a 3 x 3 gate wth nputs (A, B, C) and P A, S A B C, R AC AB outputs has a quantum cost of 5.. It B. Quantum Cost Fg. 8: HLN Gate Quantum cost refers to the cost of a crcut n terms of elementary quantum gates []. The most used elementary quantum gates are the NOT gate (a sngle qubt s nverted), the CNOT gate (the target qubt s nverted f the sngle control qubt s ), the controlled-v gate (also known as a square root of NOT, snce two consecutve V operatons are equvalent to an nverson), and the controlled-v + gate (whch performs the nverse operaton of the V gate and thus s also a square root of NOT []). C. Delay The delay of a logc crcut s the maxmum number of gates n a path from any nput lne to any output lne. Ths defnton s based on the followng two assumptons [2]: frstly, each gate performs the computaton n one unt tme. Secondly, all nputs to the crcut are known before the computaton begns. D. Garbage Output Garbage Output s the unwanted or unused output of a reversble gate (or crcut). Garbage output(s) s (are) needed only to mantan the reversblty [2]. E. Power The power dsspaton of a logc crcut s the summaton of ndvdual power dsspatons of each gate of the crcut. F. Area The area of a logc crcut s the summaton of ndvdual 89 All Rghts Reserved 207 IJARCET

3 area of each gate of the crcut. III. REVERSIBLE BINARY COMPARATORS In 200, Hmanshu et al. proposed the dea of tree based desgn of a reversble comparator [3]. Ths desgn s based on a new reversble gate called the TR gate [Fg. 6]. Ths comparator has a bnary tree structure n whch each node s a 2-bt comparator cell that wll compare two 2-bt numbers A (A A 0 ) and B (B B 0 ) to generate two outputs G ;0 and L,0 ndcatng A > B and A < B respectvely. A 2-bt comparator desgn was also proposed by them whch use R- Bcomp modules. The R-Bcomp module uses TR gates and s shown n the fgure 9b.The R-Bcomp module s a crcut whch generates e A B where e A B, AB A B ndcates l whch ndcates A <B, and g ndcates A > B. The R-Bcomp s bascally a -bt comparator whch generates greater, lesser and equal sgnals and are combned together usng TR gates accordng to the equatons () to desgn a 2-bt comparator. L l e,0 l0,0 g e g0 G () The 2-bt reversble comparator desgn usng the R-Bcomp modules s shown n Fg. 9c. The desgn of 8-bt comparator along wth a reversble output crcutry s shown n Fg. 9a.Output crcutry (Fg. 9d) generate E L G sgnal. In 20, H G et al. proposed a seral based reversble comparator n ther work ttled, Desgn of low power Reversble Bnary Comparator [4]. The desgn s based on the reversble gates such as NOT, Feynman (CNOT) and Peres (PG). (c) 2-bt reversble Comparator (d) Reversble mplementaton of output crcut Fg. 9: Desgn of 8-bt reversble Comparator [3] In ths desgn, an-bt bnary comparator s desgned usng two types of blocks, an nput crcut block andn x-bt reversble comparator blocks. The desgn of a 8-bt comparator s shown n the Fg.0a. Frst stage s nput crcut stage whch compares the MSB bts of the two numbers, here A 8, B 8. Second stage s a one-bt comparator cell n whch the result of the frst stage and the nput bts A 7, B 7 s compared and so on. The fnal stage compares the output of the seventh stage and the LSB bts A, B and produces the fnal output of the 8- bt numbers A and B. The nput crcut to bnary comparator usng reversble logc s shown n Fg.0b. The reversble nput crcut s desgned usng one PG, two CNOT and one NOT gates. The nput crcut alone can functon as one-bt comparator and has one garbage output and two constant nputs. Block A shown n Fg. 0d s used n one-bt comparator cell, whch conssts of two NOT, one PG and one CNOT gates. The outputs of block A are C AB and C2 AB. -bt reversble bnary comparator conssts of three PG and four CNOT gates. It has fve nputs vz., P n (AEB), Q n (AGB), R n (ALB), A n - and B n - and three outputs Q n -.e., AGB, P n -.e., AEB and R n -.e., ALB as shown n the Fg. 0c. In 202, Chetan et al. n ther paper, Desgn of Prefx-Based Optmal Reversble Comparator [6], proposedan mproved verson of the tree based archtecture. (a) 8-bt reversble Comparator (b) R-Bcomp Desgn (a) 8-bt reversble Comparator 892

4 G, G, k E, k Gk, E, E, k Ek, (4) where >k >. In the fnal stage the fnal greater and equal sgnals are further used for generaton of fnal lesser sgnal L usng the NOR operaton as gven below L E G (5) N0 N0 N0 (b) Reversble mplementaton of nput crcut Reversble mplementaton of frst stage, black cell and fnal stage s shown n Fg.. (c) -bt reversble Comparator (d) Block A Desgn (a) 8-bt reversble Comparator [6] Fg. 0: Desgn of 8-bt reversble Comparator [4], The basc dea of the desgn s to generate g and e sgnals for each operand bt pars A and B, where, g (greater) ndcates A > B and e (equal) ndcates A = B. For an example, the desgn of an 8-bt comparator s shown n the Fg. a. In the frst stage, the equal and greater than sgnals for th bt are generated as gven by the equatons (2): e g A B A B (2) In the second stage, the black cells generate greater and equal sgnals out of each bt postons are grouped together by groupng logc whch s based on dea presented n [7]. Frst stage groupng s done based on the equatons (3). G, E g e e e g, (3) g and e ndcate the greater and equal sgnals for th operand bts. g and e ndcate the greater and equal sgnals for th operand bts such that > (.e. th bts are sgnfcant than th bts). At the ntermedate stage of groupng the greater and equal sgnal groupng s defned by the equatons (b) Reversble mplementaton of frst stage (c) Realzaton of Black cell used for groupng 893 All Rghts Reserved 207 IJARCET

5 (d) Reversble mplementaton of output crcut Fg. : Desgn of 8-bt reversble Comparator [6] In 204, Hafz Md. Hasan Babu et al. proposed a new seral Bnary comparator n ther paper ttled Approach to desgn a compact reversble low power bnary comparator [0]. To construct the optmzed n-bt comparator, two new reversble gates, namely BJS (Babu-Jamal-Saleheen) gate [Fg. 7] and HLN (Hasan-Laffa-Nazr) gate [Fg. 8] were proposed. The desgn conssts of three man blocks: MSB comparator cell, sngle-bt GE (greater or equal) comparator cell and sngle-bt LT (less than) comparator cell. An MSB comparator cell [Fg. 2b] s used for comparng the n th bt (MSB) of two n-bt numbers and t conssts of only one BJS gate. It takes MSBs of two bnary numbers A n, B n and sets two constant nputs as 0. It produces three outputs based on the bts present at the nput level. ALB (R n ), AGB (Q n ) and AEB (P n ) are the three outputs produced from ths crcut. A sngle-bt GE (greater or equal) comparator cell[fg. 2c] whch conssts of one HLN gate and two Peres Gates has been desgned to generate greater and equal sgnal for the remanng (n-) bts of two numbers wth the prevous comparson result of MSB. It takes (n-) th bts of two bnary numbers A and B and two more nputs P n and Q n from prevous comparson result. Together they work to produce two outputs AEB (P n - ) and AGB (Q n - ) whch ndcates whether the gven numbers A and B are equal or greater than each other. A sngle-bt LT (less than) comparator cell [Fg. 2d] s desgned to determne the less than sgnal. The crcut requres two Feyman Gates. The desgn of an 8 bt comparator s gven n Fg. 2a. (d) Sngle-bt LT (less than) comparator cell Fg. 2: Desgn of 8-bt reversble Comparator [0] IV. COMPARISONS The Reversble bnary comparators descrbed n the above secton are mplemented n 80nm technology usng Cadencetool and syntheszed. The comparators are compared n terms of Number of gates [Table I], Number of garbage outputs [Table II], Quantum Cost [Table III], Delay [Table IV], Power [TABLE V] and Area [Table VI] for 2-bt, 4-bt and 8-bt. Table I: Number of Gates Table II: Number of Garbage Outputs Table III: Quantum Cost (a) 8-bt comparator crcut (b) BJS as MSB comparator crcut Table IV: Delay n ps (c) Sngle-bt GE (greater or equal) comparator cell 894

6 V. CONCLUSION Four exstng comparators are mplemented and syntheszed n 80nm technology usng Cadence tool. From the comparatve analyss, t can be nferred that the reversble bnary comparator crcut proposed by Hafz Md. Hasan Babu et al. n ther work ttled Approach to desgn a compact reversble low power bnary comparator [0] has been constructed wth the optmum number of gates, garbage outputs and quantum cost. It also shows consderable mprovement n power and area consumed. The only parameter of ths that do not outperforms the others s the delay but there s not much dfference. As [3], [6] both are tree-based desgn, they requre O(log 2 n) delay, whereas [0], [4], requres O(n) delay. The comparson of all parameters for an n-bt comparator s shown n the table VII. Consderng the optmzaton of all the parameters, the crcut outperforms the exstng ones n terms of scalablty and effcency. Snce comparson of two numbers s useful n manyapplcatons, ths comparatve study wll help the researchers n choosng a sutable comparator. From analyss of the desgn n the paper by Chetan et al. [6], t can be observed that more number of gates are used to realze the black cell. If the number of gates n the black cell s reduced, t can provde a sgnfcant decrease n the power and area consumed. Also snce t has a prefx based tree archtecture, delay wll also be less. So a more effcent bnary reversble comparator can be developed by desgnng a new reversble gate that wll replace the gates used n black cell. Table V: Total Power n nw et al [6] Table VI: Area n cm 2 et al [6] Parameters Table VII: Comparson of parameters for n-bt Number of 3n 9n 7n-4 4n-2 Gates Number of Garbage 4n-3 6n-6 5n-4 5n-4 Outputs Quantum 3n-5 8n-9 6n-0 4n Cost Delay 256.5n log 2n 847.5n log Power 23.0 n n n n n Area 90n-4 333n n-99 04n-20 REFERENCES [] R. Landauer, Irreversblty and heat generaton n the computng process, IBM ournal of research and development, vol. 5, no. 3, pp. 83 9, 96. [2] C. H. Bennett, Logcal reversblty of computaton, IBM ournal of Research and Development, vol. 7, no. 6, pp , 973. [3] M. Perkowsk, L. Jozwak, P. Kerntopf, A. Mshchenko, A. Al-Rabad, A. Coppola, A. Buller, X. Song, S. Yanushkevch, V. P. Shmerko et al., A general decomposton for reversble logc, 200. [4] M. Perkowsk and P. Kerntopf, Reversble logc. nvted tutoral, Proc. EURO-MICRO, 200. [5] P. Kerntopf, M. Perkowsk, M. H. Khan et al., On unversalty of general reversble multple-valued logc gates, n Multple-Valued Logc, Proceedngs. 34th Internatonal Symposum on. IEEE, pp , [6] R. P. Feynman, Quantum mechancal computers, Foundatons of Physcs, vol. 6, no. 6, p. 986, 985. [7] T. Toffol, Reversble computng. Sprnger, 980. [8] A. Peres, Reversble logc and quantum computers, Physcal revew A, vol. 32, no. 6, p. 3266, 985. [9] H. and N. Ranganathan, Desgn of effcent reversble bnary subtractors based on a new reversble gate, n VLSI, ISVLSI 09. IEEE Computer Socety Annual Symposum on. IEEE, pp , [0] H. MdHasanBabu, N. Saleheen, L. Jamal, S. M. Sarwar, and T. Sasao, Approach to desgn a compact reversble low power bnary comparator, Computers & Dgtal Technques, IET, vol. 8, no. 3, pp , 204. [] M. A. Nelson and I. L. Chuang, Quantum computaton and quantum nformaton, [2] A. K. Bswas, M. M. Hasan, A. R. Chowdhury, and H. M. H. Babu, Effcent approaches for desgnng reversble bnary coded decmal adders, Mcroelectroncs ournal, vol. 39, no. 2, pp , [3] H., N. Ranganathan, and R. Ferrera, Desgn of a comparator tree based on reversble logc, n Nanotechnology (IEEE-NANO), 200 0th IEEE Conference on. IEEE, pp. 3 6, 200. [4] H., V. Hegde, K. Raa, and K. Muraldhara, Desgn of low power reversble bnary comparator, Proc. Engneerng (ScenceDrect), 20., Desgn of effcent reversble bnary comparator, Proceda Engneerng, vol. 30, pp , 202. [6] C., P. S. Phaneendra, V. Sreehar, S. E. Ahmed, N. M. Muthukrshnan, and M. B. Srnvas, Desgn of prefx-based optmal reversble comparator, n VLSI (ISVLSI), 202 IEEE Computer Socety Annual Symposum on. IEEE, pp , 202. [7] S. A. Cuccaro, T. G. Draper, S. A. Kutn, and D. P. Moulton, A new quantum rpple-carry addton crcut, arxv preprnt quantph/04084, All Rghts Reserved 207 IJARCET

7 Harth M receved the B.Tech. Degree n Electroncs and Communcaton Engneerng from Government Engneerng College, Idukk, Kerala, Inda. He s currently pursung M.E. n VLSI Desgn from Government College of Technology, Combatore, Inda. Hs research focuses Reversble Logc synthesze and beyond CMOS technologes. C. Vasanthanayak receved the B.E. degree n Electroncs and Communcaton Engneerng and M.E. degree n Computer Scence, from Government College of Engneerng, Trunelvel, Inda, n 987 and 997 respectvely. She receved the Ph.D. degree n the Informaton and Communcaton Engneerng. Snce 988, she has been wth the Government College of Technology, Combatore, Inda