Estimating Delays. Gate Delay Model. Gate Delay. Effort Delay. Computing Logical Effort. Logical Effort

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1 Estmatng Delas Would be nce to have a back of the envelope method for szng gates for speed Logcal Effort ook b Sutherland, Sproull, Harrs Chapter s on our web page Gate Dela Model Frst, normalze a model of dela to dmensonless unts to solate fabrcaton effects d abs = d τ τ s the dela of a mnmum nverter drvng another mnmum nverter wth no parastcs In a 0.6u process, ths s appro 0ps Now we can thnk about dela n terms of d and scale t to whatever process we re buldng the crcut n Gate Dela Dela of a gate d has two components fed part called parastc dela p part proportonal to the load on the output called the effort dela or stage effort f Total dela s measured n unts of τ, and s sum of these delas d = f + p Effort Dela The effort dela (due to load) can be further broken down nto two terms f = g * h g = logcal effort whch captures propertes of the gate s structure h = electrcal effort whch captures propertes of load and transstor szes h = C out /C n C out s capactance that loads the output C n s capactance presented at the nput So, d = gh + p Logcal Effort Logcal effort normalzes the output drve capablt of a gate to match a unt nverter How much more nput capactance does a gate need to present to offer the same drve as n nverter? a b a g = g = /3 a b g = 5/3 Computng Logcal Effort DEF: Logcal effort s the rato of the nput capactance of a gate to the nput capactance of an nverter delverng the same output current. Measure from dela vs. fanout plots Or estmate b countng transstor wdths Y Y Y (a ) (b ) (c) C n = 3 g = 3/3 C n = g = /3 C n = 5 g = 5/3

2 Logcal Effort of Other Gates Logcal effort of common gates assumng that P/N sze rato s Number of nputs Gate Tpe 3 5 n Inverter NND /3 5/3 6/3 7/3 (n+)/3 NOR 5/3 7/3 9/3 /3 (n+)/3 MUX XOR 3 Electrcal Effort Value of logcal effort g s ndependent of transstor sze It s related to the ratos and the topolog Electrcal effort h captures the drve capablt of the transstors va szng Electrcal effort h = C out /C n Note that as transstor szes for a gate ncrease, h decreases because C n goes up Parastc Dela Plots of Gate Dela Parastc dela p s caused b the nternal capactance of the gate It s constant and ndependent of transstor sze s ou ncrease the transstor sze, ou also ncrease the cap of the gate/source/dran areas whch keeps t constant For our purposes, normalze p nv to N-nput NND = n*p nv N-nput NOR = n*p nv N-wa mu = n*p nv XOR = * p nv Two-nput NND : g =, p = Effort dela Parastc dela 3 5 Electrcal effort: h Inverter: g =, p = Dela Estmaton Dela Estmaton Remember, τ n Our process ~ 0ps Remember, τ n Our process ~ 0ps ~00ps ~00ps τ n 0nm = ~ ps FO Inverter dela = 60ps FO NND dela = 7ps ~0ps ~0ps

3 Eample: Rng Oscllator Estmate the frequenc of an N-stage rng oscllator Eample: Rng Oscllator Estmate the frequenc of an N-stage rng oscllator Logcal Effort: g = Electrcal Effort: h = Parastc Dela: p = Stage Dela: d = Perod of osc = Logcal Effort: g = Electrcal Effort: h = Parastc Dela: p = Stage Dela: d = so d abs = 0ps Perod: *N*d abs =.96ns, Freq = ~00MHz Eample: FO Inverter Estmate the dela of a fanout-of- (FO) nverter d Eample: FO Inverter Estmate the dela of a fanout-of- (FO) nverter d Logcal Effort: g = Electrcal Effort: h = Parastc Dela: p = Stage Dela: d = Logcal Effort: g = Electrcal Effort: h = Parastc Dela: p = Stage Dela: d = gh + p = 5 The FO dela s about 00 ps n 0.6 μm process 60 ps n a 0 nm process f/3 ns n an f μm process Dela Estmaton Mult Stage Dela If Cn =, Cout = 0, thus h = 0 g = 9/3 = 3 d = gh + p = 3*0 + * = 3 (360 ps) 3

4 Off-Path Load Summar multstage networks Logcal effort generalzes to multstage networks G = g Path Logcal Effort Path Electrcal Effort C H = out path C n path Ctotal Cuseful Path Effort F = f = gh Can we wrte F = GH? ranchng Effort Remember branchng effort ccounts for branchng between stages n path Con path + Coff path b = C = b on path Note: h = H Multstage Delas Path Effort Dela Path Parastc Dela Path Dela D F = f P = p D = d = D + P F Now we compute the path effort F = GH Desgnng Fast Crcuts D = d = D + P Dela s smallest when each stage bears same effort ˆ N f = gh = F F Mnmzng Path Dela Thus mnmum dela of N stage path s D = NF + P Ths s a ke result of logcal effort Fnd fastest possble dela Doesn t requre calculatng gate szes N

5 Choosng Transstor Szes Eample 0 mnd=n*f /N + P Eample, contnued Transstor Szes for Eample nother Eample, Larger Load C Load Eample Cont. 5

6 Eample.6 from Chap Eample.6 Contnued 0 Eample: 3-stage path Eample: 3-stage path Select gate szes and for least dela from to Logcal Effort G = Electrcal Effort H = ranchng Effort = Path Effort F = est Stage Effort Parastc Dela ˆf = P = Dela D = Eample: 3-stage path Logcal Effort G = (/3)*(5/3)*(5/3) = 00/7 Electrcal Effort H = / ranchng Effort = 3 * = 6 Path Effort F = GH = 5 est Stage Effort Parastc Dela 3 f ˆ = F = 5 P = = 7 Dela D = 3*5 + 7 = =. FO Eample: 3-stage path Work backward for szes = = 6

7 Eample: 3-stage path Eample.7 from Chap Work backward for szes = * (5/3) / 5 = 5 = (5*) * (5/3) / 5 = 0 P: N: P: N: 6 P: N: 3 Note: Don t care about parastcs for gate szng, onl f ou want to know absolute dela Msc. Comments Note that ou never sze the frst gate Ths gate s assumed to be fed If ou were allowed to sze t, the algorthm would tr to make t as large as possble Ths s an estmaton algorthm uthors clam that szng a gate b.5 too bg or small stll results n a path dela wthn 5% of mnmum Senstvt nalss How senstve s dela to usng eactl the best number of stages? D(N) /D(N) (ρ=6) N / N.6 (ρ =.). < ρ < 6 gves dela wthn 5% of optmal We can be slopp! I lke ρ = Evaluatng Dfferent Optons Opton # 7

8 Opton # How man stages? Consder three alternatves for drvng a load 5 tmes the nput capactance One nverter Three nverters n seres Fve nverters n seres The all do the job, but whch one s fastest? How man stages? In all cases: G =, =, and H = 5 Path dela s N(5) /N + N P nv N =, D = 6 unts N = 3, D =. unts N = 5, D =.5 unts Snce N=3 s best, each stage wll bear an effort of (5) /3 =.9 So, each stage s ~3 larger than the last In general, the best stage effort s between 3 and (not e as often stated) The e value doesn t use parastcs Choosng the est # of Stages You can solve the dela equatons to determne the number of stages N that wll acheve the mnmum dela ppromate b Log F Path Effort F est N Mn Dela D Stage effort f Eample Strng of nverters drvng an off-chp load Pad cap and load = 0pf Equvalent to 0,000 mcrons of gate cap ssume frst nverter n chan has 7.u of nput cap How man stages n nv chan? H = 0,000/7. = 777 From the table, 6 stages s best Stage effort = f = (777) /6 = 3.75 Path dela D = 6* *Pnv =.5 D =.ns f τ = 0ps Summar Compute path effort F = GH Use table, or estmate N = log F to decde on number of stages Estmate mnmum possble dela D = NF /N + Σp dd or remove stages n our logc to get close to N Compute effort at each stage f = F /N Startng at output, work backwards to compute transstor szes C n = (g /f)c out

9 Lmts of Logcal Effort Chcken and egg problem Need path to compute G ut don t know number of stages wthout G Smplstc dela model Neglects nput rse tme effects Interconnect Iteraton requred n desgns wth wre Mamum speed onl Not mnmum area/power for constraned dela Summar Logcal effort s useful for thnkng of dela n crcuts Numerc logcal effort characterzes gates NNDs are faster than NORs n CMOS Paths are fastest when effort delas are ~ Path dela s weakl senstve to stages, szes ut usng fewer stages doesn t mean faster paths Dela of path s about log F FO nverter delas Inverters and NND best for drvng large caps Provdes language for dscussng fast crcuts ut requres practce to master 9

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