Lecture 7: Multistage Logic Networks. Best Number of Stages

Transcription

1 Lecture 7: Multstage Logc Networks Multstage Logc Networks (cont. from Lec 06) Examples Readng: Ch. Best Number of Stages How many stages should a path use? Mnmzng number of stages s not always fastest Example: drve 6-bt datapath wth unt nverter Intal Drver D = NF /N + P = N(6) /N + N F=GBH B= H=6 G= Datapath Load N: f: D: Fastest

2 Best Stage Effort Dervaton Consder addng nverters to end of path How many gve least delay? N n = ( ) D= NF + p + N n p D N N N = F ln F + F + pnv = 0 N Defne best stage effort ρ = F N p + ρ lnρ = 0 nv ( ) Logc Block: n Stages Path Effort F N - n Ex tra Inv erters Neglectng parastcs (p nv = 0), we fnd ρ = 2.78 (e) For p nv =, solve numercally for ρ = 3.59 nv No closed-form soluton Senstvty Analyss How senstve s delay to usng exactly the best number of stages?.6.5 D(N) /D(N) (ρ=6) (ρ =2.) < ρ < 6 gves delay wthn 5% of optmal We can be sloppy! I lke ρ = N / N 2

3 Example: extractng logcal effort from datasheets INVX Determne p, g and τ for INVX from datasheet Unt nverter capactance s 3.6fF Parastc or ntrnsc delay s ( )/2=20ps Slope of delay vs. load capactance s the average of rsng and fallng K load values ( )/2 ns/pf Normalzed Delay: d Recall d abs = (gh+p) τ nput NAND Electrcal Ef f ort: h = C out / C n Inverter g = /3 p = 2 d = (/3)h + 2 g = p = d = h + Ef f ort Delay: f Parastc Delay: p t pd = 20ps + (3.6fF/gate)(h gates)[( )/2 ns/pf] = (20ps + 2.h) ps = tau (20ps/tau + (2./tau)h) p nv = 20ps/2.ps =.6 g==2./tau à tau=2. d=(gh+p)=(h+.6) 3

4 NAND2 Determne p, g and τ for NAND2X from datasheet Unt NAND2X capactance s.2ff Parastc or ntrnsc delay s ( )/2 Slope of delay vs. load capactance s the average of rsng and fallng K load values ( )/2 ns/pf Normalzed Delay: d Recall d abs = (gh+p) τ nput NAND Electrcal Ef f ort: h = C out / C n Inverter g = /3 p = 2 d = (/3)h + 2 g = p = d = h + Ef f ort Delay: f Parastc Delay: p t pd = ( )/2 + (.2fF/gate)(h gates)[( )/2 ns/pf] = (25.ps + 5.5h) ps p nv = 25.ps/2.ps = 2.05 g=5.5/tau=.25=5/ Example Ben Btdddle s the memory desgner for the Motorol 68W86, an embedded automotve processor. Help Ben desgn the decoder for a regster fle. A[3:0] A[3:0] 32 bts Decoder specfcatons: 6 word regster fle Each word s 32 bts wde Each bt presents load of 3 unt-szed transstors True and complementary address nputs A[3:0] Each nput may drve 0 unt-szed transstors Ben needs to decde: How many stages to use? How large should each gate be? How fast can decoder operate? :6 Decoder 6 Regster Fle 6 words

5 Intal Dlema You need the path effort to calculate the optmum number of stages N = log ρ F You need the path logcal effort to calculate the path effort F = f = gh = GBH From ρ=f /N Stage effort ρ=3- Wthout knowng the number of stages you cannot draw a path, determne the logcal effort of the path and fnd the path effort G= g Number of Stages Decoder effort s manly electrcal and branchng Electrcal Effort: H = (32*3) / 0 = 9.6 Branchng Effort: B = 8 If we neglect logcal effort (assume G = ) Path Effort: F = GBH = 76.8 Number of Stages: N = log F = 3. Try a 3-stage decoder desgn Each address s used to compute Half of the 6 word lnes; ts Complement Is used for the other half

6 Delay Logcal Effort: G = * 6/3 * = 2 Path Effort: F = GBH = 2*8*9.6=5 Stage Effort: /3 f ˆ = F = 5.36 Path Delay: D= 3fˆ = 22. A[3] A[3] A[2] A[2] A[] A[] A[0] A[0] y z word[0] 96 unts of wordlne capactance y z word[5] Gate Szes & Delay Gate szes: z = 96*/5.36 = 8 y = 8*2/5.36 = 6.7 fˆ = gh = g C C out n gc Cn = fˆ out A[3] A[3] A[2] A[2] A[] A[] A[0] A[0] y z word[0] 96 unts of wordlne capactance y z word[5] 6

7 Comparson Compare many alternatves wth a spreadsheet Desgn N G P D NAND-INV NAND2-NOR2 2 20/9 30. INV-NAND-INV NAND-INV-INV-INV NAND2-NOR2-INV-INV 20/ NAND2-INV-NAND2-INV 6/ INV-NAND2-INV-NAND2-INV 5 6/ NAND2-INV-NAND2-INV-INV-INV 6 6/ Revew of Defntons Term Stage Path number of stages logcal effort electrcal effort branchng effort effort effort delay parastc delay delay g h = b = Cout Cn Con-path + Coff-path Con-path f = gh f p d = f + p N G= g H = Cout-path Cn-path B= b F = GBH D F = f P= p D = d = D + P F 7

8 Method of Logcal Effort ) Compute path effort 2) Estmate best number of stages 3) Sketch path wth N stages ) Estmate least delay 5) Determne best stage effort F = GBH N = log F N D= NF + P ˆ N f = F 6) Fnd gate szes C n = gc fˆ out Lmts of Logcal Effort Chcken and egg problem Need path to compute G But don t know number of stages wthout G Smplstc delay model Neglects nput rse tme effects Interconnect Iteraton requred n desgns wth wre Maxmum speed only Not mnmum area/power for constraned delay 8

9 Summary Logcal effort s useful for thnkng of delay n crcuts Numerc logcal effort characterzes gates NANDs are faster than NORs n CMOS Paths are fastest when effort delays are ~ Path delay s weakly senstve to stages, szes But usng fewer stages doesn t mean faster paths Delay of path s about log F FO nverter delays (NxFO delay) Inverters and NAND2 best for drvng large caps 9