VLSI Arithmetic Adders & Multipliers

Transcription

1 VLSI Arthmet Adders & Multlers Prof. Vojn G. Oklobdzja Unversty of Calforna htt:// Prof. V.G. Oklobdzja VLSI Arthmet

2 Addton of Bnary Numbers Full Adder. The full adder s the fundamental buldn blok of most arthmet ruts: a b C out Full Adder C n The sum and arry oututs are desrbed as: s a b a b a b ab a b ab ab ab a b Prof. V.G. Oklobdzja VLSI Arthmet s a b

3 Addton of Bnary Numbers Inuts Oututs a b s Proaate Generate Proaate Generate Prof. V.G. Oklobdzja VLSI Arthmet 3

4 Full-Adder Imlementaton Full Adder oeratons s defned by equatons: s a b a b a b a b a b a b a b a b Carry-Proaate: and Carry-Generate a b a b a b out One-bt adder ould be mlemented as shown n Prof. V.G. Oklobdzja VLSI Arthmet s 4

5 Hh-Seed Addton a b a b a b 0 out s n One-bt adder ould be mlemented more effently beause MUX s faster s s Prof. V.G. Oklobdzja VLSI Arthmet 5

6 The Rle-Carry Adder Prof. V.G. Oklobdzja VLSI Arthmet 6

7 The Rle-Carry Adder A 0 B 0 A B A B A 3 B 3 C,0 C o,0 C o, C o, FA FA FA FA ( C, ) C o,3 S 0 S S S 3 Worst ase delay lnear wth the number of bts t d O(N) t adder ( N )t arry t sum From Rabaey Goal: Make the fastest ossble arry ath rut Prof. V.G. Oklobdzja VLSI Arthmet 7

8 Inverson Proerty A B A B C FA C o C FA C o S S From Rabaey Prof. V.G. Oklobdzja VLSI Arthmet 8

9 Mnmze Crtal Path by Redun Invertn Staes Even Cell Odd Cell A 0 B 0 A B A B A 3 B 3 C,0 C o,0 C o, C o, C o,3 FA FA FA FA S 0 S S S 3 Exlot Inverson Proerty From Rabaey Note: need dfferent tyes of ells Prof. V.G. Oklobdzja VLSI Arthmet 9

10 Manhester Carry-Chan Realzaton of the Carry Path Smle and very oular sheme for mlementaton of arry snal ath V dd V dd V dd V dd V dd V dd V dd V dd Carry out Generate deve Carry n Proaate deve Predshare & kll deve Prof. V.G. Oklobdzja VLSI Arthmet 0

11 Manhester Carry Chan Imlement P wth ass-transstors Imlement G wth ull-u, kll (delete) wth ull-down Use dynam lo to redue the omlexty and seed u V DD φ P 0 P P P 3 P 4 C,0 G 0 G G G 3 G 4 φ Klburn, et al, IEE Pro, 959. Prof. V.G. Oklobdzja VLSI Arthmet

12 Rle Carry Adder Carry-Chan of an RCA mlemented usn multlexer from the standard ell lbrary: a b a b a b Crtal Path out n Oklobdzja, ISCAS 88 s s s Prof. V.G. Oklobdzja VLSI Arthmet

13 Carry-Lookahead Adder (Wenberer and Smth) Wenberer and J. L. Smth, A Lo for Hh-Seed Addton, Natonal Bureau of Standards, Cr. 59,.3-, 958. Prof. V.G. Oklobdzja VLSI Arthmet 3

14 Prof. V.G. Oklobdzja VLSI Arthmet 4 Carry-Lookahead Adder (Wenberer and Smth) ) ( a b a b a b 3 ) (

15 Carry-Lookahead Adder G j Pj 3 One ate delay to alulate, One to alulate P and two for G Three ate delays C 4(j) a 3 b 3 C 4j3 a b P, G Grou C 4j a b To alulate C 4(j) G 4 ( j ) G P j P j 4 j Comare that to 8 n RCA! Prof. V.G. Oklobdzja VLSI Arthmet 5 j a b Cn C 4j C j

16 Carry-Lookahead Adder (Wenberer and Smth) * G j G P 3G P 3P G P 3P P 3 * P j P 3P P P G G j3 P j3 G j P j G j P j G j P j C 4(j) C 4j G* P* 4 ( j ) G * k P * k 4 j C 4j3 C 4j C 4j Addtonal two ate delays C 6 wll take a total of 5 vs. 3 for RCA! Prof. V.G. Oklobdzja VLSI Arthmet 6

17 3-bt Carry Lookahead Adder a ndvdual adders eneratn:,, and sum S b C 8 C 4 C 0 C C 8 C 4 C n C 6 C out C n Carry-lookahead suer- bloks of 4-bts bloks eneratn: G*, P*, and C n for the 4-bt bloks C out C n Grou rodun fnal arry C out and C 6 Carry-lookahead bloks of 4-bts eneratn: G, P, and C n for the adders Crtal ath delay (for,)x (for G,P)3x (for Cn)XOR- (for Sum) ax. of delay Prof. V.G. Oklobdzja VLSI Arthmet 7

18 Carry-Lookahead Adder (Wenberer and Smth: ornal dervaton ) Prof. V.G. Oklobdzja VLSI Arthmet 8

19 Carry-Lookahead Adder (Wenberer and Smth: ornal dervaton ) Prof. V.G. Oklobdzja VLSI Arthmet 9

20 Carry-Lookahead Adder (Wenberer and Smth) lease note the smlarty wth Parallel-Prefx Adders! Prof. V.G. Oklobdzja VLSI Arthmet 0

21 Carry-Lookahead Adder (Wenberer and Smth) lease note the smlarty wth Parallel-Prefx Adders! Prof. V.G. Oklobdzja VLSI Arthmet