Laboratoire de l Informatique du Parallélisme

Transcription

1 Laboratoire de l Informatique du Parallélisme Ecole Normale Suérieure de Lyon Unité de recherche associée au CNRS n 1398 Asynchronous Sub-Logarithmic Adders J.M. Muller, A. Tisserand and J.M. Vincent May 16, 1997 Research Reort N o RR Ecole Normale Suérieure de Lyon 46 Allée d Italie, Lyon Cedex 7, France Téléhone : (+33) () Télécoieur : (+33) () Adresse électronique : li@li.ens lyon.fr

2 Asynchronous Sub-Logarithmic Adders J.M. Muller, A. Tisserand and J.M. Vincent May 16, 1997 Abstract Fast arithmetic oerators have always been an imortant toic in comuter design. There are two kinds of arithmetic oerators: xed-time and variable-time ones. While xed-time arithmetic oerators have been widely studied, variable-time oerators seem to be more and more interesting for low-ower design and very high erformance comuting. Self-timed arithmetic oerators are able to deliver their result in an average comutation time less than the worst case time. We resent an architecture, which is a variant of the carry select adder, for the addition of n-bit numbers with a O( log 2 n) average comutation time. Keywords: Comuter arithmetic, asynchronous oerators, addition Resume La concetion d'oerateurs arithmetiques raides est un enjeu imortant dans la realisation d'un ordinateur. Il existe deux tyes d'oerateurs arithmetiques : ceux a delai xe et ceux a delai variable. Tandis que les oerateurs a delai xe ont ete beaucou etudies dans le asse, les oerateurs a delai variable semblent tres rometteurs our les realisations basse consommation et our le calcul haute erformance. Les oerateurs auto-sequences delivrent leur resultat dans un tems moyen beaucou lus etit que le tems dans le ire cas. Nous resentons ici une nouvelle architecture, basee sur l'additionneur a selection de la retenue, our laquelle le tems moyen d'une addition de deux nombres de n chires est en O( log 2 n). Mots-cles: Arithmetique des ordinateurs, oerateurs asynchrones, addition

3 Asynchronous Sub-Logarithmic Adders Jean-Michel Muller and Arnaud Tisserand CNRS, Laboratoire LIP ENS Lyon. 46 Allee d'italie LYON Cedex 7, FRANCE Jean-Marc Vincent Laboratoire LMC - IMAG. 1 rue des Mathematiques, BP GRENOBLE Cedex 9, FRANCE Jean-Marc.Vincent@imag.fr Abstract Fast arithmetic oerators have always been an imortant toic in comuter design. There are two kinds of arithmetic oerators: xed-time and variabletime ones. While xed-time arithmetic oerators have been widely studied, variable-time oerators seem to be more and more interesting for low-ower design and very high erformance comuting. Self-timed arithmetic oerators are able to deliver their result in an average comutation time less than the worst case time. We resent an architecture, which is a variant of the carry select adder, for the addition of n-bit numbers with a O( log 2 n) average comutation time. 1 Introduction Fast arithmetic oerators have always been a main goal in comuter design. There are two kinds of arithmetic oerators: xed-time and variable-time ones. Fixed-time oerators for the basic arithmetic oerations (addition, multilication, division and square-root) have been widely studied ([Kor93], [Omo94]). Variable-time oerators are able to erform very fast comutations whose based on algorithms for which the average comutation time is signicantly dierent from the worst case comutation time. In most arithmetic oerations the average comutation time is less than the worst case comutation time. Self-timed oerators can be used in low-ower alications such as mobile systems ([BBK + 94]). In asynchronous oerators there is no exensive global clock signal which roduces an amount of current at each clock edge. Another use of self-timed oerators is the design of reliable circuits and variable bandwidth systems. Indeed, self-timed oerators are able to achieve their comutations in a large interval of electrical arameters such as suly voltage ([RRPB96]). The design of self-timed oerators is dierent from the design of synchronous oerators both from the theoretical and imlementation oints of view. Due to the asynchronous imlementation, only the real change of signal state must be detected ([Hau95]). But the imlementation is not the only dierence between synchronous and asynchronous oerator design: there may also be algorithmic dierences. One reason is that the minimization of the average comutation time and the minimization of the worst case comutation time do not lead to the same results. An imortant characteristic of asynchronous oerators is the need to detect of the com-

4 letion of the comutation. In order to send its result to the next oerators, an oerator must in general rovide a comletion detection signal. There are a few excetions to this rule: alications for which having from time to time a slightly erroneous result is accetable, rovided that the robability of error is small enough (secic alications in signal and image rocessing, some data comression algorithms, some neural networks algorithms... ). In this aer we deal with fast asynchronous arithmetic algorithms and architectures for the addition, and their hardware imlementation. We use the robability distribution of the comutation time as a tool to erform analysis and comarisons of dierent addition algorithms. In the rst art we recall the average comutation time and we give some informations about the robability distribution of the comutation time for the simlest adder: the rile carry adder. The average comutation time of the rile carry adder have been given in many aers (see [BGN47] for examle). But the average comutation time does not suce to chose between several algorithms. Indeed, we need the robability distribution of the comutation time in order to design oerators for very fast alications allowing a very small error, rovided that the robability of this error is small enough. In the second art we resent an asynchronous adder, its architecture and its analysis. This adder, based on a modication of the carry select adder, has a sub-logarithmic average comutation time, more recisely O( log 2 n) (n-bit oerands). We also analyze dierent comletion schemes with a small hardware overhead for this adder. 2 The Rile Carry Adder In this aer we deal with n bit integers reresented in the usual binary system (the results for the 2's comlement notation are obviously similar): A = (a n?1a n?2 : : : a 1 a ) = n?1 X i= a i 2 i : Brent ([Bre7]) and Winograd([Win65]) have shown that the time comlexity of the binary addition in the synchronous case is O(log 2 n) rovided that we use gates with bounded fan-in and fan-out. The rile carry adder () is the direct transcrition of the aer-and-encil algorithm (see gure 1). Each cell is a full-adder (FA) that comutes the sum b n?1 a n?1 b n?2 a n?2 b 1 a 1 b a c n c n?1 c n?2 c 2 c 1 c F A n?1 F A n?2 F A 1 F A s n?1 s n?2 s 1 s Figure 1: A n-bit Rile Carry Adder bit s i and the carry out bit c i+1 from the two oerands inut bits (a i ; b i ) and the carry-in bit c i using the well-known formul: s i = a i b i c i c i+1 = (a i ^ b i ) _ (a i ^ c i ) _ (b i ^ c i ): The average comutation time (ACT) of the rile carry adder is O(log 2 n) (see gure 2). This result was shown by Burks, Goldstine and Von Neumann in [BGN47].

5 1 8 7 Average Comutation Oerand Size (bits) Figure 2: The Average Comutation Time of several Rile Carry Adders (4 n 128) The average comutation time (ACT) is not the only interesting characteristics of an asynchronous arithmetic oerator. The comutation time robability distribution (CTPD) is a good information to comare oerators. We resent in gure 3 the comutation time distribution for s of 32 and 128 binary digits. The time unit is the delay of a full-adder cell. We have erformed a comlete analysis of the robabilistic characteristic of the rile carry adder using generating functions. The gures 3 and 2 are deduced from this analysis digit 128-digit E-2 Probabilty.15 1E-2 Probabilty.1 1E-3.1 1E-3.5 1E-6.5 1E Figure 3: Comutation Time Probability Distribution for 32 and 128-bit Rile Carry Adders We can see on the CTPD curves (gure 3) that most cases time a n-bit addition is comleted much before the time n (where is the time of one full adder cell). From the robabilistic analysis of the rile carry adder we can calculate the robability that an n-bit addition is not nished at time t for any t in the interval [; n ]. For examle, with a 128-bit adder the robability that the addition is not comlete at the time 32 is 2:28 1?8. Figure 4 resents the robability failure for rile carry adders with 16, 32, 64 and 128 bits. This can be eciently used in some alications for which having a slightly erroneous result with a low robability is accetable (secic alications in signal and image rocessing, no-exact data comression algorithms, some neural networks algorithms... ).

6 1e bits 32 bits 64 bits 128 bits 1e-1 Failure Probability 1e-2 1e Figure 4: Failure robability as a function of the stoing time for a n bits rile carry adder 3 The Sub-Logarithmic Carry Select Adder In this section we resent an adder called sub-logarithmic carry select adder () which average comutation time is O( log 2 n). This adder is based on a modication of the well-known carry select adder. The sub-logarithmic carry select adder is based on the following rinciles: a carry anticiation strategy, an asynchronous carry roagation scheme. 3.1 The Sub-Logarithmic Carry Select Adder Architecture The whole architecture of the sub-logarithmic carry select adder is resented gure 5 and the basic cell is resented gure 6. The basic cell is made u with two -bit A n B n A n B n?1?1 A 2 B 2 A 1 B 1 S n S n?1 S 2 S 1 Figure 5: The Sub-Logarithmic Carry Select Adder rile carry adders. The two inut n-bit numbers (A; B) are slit into small blocks of bits (A = A n= : : : A 2 A 1 and A k = a (k?1)a (k?1)+1 : : : a (k?1)+?1; 8k 2 [1:: n], the same for B and S). Each basic cell of the receives two inut blocks (A k ; B k ) and roduces one block of the sum S k. The carry anticiation scheme is the same as in carry select adders. One adder is fed with an inut carry equal to while the second adder is fed with an inut carry equal to 1. The carry-in block signal c in connects the outut corresonding to the sum of the whole block with the sum outut of the adder which had the good anticiated inut carry. In the following we assume that n is an integer. In ractice, if n is not an integer we can adjust the size of the last block with a block size smaller than. We will see in the next section what value is convenient for. In n-bit conditional sum adders, 3 adders of size n=2 are used. The rst comutes the sum of the n=2 least signicant digits while the two other adders comute the

7 A k B k -digit 1 d 1 one bit wire wires c out 1 S k c in Figure 6: The Sub-Logarithmic Carry Select Adder Cell sum of the half most signicant digits, one with an inut carry equal to and the second with an inut carry equal to 1. These 3 sums can be erformed in a fully arallel scheme. When the rst adder has a result it is ossible to determine which result of the two other adders should be used. This strategy is alied in a recursive way, then conditional sum adders have a comutation time equal to O(log 2 n). 3.2 Evaluation In this subsection we give the analysis of the sub-logarithmic carry select adder that shows the average and the worst case comutation time. We resent the comutation time robability distribution of the using simulations Analysis During a rst \ste" all the basic cells of the comute their results in arallel. After this comutation, there is a roagation of the carry c out of each block. There is an imortant overlaing of these two \stes" due to the asynchronous scheme. Each block has an average comutation time equal to the average comutation time of a -bit adder lus a constant time due to the multilexer erforming the choice between the oututs of the two adders (in this analysis we neglect this constant time). As we have shown in section 2, the average comutation time for a n-bit rile carry adder is O(log 2 n). In order to make sure that in all blocks the comutation time is less than O(log 2 n) we must have < log 2 n. In the following we use a time unit equal to the delay of one full-adder cell. The worst case comutation time is for one basic cell. The average time needed for the comletion of all the basic cells is slightly less than. Indeed, for one basic cell the average comutation time is O(log 2 ), but for all the n basic cells the robability that there is at least a roagation all over one cell is high since < log 2 n. Hence, the average comutation time for the comletion of all basic cells is bounded by k 1, with k 1 slightly less than 1. The worst case comutation time for the roagation of the block carries is the time needed by the signal to ass through n multilexers. Let k 2 be the time necessary to ass through the multilexer which erforms the choice between the inut block carry c in and the anticiated carry in each basic cell (with the time unit equal to the delay of one full-adder cell, k 2 is much less than 1). Then the worst case comutation time for the is:

8 + k 2 n : We have seen above that the average comutation time for the comletion of all basic cells can be uer bounded by k 1 with k 1 slightly less than 1. The average comutation time for the roagation of the block carries is log 2 n, because it is equal to the average carry length in the whole adder (that is log 2 n) divided by the size of the block (that is ). The average comutation time of the sub-logarithmic carry select adder T is: T f(n) = k 1 + log 2 k 2 n : q k2 The function f(n) is minimal for = log k1 2 n. For this value of the average comutation time of the is 2 k 1 k 2 log 2 n. Then we have the comlexity of the sub-logarithmic carry select adder: T = O( log 2 n): The area used by a n-bit sub-logarithmic carry select adder is more than two times the area of a rile carry adder. In ractice the best choice for the value of deends on the value of the technological constants k 1 and k 2. In [GO96], De Gloria and Olivieri have built a fast asynchronous adder based on statistical carry lookahead adders (SCLA). This adder has an average comutation time less than O(log 2 n) but our simulation results (see section 3.2.2) shows that our adder is faster. The areas needed by both adders are close together. The oint that makes the simler to imlement is the fan-in, all the gates in the have a bounded fan-in while in the SCLA some gates have a non-bounded fan-in Simulations In this art of the aer we erform some comarisons between our sub-logarithmic carry select adder and the rile carry adder using simulations. Figure 7 resent comarisons between the average comutation time of the and the for several block sizes. The curves are reresented with lain lines and curves with dotted lines. Our simulations are such that the condence interval of the results have a length smaller than 1?6. The following table gives some values for the average comutation time of the sublogarithmic carry select adder and for the rile carry adder. In this table we can see that with blocks of size 2 is very ecient for small adders and a with blocks of size 3 is a good choice for large adders. The time unit used in these simulations is the delay of one full-adder cell. adder sizes block sizes

9 Average Comutation Average Comutation Oerand Size (bits) Block size Oerand Size (bits) Block size Average Comutation Average Comutation Oerand Size (bits) Oerand Size (bits) Block size 6 Block size 8 Figure 7: Comarisons between the average comutation time of the sublogarithmic carry select adder and the rile carry adder In gure 8 the comutation time robability distribution of 128-bit sub-logarithmic carry select adders of dierent block sizes are comared with the 128-bit rile carry adder. As with rile carry the comutation time robability distribution is useful for determining the time after which we can sto the comutation for secial alications. On the dierent curves we can see that the stoing time of the is smaller than the stoing time of the. 3.3 Comletion detection in the In this last section we deal with the comletion detection in the sub-logarithmic carry select adder. The comletion detection is a critical oint in asynchronous systems. Usually, the comletion detection is based on delay-insensitive codes such as double-rail code (see [Ver88] for more information on delay-insensitive codes). Such codes give reliable circuits but their area is rather large. In the, we can use an economical (in term of area) comletion detection strategy. We have shown in section that in most cases there is a least one basic cell on which there is a carry roagation all over this cell. It is not that dicult to build a comletion detection which tends to determinate when all the basic cells have nished their comutation. As in most cases the comutation of all basic cells is comlete after a time close to times the delay of one full-adder cell, we should start the comletion detection after this time. Then we just need to detect when all the block carries (c out is gure 6) have comleted their roagation. This can be done using a double-rail code with a very small chi area.

10 Probability.4 Probability Block size Block size Probability.4 Probability Block size 6 Block size 8 Figure 8: Sub-logarithmic carry select adder comutation time distribution 4 Conclusion In this aer we have shown a new fast asynchronous adder whose average comutation time is O( log 2 n) called sub-logarithmic carry select adder (). The worst case comutation time of the is also smaller than the worst case comutation time of the rile carry adder. We have also resented a comletion detection solution for this adder allowing ecient VLSI imlementations of large adders. In this aer we use the robabilities and esecially the comutation time robability distribution as a owerful tool for erforming comarisons between several asynchronous arithmetic algorithms. In future works we will study self-timed oerators for multilication and division. References [BBK + 94] K. Van Berkel, R. Burgess, J. Kessels, M. Roncken, F. Schalij, and A. Peeters. Asynchronous circuits for low ower: A DCC error corrector. IEEE Design and Test of Comuters, 11(2):22{32, June [BGN47] [Bre7] [GO96] A.W. Burks, H.H. Goldstine, and J. Von Neumann. Preliminary discusion of the logical design of an electronic instrument. Technical reort, The Institut of Advanced Study, Princeton, N.J., (rerinted in Bell and Newell, Comuter structures: readings and examles, Comuter Science series, Mc Graw-Hill, 1971). R.P. Brent. On the addition of binary numbers. IEEE Transactions on Comuters, ages 758{759, August 197. A. De Gloria and M. Olivieri. Statistical carry lookahead adders. IEEE Transactions on Comuters, 45(3):34{347, March 1996.

11 [Hau95] S. Hauck. Asynchronous design methodologies: An overview. Proceedings of the IEEE, 83(1):69{93, January [Kor93] I. Koren. Comuter Arithmetic Algorithms. Prentice-Hall, [Omo94] A.R. Omondi. Comuter Arithmetic Systems. Algorithms, Architecture and Imlementations. Prentice-Hall, [RRPB96] F. Robin, M. Renaudin, G. Privat, and N. Van Den Bossche. A functionally asynchronous array-rocessor for morhological ltering of greysacle images. IEE Comuters and Digital Techniques, July Secial Issue on Asynchronous Processors. [Ver88] [Win65] T. Verhoe. Delay-insensitive codes - an overview. Distributed Comuting, 3:1{8, S. Winograd. On the time required to erform addition. Journal of the Association for Comuting Machinery, 12(2):277{285, Aril 1965.