Logic effort and gate sizing

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Arabella Reeves
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1 EEN454 Dgtal Integrated rcut Desgn Logc effort and gate szng EEN 454 Introducton hp desgners face a bewlderng arra of choces What s the best crcut topolog for a functon? How man stages of logc gve least dela? How wde should the transstors be? Logcal effort s a method to make these decsons Uses a smple model of dela Allows back-of-the-envelope calculatons Helps make rapd comparsons between alternatves t Emphaszes remarkable smmetres??? EEN

2 Dela n a Logc Gate Epress delas n process-ndependent unt d = d abs τ τ = 3R 2 ps n 80 nm process 40 ps n 0.6 μm process 2 R A 2 Y 2 R 2 Y 2 R 2 2 τ= Inverter FO effort dela (due to load) τ= Inverter parastc dela (due to ts own parastc) EEN Dela n a Logc Gate Epress delas n process-ndependent unt dabs d = τ Dela has two components d = f + p EEN

3 Dela n a Logc Gate Epress delas n process-ndependent unt d = d abs τ Dela has two components d = f + p Effort dela f = gh (a.k.a. stage effort) Agan has two components EEN Dela n a Logc Gate Epress delas n process-ndependent unt d abs d = τ Dela has two components d = f + p Effort dela f = gh (a.k.a. stage effort) Agan has two components g: logcal effort Measures relatve ablt of gate to delver current g for nverter EEN

4 Dela n a Logc Gate Epress delas n process-ndependent unt d = d abs τ Dela has two components d = f + p Effort dela f = gh (a.k.a. stage effort) Agan has two components h: electrcal effort = out / n Rato of output to nput capactance Sometmes called fanout EEN Dela n a Logc Gate Epress delas n process-ndependent unt d = d abs τ Dela has two components d = f + p Parastc dela p Represents dela of gate drvng no load Set b nternal parastc capactance EEN

5 Dela Plots d = f + p = gh + p Normalzed Dela: d nput NAND g = p = d = Inverter g = p = d = Electrcal Effort: h = out / n EEN Dela Plots d = f + p = gh + p What about NOR2? Normalzed Dela: d nput NAND Inverter g = 4/3 p = 2 d = (4/3)h + 2 g = p = d = h + Effort Dela: f 0 Parastc Dela: p Electrcal Effort: h = out / n EEN

6 omputng Logcal Effort DEF: Logcal effort s the rato of the nput capactance of a gate to the nput capactance of an nverter delverng the same output current. Measure from dela vs. fanout plots Or estmate b countng transstor wdths Addtonal assumptons: Matched pull-up/pull-down currents/effectve resstances A 2 Y A B 2 2 A 4 Y 2 B 4 2 Y n = 3 g = 3/3 n = 4 g = 4/3 n = 5 g = 5/3 EEN f = gh? Effort Dela: How Does It Work f abs = R eff out = R eff n ( out / n ) = R eff n h = R eff ( ( n / n,nv ) n,nv ) h = gh n,nv R eff = gh ( n,nv R n,nv )(R eff /R n,nv ) = gh ( n,nv R n,nv ).0 3R = Tau f = gh EEN

7 atalog of Gates Logcal effort of common gates Gate tpe Number of nputs n Inverter NAND 4/3 5/3 6/3 (n+2)/3 NOR 5/3 7/3 9/3 (2n+)/3 Trstate / mu XOR, XNOR 4, 4 6, 2, 6 8, 6, 6, 8 EEN atalog of Gates Parastc dela of common gates In multples of p nv ( ) Internal node parastcs neglected when computng parastc delas Gate tpe Number of nputs n Inverter NAND n NOR n Trstate / mu n XOR, XNOR EEN

8 Eample: Rng Oscllator Estmate the frequenc of an N-stage rng oscllator Logcal Effort: g = Electrcal Effort: h = Parastc Dela: p = Stage Dela: d = Frequenc: f osc = EEN Eample: Rng Oscllator Estmate the frequenc of an N-stage rng oscllator Logcal Effort: g = Electrcal Effort: h = Parastc Dela: p = q Stage Dela: d = 2 Frequenc: f osc = /(2*N*d) = /4N 3 stage rng oscllator n 0.6 μm process has frequenc of ~ 200 MHz EEN

9 Eample: FO4 Inverter Estmate the dela of a fanout-of-4 (FO4) nverter d Logcal Effort: g = Electrcal Effort: h = Parastc Dela: p = Stage Dela: d = EEN Eample: FO4 Inverter Estmate the dela of a fanout-of-4 (FO4) nverter d Logcal Effort: g = Electrcal Effort: h = 4 Parastc Dela: p = The FO4 dela s about Stage Dela: d = ps n 0.6 μm process 60 ps n a 80 nm process f/3 ns n an f μm process EEN

10 Multstage Logc Networks Logcal effort generalzes to multstage networks Path Logcal Effort Path Electrcal Effort Path Effort G = g H = out-path n-path F = f = gh 0 g = h = /0 g 2 = 5/3 h 2 = / g 3 = 4/3 h 3 = z/ z g 4 = h 4 = 20/z 20 EEN Multstage Logc Networks Logcal effort generalzes to multstage networks Path Logcal Effort Path Electrcal Effort Path Effort an we wrte F = GH? G = g H = out path n path F = f = gh EEN

11 Paths that Branch No! onsder paths that branch: (Sze of each gate s characterzed b ts nput pn capactance) G = H = GH = h = h 2 = F = GH? EEN Paths that Branch No! onsder paths that branch: (Sze of each gate s characterzed b ts nput pn capactance) G = H = 90 / 5 = 8 GH = 8 h = (5 +5) / 5 = 6 h 2 = 90 / 5 = F = g g 2 h h 2 = 36 = 2GH EEN

12 Branchng Effort Introduce branchng effort Accounts for branchng between stages n path on path b = B= b + on path off path Now we compute the path effort F = GBH Note: h = BH EEN Multstage Delas Path Effort Dela Path Parastc Dela Path Dela D F = f P= p D = d = D + P F EEN

13 Desgnng Fast rcuts D= d = D + P F Dela s smallest when each stage bears same effort fˆ = gh = F N Thus mnmum dela of N stage path s N D = NF + P Ths s a ke result of logcal effort Fnd fastest possble dela Doesn t requre calculatng gate szes EEN Gate Szes How wde should the gates be for least dela? fˆ = gh= g = n out n g fˆ out Workng backward, appl capactance transformaton to fnd nput capactance of each gate gven load t drves. heck work b verfng nput cap spec s met. EEN

14 Eample: 3-stage path Select gate szes and for least dela from A to B A 8 45 B 45 EEN Eample: 3-stage path A 8 45 B 45 Logcal Effort G = Electrcal Effort H = Branchng Effort B = Path Effort F = Best Stage Effort ˆf = Parastc Dela P = Dela D = EEN

15 Eample: 3-stage path A 8 45 B 45 Logcal Effort G = (4/3)*(5/3)*(5/3) = 00/27 Electrcal Effort H = 45/8 Branchng Effort B = 3 * 2 = 6 Path Effort F = GBH = 25 3 Best Stage Effort f ˆ = F = 5 Parastc Dela P = = 7 Dela D = 3*5 + 7 = 22 = 4.4 FO4 EEN Eample: 3-stage path Work backward for szes = = A 8 45 B 45 EEN

16 Eample: 3-stage path Work backward for szes = 45 * (5/3) / 5 = 5 = (5*2) * (5/3) / 5 = 0 45 A P: 4 N: 4 P: 4 N: 6 P: 2 N: 3 B 45 EEN Best Number of Stages How man stages should a path use? Mnmzng number of stages s not alwas fastest Eample: drve 64-bt datapath wth unt nverter D = Intal Drver Datapath Load N: f: D: EEN

17 Best Number of Stages How man stages should a path use? Mnmzng number of stages s not alwas fastest Eample: drve 64-bt datapath wth unt nverter Intal Drver D = NF /N + P = N(64) /N + N Datapath Load N: f: D: Fastest EEN Dervaton onsder addng nverters to end of path How man gve least dela? N = ( ) Defne best stage effort n D= NF + p + N n p nv D N N N = F ln F + F + pnv = 0 N ρ = F N ( ) p + ρ lnρ = 0 nv Logc Block: n Stages Path Effort F F N N - n Etra Inverters EEN

18 ( ) p + ρ lnρ = 0 nv Best Stage Effort has no closed-form soluton Neglectng parastcs (p nv = 0), we fnd ρ = 2.78 (e) For p nv =, solve numercall for ρ = 3.59 EEN Senstvt Analss How senstve s dela to usng eactl the best number of stages? D(N) /D(N) (ρ=6) (ρ =2.4) N / N 2.4 < ρ < 6 gves dela wthn 5% of optmal We can be slopp! I lke ρ = 4 EEN

19 Eample Ben Btdddle s the memor desgner for the Motorol 68W86, an embedded automotve processor. Help Ben desgn the decoder for a regster fle. Decoder specfcatons: 6 word regster fle Each word s 32 bts wde Each bt presents load of 3 unt-szed transstors True and complementar address nputs A[3:0] Each nput ma drve 0 unt-szed transstors A[3:0] A[3:0] Ben needs to decde: 32 bts How man stages to use? How large should each gate be? 6 Regster Fle How fast can decoder operate? 4:6 Decoder 6 words EEN Number of Stages Decoder effort s manl electrcal and branchng Electrcal Effort: H = Branchng Effort: B = If we neglect logcal effort (assume G = ) Path Effort: F = Number of Stages: N = EEN

20 Number of Stages Decoder effort s manl electrcal and branchng Electrcal Effort: H = (32*3) 3) / 0 = 9.6 Branchng Effort: B = 8 If we neglect logcal effort (assume G = ) Path Effort: F = GBH = 76.8 Number of Stages: N = log 4 F = 3. Tr a 3-stage desgn EEN Gate Szes & Dela Logcal Effort: G = Path Effort: F = Stage Effort: f ˆf = Path Dela: Gate szes: D = z = = A[3] A[3] A[2] A[2] A[] A[] A[0] A[0] z word[0] 96 unts of wordlne capactance z word[5] EEN

21 Gate Szes & Dela Logcal Effort: G = * 6/3 * = 2 Path Effort: F = GBH = 54 /3 Stage Effort: f ˆ = F = Path Dela: D= 3 fˆ = 22. Gate szes: z = 96*/5.36 = 8 = 8*2/5.36 = 6.7 A[3] A[3] A[2] A[2] A[] A[] A[0] A[0] z word[0] 96 unts of wordlne capactance z word[5] EEN omparson ompare man alternatves wth a spreadsheet Desgn N G P D NAND4-INV NAND2-NOR2 2 20/ INV-NAND4-INV NAND4-INV-INV-INV NAND2-NOR2-INV-INV 4 20/ NAND2-INV-NAND2-INV 4 6/ INV-NAND2-INV-NAND2-INV 5 6/ NAND2-INV-NAND2-INV-INV-INV 6 6/ EEN

22 Revew of Defntons Term Stage Path number of stages N logcal effort g G = g out out-path electrcal effort h = H = n n-path on-path + off-path branchng effort b = B = b on-path effort f = gh F = GBH effort dela f D F = f parastc dela p P= p dela d = f + p D = d = DF + P EEN Method of Logcal Effort ) ompute path effort 2) Estmate best number of stages 3) Sketch path wth N stages 4) Estmate least dela 5) Determne best stage effort 6) Fnd gate szes F = GBH N = log 4 F N D = NF + P ˆ N f = F g out n = fˆ EEN

23 Lmts of Logcal Effort hcken and egg problem Need path to compute G But don t know number of stages wthout G Smplstc dela model Neglects nput rse tme effects Interconnect Iteraton requred n desgns wth wre Mamum speed onl Not mnmum area/power for constraned dela EEN Summar of Logcal Effort Logcal effort s useful for thnkng of dela n crcuts Numerc logcal effort characterzes gates NANDs are faster than NORs n MOS Paths are fastest when effort delas are ~4 Path dela s weakl senstve to stages, szes But usng fewer stages doesn t mean faster paths Dela of path s about log 4 F FO4 nverter delas Inverters and NAND2 best for drvng large caps Provdes language for dscussng fast crcuts But requres practce to master EEN

24 Specal ase: ascaded Inverters Smple elegant answer f neglectng parastc delas 2 3 k p: stage rato L sze + = p sze R + =R /p + = p EEN Dela of ascaded Drvers Dela between stage and + R + = p R Total dela from stage to stage k pr + pr pr k- k- + R k L = pr + pr + + pr + R L / p k- = (k-)pr +R /p k- L EEN

25 Mnmum Dela Stage Rato A = (k-) R, B = R L t = A p + B p -k Let dervatve t = 0 A + (-k) B p -k = 0 p k = (k-) B/A = L / p = [ L / ] /k EEN Optmal Number of Stages L = p k k = ln( L / ) / ln p t = k p R = (ln ( L / ) / ln p) p R Dela t reaches mnmum when stage rato: p = e 2.78 EEN

Lecture 7: Multistage Logic Networks. Best Number of Stages

Lecture 7: Multistage Logic Networks. Best Number of Stages Lecture 7: Multstage Logc Networks Multstage Logc Networks (cont. from Lec 06) Examples Readng: Ch. Best Number of Stages How many stages should a path use? Mnmzng number of stages s not always fastest