Clock T FF1 T CL1 T FF2 T T T FF T T FF T CL T FF T CL T FF T T FF T T FF T CL. T cyc T H. Clock T FF T T FF T CL T FF T T FF T CL.

Transcription

1 etup TA 60 c, vcc 3v Hold TA 30 c, vcc 5v Tkew TL TL TH FF FF 2 T cyc T H T L Clock TpdFF 2 TpdCL2Tetup FF Tcyc TL 2 2 TpdFF TpdCL Tetup FF2 TH 2 T FF T T FF T CL Hold L cd cd T FF T T FF T CL Hold L cd cd FF FF 2 FF FF 2 FF FF 2 Tkew TH TH TL FF 2 FF T cyc T H T L Clock T FF T CL T FF2 T T 2 T FF T CL T FF T pd pd etup L T FF T T FF T CL Hold H cd cd pd pd etup cyc H T FF T T FF T CL Hold H cd cd FF FF 2 FF FF 2 FF FF 2 ( '!&$%%###!

2 FF 2 FF T L T H T cyc T H T L Clock T FF2 T CL2 T FF T FF 2 pd pd etup L T FF T CL T FF T pd pd etup H FF 2 T Hold THold Tpd FF 2 FF #! FF FF 2 $ #! &% T FF2 T CL2 T FF T T ( FF) T T ( FF2) T ( CL2) pd pd etup L hold L cd cd T FF2 T CL2 T FF T T ( FF 2) T ( CL2) T ( FF) pd pd etup L cd cd hold T, T T, T pd etup cd Hold ( '!&$%%###!

3 NAND( x,'') x ) t pd t cd t setup t hold NAND In In 2 D Out CLK '' '' NAND T cd T hold ( '!&$%%###!

4 RA CA W A0 A CA W D A0 A KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 Decoder 3 8 RA KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C A2 A3 A 4 D D D D D D D 0 ' KM4C6000C-5 Fanout DRAM' D 7 DRAM RA RA DRAM Tpd Decoder inout Tpd t * t Tpd RRH RRH t * t Tpd RAH RAH tcrp* tcrptpd t * t Tpd RAL RAL t * t Tpd RAC RAC tcac* tcac Tpd ( '!&$%%###!

5 CA W D A0 A KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 KM4C6000C-5 Decoder 3 8 A2 A3 A 4 RA ( DRAM RA ) W CA RA t * t Tpd RA RAH RAH tpd 0 ( '!&$%%###!

6 t RCD t CA CA RA trac 50 T t ns min RC 90 Tmin tra trp ns T max t, t max t, t t, t t 50 t min CRP AR RAC max RAD AAmax RCD min CAC max OFF min max 5, 0 max 50,5 25, ns 75>tRA,tCH,tRDC+tRH T trp>30 min 05 ns $ trcd>20 55 tcrp= ns & %&% 5ns 45ns T min 00 T max t, t max t, t t, t t 50 t min CRP AR RAC max RAD AAmax RCD min CAC max OFF min max 5, 0 max 50,5 25, ns Tmin 95ns ns ( '!&$%%###!

7 * CA t max t, t rows max t t, t min min 2 ns ns ns ns CRP AR RA RP RC max 5, 0 2 max 50 30, s 0.37ms W CA t max t, t max t, t rows max t t, t min min 2 RP CR RPC CP RA RP RC max 30,5max 5,0 2 max 5030, ns 2 90ns s 0.37ms 64ms DRAM 0.4msCA BEFORE RA) +*DRAM ++ 5ms 0.4ms 9000nsRA ONLY DRAMTRADEOFF DRAM + 0.4msCA BEFORE RA) CBR RA ONLY++* ( '!&$%%###!

8 + Idle Output_Ready Compute Init0 Clr_Reg Init DR_Num LD_A el_cnt Init2 DR_Y LD_B LD_C el_cnt Z Z' Z CheckZ el_cnt Calc ALU_OP DR_ALU LD_C updnum el_cnt DR_ALU LD_A OutRdy Clr_Reg , Idle Init0 ++ Num Init ++ Y Init2 $ + ANum- updnum! ++ CB+C Calc - + Num-=0 CheckZ. + ALU_OP DR_Y DR_Num DR_ALU LD_C LD_B LD_A $ ! P Compute= Z=0 Z= el_cnt Z' ( '!&$%%###!

9 Output Compute Z Preset tate, ROM Output_Ready Next tate Register Controls &% Output Compute Z Preset tate ROM Cominational Logic Next tate Output_Ready Controls ZCompute$-ROM /Output_Ready$ROM 5 5 ROM $ 2 &% ROM ROM Address Data Com DR_ P OutRdy ClrReg elcnt ALUOP DR_Y pute Z Num DRALU LD_C LD_B LD_A N ( '!&$%%###! Register

10 ROM Addres Data Com P pute Z N ( 0 Dr_Num Output_Ready Clr_Reg Next tate Decoder OR OR el_cnt Dr_Y, Ld_B Dr_ALU ALU_OP 6 7 OR OR Ld_C Ld_A ( '!&$%%###!

11 Preset tate Test ROM True False Outputs Output_Ready Controls Compute Z 0 ele ctor elector Next tate Register &% Preset tate Test ROM True False Controls Output_Ready Compute Z 0 ele ctor elector Next tate Combinational Logic Register False True $0Test Outputs ROM ROMtest, linkt, linkf ( '!&$%%###!

12 Address test + linktrue linkfalse Output ROM Address test linktrue linkfalse a d b e F J c f T ns ( '!&$%%###!

13 ) T 2T s 2T c 42ns L pd pd o TP 42 c FA s o co FA s c FA s o FA FA co co s s Count FF 9 T max,0 T FF T K 4 TPmax FF 539ns cyc pd su CL T 3AdderP KT 49 76ns L cyc TP max 9 ( '!&$%%###!

14 ai bi tart FA ci c s o 2 el Controller T T FF T el T FA T FF tart el, Done ns cyc pd pd pd su T nt 26n n L cyc TP ntcyc Done n ( '!&$%%###!

15 ! $ D-2, G-, H-, K-, N-,- n n 48, 48 ' 75, ! Latency - ' 2 2 # pipe $ $ $ $ 2 2 TP T cyc!! -... T L n7 K 3 T 4 cyc KT cyc D-2, G-, H-, K-, N-,- D-,G-,H-,I-,J-,K-,N-,- D-,G-,H-,M-,N-,O-,- D-,G-,H-,O-,P-,- I-,J-,K-,N-,- M-,N-,O-,- TP T cyc n!t cyc 4 6 ( '!&$%%###!

16 while (a OR b) do nothing; c=0; while (a NAND b) do nothing; c=; a b C c d F a F b C F c F d a b J F c d x A x f A, B,, t x P g f x P f x f x f p B p p 2 g A g B p 2 ( '!&$%%###!

17 * A x A, B f f p B p p F J B p 2 A g g ForkJoin W A x A, B f f p B p p F J W B p 2 A g g (! ( ( '!&$%%###!

18 + rs label - beqz rs,label - beq $rs,$zero,label branch blt * & %branch branch )label label= add $t7, $t7, $t beq $t7, $t7, addi $t7,$t7, $t7 addi branch $t7( [0x ] add $t0,$zero,$zero $t0 = 0 [0x ] addi $s0,$zero,0x4004 $s0 = 0x4004 [0x ] addi $t0,$t0,4 $t0 += 4 [0x C] add $s0,$s0,$t0 $s0 += $t0 [0x ] jr $s0 Goto $s0 +$t0 $s0*$s0=0x4004 $t0=4!$t0 $ $t0! $s0*$s0=0x4008$t0$s0! $s00x400 - $t0=8!$t0. jr $s0*+$s0=0x40$t0$s0, $s0jr ' '$t0jr ( '!&$%%###!

19 , s2=s2+0 add $s2, $s2, $zero NOP s2=s2+0 addi $s2, $s2, 0 NOP ( ) NOP j 0x ) ( beq NOP beq $s2, $s2 0x ' *( % n n 5 n # -& 2 & 4.5 n 8 n%ingle Cycle MIP.data 0x # Data egment start (assembler directive) A:.word 0 # array element A[0] of Fibonacci series array.word 0 # A[].word 0.word 0.word 0.word 0.word 0.word 0.word 0.word 0 # A[9] n:.word 9 # n.text.globl main main: la $s0, A # Code egment start (assembler directive) # load value of A into register $s0 --> $s0 = &A[0] la $a0, n # load address of n into $a0 # lw $a0, 0($a0) # load value of n into $a0 # --> $a0 = n loop: addi $t0, $zero, 0 # first element $t0 = a_ = 0 addi $t, $zero, # second element $t = a_2 = sw $t0, 0($s0) addi $a0, $a0 - beq $a0, $zero, done sw $t, 4($s0) # stores element a_n # decrease index: n=n- # stores element a_n+ done: add $t0, $t0, $t add $t, $t0, $t addi $s0, $s0, 8 addi $a0, $a0, - bne $a0, $zero, loop # calculates $t0 = a_n+2 # calculates $t = a_n+3 # moves to the next 2 elements in the array # decrease index: n=n- addi $v0, $0, 0 # exit the program by calling syscall with parameter 0 syscall ( '!&$%%###!

20 .data 0x # Data egment start n:.word # n $ 0 2 n v.text # Code egment start.globl main main: la $a0, n lw $a0, 0($a0) # load $a0=n addi $s0, $zero, # $s0 = addi $s, $zero, 0 # $s = 0 loop: slt $s2, $a0, $s # if $a0 < $s then $s2 = else $s2 = 0 bne $s2, $zero, finish # if $s2 == goto finish # actually: if $a0 < $s goto finish add $s0, $s0, $s0 # $s0 = 2 * $s0 addi $s, $s, # $s ++ j loop # goto loop finish: add $v0, $s0, $zero # $v0 = $s0 ( '!&$%%###!

21 ! jrr-type orii-type jj-type $s2 $s=, $s2=5, $s3=3 ALUmux +--Zero Extend ALUrc=2$ rsoralu OR PC+4 R-type lw/sw PC) (beq ) PC+4 beq j ( '!&$%%###!

22 Preserved on call ( Prologue Epilogue Preserved on call $a0-$a3 A $a0a $ B B jal B $a0c C jal C,$a0BC $$a0 BEpilogue Preseved on $v0,$v call B B$v0A post-callbpre-callframe Preserved on call &%)++3 2 Preserved on call&% ( ( '!&$%%###!

23 main: addi $sp, $sp, -32 # Main - prologue sw $ra, 20($sp) # Main - prologue sw $fp, 6($sp) # Main - prologue addi $fp, $sp, 28 # Main - prologue li $a0, 2 li $a, 8 jal gcd lw $fp, 6($sp) # Main - epilogue lw $ra, 20($sp) # Main - epilogue addi $sp, $sp, 32 # Main - epilogue jr $ra # Main - epilogue gcd: addi $sp, $sp, -32 # GCD - prologue sw $ra, 20($sp) # GCD - prologue sw $fp, 6($sp) # GCD - prologue sw $a0, 2($sp) # GCD - prologue sw $a, 8($sp) # GCD - prologue sw $s0, 4($sp) # GCD - prologue addi $fp, $sp, 28 # GCD - prologue slt $t0, $a0, $a bne $t0, $0, smaller slt $s0, $a, $a0 bne $s0, $0, greater addi $v0, $a0, 0 j return smaller: sub $a, $a, $a0 j callagain greater: sub $a0, $a0, $a callagain: jal gcd return: lw $s0, 4($sp) # GCD - prologue lw $a, 8($sp) # GCD - epilogue lw $a0, 2($sp) # GCD - epilogue lw $fp, 6($sp) # GCD - epilogue lw $ra, 20($sp) # GCD - epilogue addi $sp, $sp, 32 # GCD - epilogue jr $ra # GCD - epilogue ) gcdinstances $fp Frame ) $v0 gcd jal gcd returnreturn ))() $v0 $sp $ra $fp $a0 $a $s0 ( '!&$%%###!

24 # MemRead (lw (!opcode Dispatch ROM cyclememread ALUOut rt [20-6]( Label dr-a dr-b ld-a ld-b dr-alu ALUop Done equencing Idle Dispatch LoadA eq LoadB eq CalcA-B 0 Dispatch2 A<-A-B 0 CalcA-B B<-B-A CalcA-B $ AddrCtrl tate Mux CalcA-B Dispatch ROM 2 Dispatch ROM CC tart 0, 0 equencing ROM bitROM ( '!&$%%###!

25 rt &!%rs&rs %rs! DataMem[-4($rs)]$rt $rs$rs 4 MemRead ALUrcA=0 IorD=0 IRWrite ALUrcB=0 ALUOp=00 PCWrite PCource=00 ALUrcA=0 ALUrcB= ALUOp=00 beqsub ALUrcA= ALUrcB=00 ALUOp=0 PCWriteCond PCource=0 RegDest=0 RegWrite MemtoReg=0 ( '!&$%%###!