CSc 256 Midterm 2 Fall 2010

Size: px
Start display at page:

Download "CSc 256 Midterm 2 Fall 2010"

Transcription

1 CSc 256 Midterm 2 Fall 2010 NAME: 1a)YouaregivenaMIPSbranchinstruction: x:beq$12,$0,y Theaddressofthelabel"y"is0x40013c.Thememorylocationat"x"contains: addresscontents 0x ????????????????...whichrepresentsthebeqinstruction;the????...????arethe 16 bitconstant.findthe16 bitconstant (12points) ANS:BTA=&beq+4+offset 0x40013c=0x offset offset=0x40013c 0x400208=0x40013c+0xffbffdf4=0xffffff30 = constant= b)YouaregiventhisMIPSinstruction: lb $8,x Thelabelxisatmemoryaddress0x TranslatethisMIPSinstructiontoanefficientsequenceofmachine languageinstructions.youonlyhavetoshowthetextformofthe machinelanguageinstructions;don'ttranslateintobinary. (5points) ANS: lui$1,0x1001 lb$8,0x408($1)

2 1c)ThisisamemorylocationthatcontainsaMIPSinstruction: addresscontents [0x ] 0xad74000c TranslateitintotheMIPSassemblylanguageinstruction(showthe operation,operands,etc): (13points) ANS: 0xad74000c= opcode=101011sw rsis11,rtis20,constantis12 sw$20,12($11)

3 Problem2: Considerthisdigitallogiccircuit:

4 a)filloutanequivalenttruthtableforthecircuit.(14points) X3 X2 X1 X0 y b)writeanequivalentlogicexpressionforoutputy,insumofproductsform.(6 points) y=~x3x2x1x0+x3~x2x1x0+x3x2x1x0

5 Problem3: Refer to the MIPS single-cycle datapath in the sheets provided. Show the control signals for the MIPS instructions, in the table below. Note that some of the control signals have new names. (30 points) Hint: ALUOp control bits are 00 (force ALU to add), 01 (force ALU to subtract), 10 (follow operation specified by bits 5-0 of instruction word) [SelA is branch, SelB is ALUSrc, SelC is RegDst, SelD is MemToReg] a) R-type ALUOp1 ALUOp0 RegWrite MemRead MemWrite SelA SelB SelC SelD x b) sw ALUOp1 ALUOp0 RegWrite MemRead MemWrite SelA SelB SelC SelD x x x

6 Problem 4 For the MIPS single-cycle datapath given, suppose we build a new implementation using slower technology. These are the latencies through the main components: Register Read Register Write ALU operation Memory Read Memory Write 15 ns 15 ns 25 ns 20 ns 20 ns a) Estimate the time taken for each type of instruction to complete (14 points): lw 20 (IF) + 15 (RegR) + 25 (ALU) + 20 (MemR) + 15 (RegW) = 95 ns sw 20 (IF) + 15 (RegR) + 25 (ALU) + 20 (MemW) = 80 ns R-type 20 (IF) + 15 (RegR) + 25 (ALU) + 15 (RegW) = 75 ns Beq 20 (IF) + 15 (RegR) + 25 (ALU) = 60 ns b) What is the cycle time for this implementation? What is the clock rate in MHz? (Hint: 1 ns = 10^-9 seconds, 1 MHz = 10^6 Hz.) You can show an expression that evaluates to the clock rate, but make sure the unit is in MHz. (6 points) ANS: Cycle time = 95 ns Clock rate = 1 / (95 * 10^-9) Hz = 10^9 / 95 Hz = 1000/95 MHz

7 MIPSinstructions op1,op2areregisters,op3isregisterorconstant cont[op1]meanscontentsofop1 moveop1,op2 cont[op1]=cont[op2] addop1,op2,op3 cont[op1]=cont[op2]+cont[op3] subop1,op2,op3 cont[op1]=cont[op2] cont[op3] mulop1,op2,op3 cont[op1]=cont[op2]*cont[op3] divop1,op2,op3 cont[op1]=cont[op2]/cont[op3] remop1,op2,op3 cont[op1]=cont[op2]%cont[op3] notop1,op2 cont[op1]=notcont[op2](bitwise) andop1,op2,op3 cont[op1]=cont[op2]andcont[op3](bitwise) orop1,op2,op3 cont[op1]=cont[op2]orcont[op3](bitwise) nandop1,op2,op3 cont[op1]=cont[op2]nandcont[op3](bitwise) norop1,op2,op3 cont[op1]=cont[op2]norcont[op3](bitwise) xorop1,op2,op3 cont[op1]=cont[op2]xorcont[op3](bitwise) sllop1,op2,amt cont[op1]=cont[op2]shiftleftlogical byamtbits srlop1,op2,amt cont[op1]=cont[op2]shiftrightlogical byamtbits sraop1,op2,amt cont[op1]=cont[op2]shiftrightarithmetic byamtbits rolop1,op2,amt cont[op1]=cont[op2]rotateleftbyamtbits rorop1,op2,amt cont[op1]=cont[op2]rotaterightbyamtbits blabel gotolabel jlabel gotolabel beqop1,op2,label if(cont[op1]==cont[op2])gotolabel bneop1,op2,label if(cont[op1]!=cont[op2])gotolabel bgtop1,op2,label if(cont[op1]>cont[op2])gotolabel bgeop1,op2,label if(cont[op1]>=cont[op2])gotolabel bltop1,op2,label if(cont[op1]<cont[op2])gotolabel bleop1,op2,label if(cont[op1]<=cont[op2])gotolabel beqzop1,label if(cont[op1]==0)gotolabel bnezop1,label if(cont[op1]!=0)gotolabel bgtzop1,label if(cont[op1]>0)gotolabel bgezop1,label if(cont[op1]>=0)gotolabel bltzop1,label if(cont[op1]<0)gotolabel blezop1,label if(cont[op1]<=0)gotolabel lar,label cont[r]=addressoflabel lir,constant cont[r]=constant lwr,?? cont[r]=m[addr]

8 lbr,?? cont[r]=m[addr],sign extended lbur,?? cont[r]=m[addr],zero extended swr,?? M[ADDR]=cont[R] sbr,?? m[addr]=low8 bitsofcont[r] if??isalabel,addr=addressoflabel if??is(r),addr=cont[r] if??isconstant(r),addr=cont[r]+constant if??islabel(r),addr=cont[r]+addressoflabel mtc0op1,op2 contentsofcoprocessor0registerop1= contentsofmipsregisterop2 mfc0op1,op2 contentsofmipsregisterop1= contentsofcoprocessor0registerop2 Syscallusage: printanint $v0=1,$a0=inttobeprinted printastring $v0=4,$a0=addressofstringtobeprinted readanint $v0=5,inputintappearsin$v0 exit $v0=10 MIPSregisternames: $0 $1 $2,$3 $v0,$v1 $4 $7 $a0 $a3 $8 $15 $t0 $t7 $16 $23 $s0 $s7 $24 $25 $t8 $t9 $26 $27 $k0 $k1 $28 $gp $29 $sp $30 $s8 $31 $ra

9 ss ssst tttt dddd d add rd,rs,rt ss ssst tttt dddd d sub rd,rs,rt ss ssst tttt mult rs,rt ss ssst tttt div rs,rt ss ssst tttt dddd d addu rd,rs,rt ss ssst tttt dddd d subu rd,rs,rt ss ssst tttt multu rs,rt ss ssst tttt divu rs,rt dddd d mfhi rd ss sss mthi rs dddd d mflo rd ss sss mtlo rs ss ssst tttt dddd d and rd,rs,rt ss ssst tttt dddd d nor rd,rs,rt ss ssst tttt dddd d or rd,rs,rt ss ssst tttt dddd d xor rd,rs,rt ss ssst tttt dddd d sllv rd,rt,rs ss ssst tttt dddd d srlv rd,rt,rs ss ssst tttt dddd d srav rd,rt,rs ss ssst tttt iiii iiii iiii iiii addi rt,rs,i ss ssst tttt iiii iiii iiii iiii addiu rt,rs,i ss ssst tttt iiii iiii iiii iiii andi rt,rs,i t tttt iiii iiii iiii iiii lui rt,i ss ssst tttt iiii iiii iiii iii ori rt,rs,i ss ssst tttt iiii iiii iiii iiii xori rt,rs,i t tttt dddd diii ii sll rd,rt,i t tttt dddd diii ii srl rd,rt,i t tttt dddd diii ii sra rd,rt,i bb bbbt tttt iiii iiii iiii iiii lw rt,i(rb) bb bbbt tttt iiii iiii iiii iiii lb rt,i(rb) bb bbbt tttt iiii iiii iiii iiii lbu rt,i(rb) bb bbbt tttt iiii iiii iiii iiii sw rt,i(rb) bb bbbt tttt iiii iiii iiii iiii sb rt,i(rb) ss sss iiii iiii iiii iiii bltz rs,i ss sss iiii iiii iiii iiii bgez rs,i ss sss iiii iiii iiii iiii blez rs,i ss sss iiii iiii iiii iiii bgtz rs,i ss ssst tttt iiii iiii iiii iiii beq rs,rt,i

10 ss ssst tttt iiii iiii iiii iiii bne rs,rt,i ss ssst tttt dddd d slt rd,rs,rt ss ssst tttt iiii iiii iiii iiii slti rt,rs,i ii iiii iiii iiii iiii iiii iiii j I ss sss jr rs ii iiii iiii iiii iiii iiii iiii jal I ss sss dddd d jalr rd,rs syscall

CPU DESIGN The Single-Cycle Implementation

CPU DESIGN The Single-Cycle Implementation CSE 202 Computer Organization CPU DESIGN The Single-Cycle Implementation Shakil M. Khan (adapted from Prof. H. Roumani) Dept of CS & Eng, York University Sequential vs. Combinational Circuits Digital circuits

More information

Arithmetic and Logic Unit First Part

Arithmetic and Logic Unit First Part Arithmetic and Logic Unit First Part Arquitectura de Computadoras Arturo Díaz D PérezP Centro de Investigación n y de Estudios Avanzados del IPN adiaz@cinvestav.mx Arquitectura de Computadoras ALU1-1 Typical

More information

Computer Engineering Department. CC 311- Computer Architecture. Chapter 4. The Processor: Datapath and Control. Single Cycle

Computer Engineering Department. CC 311- Computer Architecture. Chapter 4. The Processor: Datapath and Control. Single Cycle Computer Engineering Department CC 311- Computer Architecture Chapter 4 The Processor: Datapath and Control Single Cycle Introduction The 5 classic components of a computer Processor Input Control Memory

More information

TEST 1 REVIEW. Lectures 1-5

TEST 1 REVIEW. Lectures 1-5 TEST 1 REVIEW Lectures 1-5 REVIEW Test 1 will cover lectures 1-5. There are 10 questions in total with the last being a bonus question. The questions take the form of short answers (where you are expected

More information

Computer Architecture. ECE 361 Lecture 5: The Design Process & ALU Design. 361 design.1

Computer Architecture. ECE 361 Lecture 5: The Design Process & ALU Design. 361 design.1 Computer Architecture ECE 361 Lecture 5: The Design Process & Design 361 design.1 Quick Review of Last Lecture 361 design.2 MIPS ISA Design Objectives and Implications Support general OS and C- style language

More information

Designing Single-Cycle MIPS Processor

Designing Single-Cycle MIPS Processor CSE 32: Introdction to Compter Architectre Designing Single-Cycle IPS Processor Presentation G Stdy:.-. Gojko Babić 2/9/28 Introdction We're now ready to look at an implementation of the system that incldes

More information

Spiral 1 / Unit 3

Spiral 1 / Unit 3 -3. Spiral / Unit 3 Minterm and Maxterms Canonical Sums and Products 2- and 3-Variable Boolean Algebra Theorems DeMorgan's Theorem Function Synthesis use Canonical Sums/Products -3.2 Outcomes I know the

More information

Computer Architecture. ESE 345 Computer Architecture. Design Process. CA: Design process

Computer Architecture. ESE 345 Computer Architecture. Design Process. CA: Design process Computer Architecture ESE 345 Computer Architecture Design Process 1 The Design Process "To Design Is To Represent" Design activity yields description/representation of an object -- Traditional craftsman

More information

A Second Datapath Example YH16

A Second Datapath Example YH16 A Second Datapath Example YH16 Lecture 09 Prof. Yih Huang S365 1 A 16-Bit Architecture: YH16 A word is 16 bit wide 32 general purpose registers, 16 bits each Like MIPS, 0 is hardwired zero. 16 bit P 16

More information

Review. Combined Datapath

Review. Combined Datapath Review Topics:. A single cycle implementation 2. State Diagrams. A mltiple cycle implementation COSC 22: Compter Organization Instrctor: Dr. Amir Asif Department of Compter Science York University Handot

More information

CSE Computer Architecture I

CSE Computer Architecture I Execution Sequence Summary CSE 30321 Computer Architecture I Lecture 17 - Multi Cycle Control Michael Niemier Department of Computer Science and Engineering Step name Instruction fetch Instruction decode/register

More information

Lecture 3, Performance

Lecture 3, Performance Repeating some definitions: Lecture 3, Performance CPI MHz MIPS MOPS Clocks Per Instruction megahertz, millions of cycles per second Millions of Instructions Per Second = MHz / CPI Millions of Operations

More information

Lecture 3, Performance

Lecture 3, Performance Lecture 3, Performance Repeating some definitions: CPI Clocks Per Instruction MHz megahertz, millions of cycles per second MIPS Millions of Instructions Per Second = MHz / CPI MOPS Millions of Operations

More information

Project Two RISC Processor Implementation ECE 485

Project Two RISC Processor Implementation ECE 485 Project Two RISC Processor Implementation ECE 485 Chenqi Bao Peter Chinetti November 6, 2013 Instructor: Professor Borkar 1 Statement of Problem This project requires the design and test of a RISC processor

More information

Clock T FF1 T CL1 T FF2 T T T FF T T FF T CL T FF T CL T FF T T FF T T FF T CL. T cyc T H. Clock T FF T T FF T CL T FF T T FF T CL.

Clock T FF1 T CL1 T FF2 T T T FF T T FF T CL T FF T CL T FF T T FF T T FF T CL. T cyc T H. Clock T FF T T FF T CL T FF T T FF T CL. etup TA 60 c, vcc 3v Hold TA 30 c, vcc 5v Tkew TL TL TH FF FF 2 T cyc T H T L Clock TpdFF 2 TpdCL2Tetup FF Tcyc TL 2 2 TpdFF TpdCL Tetup FF2 TH 2 T FF T T FF T CL Hold L cd cd T FF T T FF T CL Hold L cd

More information

Building a Computer. Quiz #2 on 10/31, open book and notes. (This is the last lecture covered) I wonder where this goes? L16- Building a Computer 1

Building a Computer. Quiz #2 on 10/31, open book and notes. (This is the last lecture covered) I wonder where this goes? L16- Building a Computer 1 Building a Computer I wonder where this goes? B LU MIPS Kit Quiz # on /3, open book and notes (This is the last lecture covered) Comp 4 Fall 7 /4/7 L6- Building a Computer THIS IS IT! Motivating Force

More information

Design of Digital Circuits Lecture 14: Microprogramming. Prof. Onur Mutlu ETH Zurich Spring April 2017

Design of Digital Circuits Lecture 14: Microprogramming. Prof. Onur Mutlu ETH Zurich Spring April 2017 Design of Digital Circuits Lecture 4: Microprogramming Prof. Onur Mutlu ETH Zurich Spring 27 7 April 27 Agenda for Today & Next Few Lectures! Single-cycle Microarchitectures! Multi-cycle and Microprogrammed

More information

EC 413 Computer Organization

EC 413 Computer Organization EC 413 Computer Organization rithmetic Logic Unit (LU) and Register File Prof. Michel. Kinsy Computing: Computer Organization The DN of Modern Computing Computer CPU Memory System LU Register File Disks

More information

CPSC 3300 Spring 2017 Exam 2

CPSC 3300 Spring 2017 Exam 2 CPSC 3300 Spring 2017 Exam 2 Name: 1. Matching. Write the correct term from the list into each blank. (2 pts. each) structural hazard EPIC forwarding precise exception hardwired load-use data hazard VLIW

More information

Implementing the Controller. Harvard-Style Datapath for DLX

Implementing the Controller. Harvard-Style Datapath for DLX 6.823, L6--1 Implementing the Controller Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 6.823, L6--2 Harvard-Style Datapath for DLX Src1 ( j / ~j ) Src2 ( R / RInd) RegWrite MemWrite

More information

Outcomes. Spiral 1 / Unit 2. Boolean Algebra BOOLEAN ALGEBRA INTRO. Basic Boolean Algebra Logic Functions Decoders Multiplexers

Outcomes. Spiral 1 / Unit 2. Boolean Algebra BOOLEAN ALGEBRA INTRO. Basic Boolean Algebra Logic Functions Decoders Multiplexers -2. -2.2 piral / Unit 2 Basic Boolean Algebra Logic Functions Decoders Multipleers Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name eamples of each.

More information

COVER SHEET: Problem#: Points

COVER SHEET: Problem#: Points EEL 4712 Midterm 3 Spring 2017 VERSION 1 Name: UFID: Sign here to give permission for your test to be returned in class, where others might see your score: IMPORTANT: Please be neat and write (or draw)

More information

L07-L09 recap: Fundamental lesson(s)!

L07-L09 recap: Fundamental lesson(s)! L7-L9 recap: Fundamental lesson(s)! Over the next 3 lectures (using the IPS ISA as context) I ll explain:! How functions are treated and processed in assembly! How system calls are enabled in assembly!

More information

A Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor

A Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor A Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor Farhad Mehdipour, H. Noori, B. Javadi, H. Honda, K. Inoue, K. Murakami Faculty

More information

CA Compiler Construction

CA Compiler Construction CA4003 - Compiler Construction Code Generation to MIPS David Sinclair Code Generation The generation o machine code depends heavily on: the intermediate representation;and the target processor. We are

More information

Pipelining. Traditional Execution. CS 365 Lecture 12 Prof. Yih Huang. add ld beq CS CS 365 2

Pipelining. Traditional Execution. CS 365 Lecture 12 Prof. Yih Huang. add ld beq CS CS 365 2 Pipelining CS 365 Lecture 12 Prof. Yih Huang CS 365 1 Traditional Execution 1 2 3 4 1 2 3 4 5 1 2 3 add ld beq CS 365 2 1 Pipelined Execution 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5

More information

Lecture 9: Control Hazard and Resolution. James C. Hoe Department of ECE Carnegie Mellon University

Lecture 9: Control Hazard and Resolution. James C. Hoe Department of ECE Carnegie Mellon University 18 447 Lectre 9: Control Hazard and Resoltion James C. Hoe Department of ECE Carnegie ellon University 18 447 S18 L09 S1, James C. Hoe, CU/ECE/CALC, 2018 Yor goal today Hosekeeping simple control flow

More information

Lecture 13: Sequential Circuits, FSM

Lecture 13: Sequential Circuits, FSM Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines Reminder: midterm on Tue 2/28 will cover Chapters 1-3, App A, B if you understand all slides, assignments,

More information

Topics: A multiple cycle implementation. Distributed Notes

Topics: A multiple cycle implementation. Distributed Notes COSC 22: Compter Organization Instrctor: Dr. Amir Asif Department of Compter Science York University Handot # lticycle Implementation of a IPS Processor Topics: A mltiple cycle implementation Distribted

More information

EXAMPLES 4/12/2018. The MIPS Pipeline. Hazard Summary. Show the pipeline diagram. Show the pipeline diagram. Pipeline Datapath and Control

EXAMPLES 4/12/2018. The MIPS Pipeline. Hazard Summary. Show the pipeline diagram. Show the pipeline diagram. Pipeline Datapath and Control The MIPS Pipeline CSCI206 - Computer Organization & Programming Pipeline Datapath and Control zybook: 11.6 Developed and maintained by the Bucknell University Computer Science Department - 2017 Hazard

More information

ECEN 651: Microprogrammed Control of Digital Systems Department of Electrical and Computer Engineering Texas A&M University

ECEN 651: Microprogrammed Control of Digital Systems Department of Electrical and Computer Engineering Texas A&M University ECEN 651: Microprogrammed Control of Digital Systems Department of Electrical and Computer Engineering Texas A&M University Prof. Mi Lu TA: Ehsan Rohani Laboratory Exercise #4 MIPS Assembly and Simulation

More information

CSCI-564 Advanced Computer Architecture

CSCI-564 Advanced Computer Architecture CSCI-564 Advanced Computer Architecture Lecture 8: Handling Exceptions and Interrupts / Superscalar Bo Wu Colorado School of Mines Branch Delay Slots (expose control hazard to software) Change the ISA

More information

61C In the News. Processor Design: 5 steps

61C In the News. Processor Design: 5 steps www.eetimes.com/electronics-news/23235/thailand-floods-take-toll-on--makers The Thai floods have already claimed the lives of hundreds of pele, with tens of thousands more having had to flee their homes

More information

Review: Single-Cycle Processor. Limits on cycle time

Review: Single-Cycle Processor. Limits on cycle time Review: Single-Cycle Processor Jump 3:26 5: MemtoReg Control Unit LUControl 2: Op Funct LUSrc RegDst PCJump PC 4 uction + PCPlus4 25:2 2:6 2:6 5: 5: 2 3 WriteReg 4: Src Src LU Zero LUResult Write + PC

More information

3. (2) What is the difference between fixed and hybrid instructions?

3. (2) What is the difference between fixed and hybrid instructions? 1. (2 pts) What is a "balanced" pipeline? 2. (2 pts) What are the two main ways to define performance? 3. (2) What is the difference between fixed and hybrid instructions? 4. (2 pts) Clock rates have grown

More information

Lecture 5: Arithmetic

Lecture 5: Arithmetic Lecture 5: Arithmetic COS / ELE 375 Computer Architecture and Organization Princeton University Fall 2015 Prof. David August 1 5 Binary Representation of Integers Two physical states: call these 1 and

More information

Computer Architecture

Computer Architecture Computer Architecture QtSpim, a Mips simulator S. Coudert and R. Pacalet January 4, 2018..................... Memory Mapping 0xFFFF000C 0xFFFF0008 0xFFFF0004 0xffff0000 0x90000000 0x80000000 0x7ffff4d4

More information

On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work

On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work Lab 5 : Linking Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work 1 Objective The main objective of this lab is to experiment

More information

4. (3) What do we mean when we say something is an N-operand machine?

4. (3) What do we mean when we say something is an N-operand machine? 1. (2) What are the two main ways to define performance? 2. (2) When dealing with control hazards, a prediction is not enough - what else is necessary in order to eliminate stalls? 3. (3) What is an "unbalanced"

More information

Designing MIPS Processor

Designing MIPS Processor CSE 675.: Introdction to Compter Architectre Designing IPS Processor (lti-cycle) Presentation H Reading Assignment: 5.5,5.6 lti-cycle Design Principles Break p eection of each instrction into steps. The

More information

Lecture 13: Sequential Circuits, FSM

Lecture 13: Sequential Circuits, FSM Lecture 13: Sequential Circuits, FSM Today s topics: Sequential circuits Finite state machines 1 Clocks A microprocessor is composed of many different circuits that are operating simultaneously if each

More information

Design. Dr. A. Sahu. Indian Institute of Technology Guwahati

Design. Dr. A. Sahu. Indian Institute of Technology Guwahati CS222: Processor Design: Multi Cycle Design Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati Mid Semester Exam Multi Cycle design Outline Clock periods in single cycle and

More information

Computer Architecture ELEC2401 & ELEC3441

Computer Architecture ELEC2401 & ELEC3441 Last Time Pipeline Hazard Computer Architecture ELEC2401 & ELEC3441 Lecture 8 Pipelining (3) Dr. Hayden Kwok-Hay So Department of Electrical and Electronic Engineering Structural Hazard Hazard Control

More information

CPU DESIGN The Single-Cycle Implementation

CPU DESIGN The Single-Cycle Implementation 22 ompter Organization Seqential vs. ombinational ircits Digital circits can be classified into two categories: DESIGN The Single-ycle Implementation. ombinational ircits: m, 2. Seqential ircits: flip-flops,

More information

1. (2 )Clock rates have grown by a factor of 1000 while power consumed has only grown by a factor of 30. How was this accomplished?

1. (2 )Clock rates have grown by a factor of 1000 while power consumed has only grown by a factor of 30. How was this accomplished? 1. (2 )Clock rates have grown by a factor of 1000 while power consumed has only grown by a factor of 30. How was this accomplished? 2. (2 )What are the two main ways to define performance? 3. (2 )What

More information

[2] Predicting the direction of a branch is not enough. What else is necessary?

[2] Predicting the direction of a branch is not enough. What else is necessary? [2] When we talk about the number of operands in an instruction (a 1-operand or a 2-operand instruction, for example), what do we mean? [2] What are the two main ways to define performance? [2] Predicting

More information

M1 a. So there are 4 cases from the total 16.

M1 a. So there are 4 cases from the total 16. M1 a. Remember that overflow is defined as the result of the operation making no sense, which in 2's complement representa tion is equivalent to the mathematical result not fitting in the format. if any

More information

[2] Predicting the direction of a branch is not enough. What else is necessary?

[2] Predicting the direction of a branch is not enough. What else is necessary? [2] What are the two main ways to define performance? [2] Predicting the direction of a branch is not enough. What else is necessary? [2] The power consumed by a chip has increased over time, but the clock

More information

Processor Design & ALU Design

Processor Design & ALU Design 3/8/2 Processor Design A. Sahu CSE, IIT Guwahati Please be updated with http://jatinga.iitg.ernet.in/~asahu/c22/ Outline Components of CPU Register, Multiplexor, Decoder, / Adder, substractor, Varity of

More information

Lecture 12: Pipelined Implementations: Control Hazards and Resolutions

Lecture 12: Pipelined Implementations: Control Hazards and Resolutions 18-447 Lectre 12: Pipelined Implementations: Control Hazards and Resoltions S 09 L12-1 James C. Hoe Dept of ECE, CU arch 2, 2009 Annoncements: Spring break net week!! Project 2 de the week after spring

More information

Performance Evaluation of a Reconfigurable Instruction Set Processor

Performance Evaluation of a Reconfigurable Instruction Set Processor 九州大学学術情報リポジトリ Kyushu University Institutional Repository Performance Evaluation of a Reconfigurable Instruction Set Processor Mehdipour, Farhad Faculty of Information Science and Electrical Engineering,

More information

Instruction register. Data. Registers. Register # Memory data register

Instruction register. Data. Registers. Register # Memory data register Where we are headed Single Cycle Problems: what if we had a more complicated instrction like floating point? wastefl of area One Soltion: se a smaller cycle time have different instrctions take different

More information

ICS 233 Computer Architecture & Assembly Language

ICS 233 Computer Architecture & Assembly Language ICS 233 Computer Architecture & Assembly Language Assignment 6 Solution 1. Identify all of the RAW data dependencies in the following code. Which dependencies are data hazards that will be resolved by

More information

Formal Verification of Systems-on-Chip

Formal Verification of Systems-on-Chip Formal Verification of Systems-on-Chip Wolfgang Kunz Department of Electrical & Computer Engineering University of Kaiserslautern, Germany Slide 1 Industrial Experiences Formal verification of Systems-on-Chip

More information

CS61C : Machine Structures

CS61C : Machine Structures CS 61C L15 Blocks (1) inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks Outline CL Blocks Latches & Flip Flops A Closer Look 2005-07-14 Andy Carle CS

More information

EECS 270 Midterm Exam 2 Fall 2009

EECS 270 Midterm Exam 2 Fall 2009 EECS 270 Midterm Exam 2 Fall 2009 Name: unique name: UMID: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1&2

More information

CS61C : Machine Structures

CS61C : Machine Structures inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine Structures Lecture #15: Combinational Logic Blocks 2005-07-14 CS 61C L15 Blocks (1) Andy Carle Outline CL Blocks Latches & Flip Flops A Closer Look CS

More information

Computer Architecture Lecture 5: ISA Wrap-Up and Single-Cycle Microarchitectures

Computer Architecture Lecture 5: ISA Wrap-Up and Single-Cycle Microarchitectures 8-447 Compter Architectre Lectre 5: ISA Wrap-Up and Single-Cycle icroarchitectres Prof. Onr tl Carnegie ellon University Spring 22, /25/22 Homework Was de Wednesday! 34 received 2 Reminder: Homeworks for

More information

CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh

CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Sangyeun Cho. Computer Science Department University of Pittsburgh CS/COE54: Introduction to Computer Architecture Logic Design Review Sangyeun Cho Computer Science Department Logic design? Digital hardware is implemented by way of logic design Digital circuits process

More information

Control. Control. the ALU. ALU control signals 11/4/14. Next: control. We built the instrument. Now we read music and play it...

Control. Control. the ALU. ALU control signals 11/4/14. Next: control. We built the instrument. Now we read music and play it... // CS 2, Fall 2! CS 2, Fall 2! We built the instrument. Now we read music and play it... A simple implementa/on uc/on uct r r 2 Write r Src Src Extend 6 Mem Next: path 7-2 CS 2, Fall 2! signals CS 2, Fall

More information

Formal Verification of Systems-on-Chip Industrial Practices

Formal Verification of Systems-on-Chip Industrial Practices Formal Verification of Systems-on-Chip Industrial Practices Wolfgang Kunz Department of Electrical & Computer Engineering University of Kaiserslautern, Germany Slide 1 Industrial Experiences Formal verification

More information

CHAPTER log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C * 9-4.* (Errata: Delete 1 after problem number) 9-5.

CHAPTER log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C * 9-4.* (Errata: Delete 1 after problem number) 9-5. CHPTER 9 2008 Pearson Education, Inc. 9-. log 2 64 = 6 lines/mux or decoder 9-2.* C = C 8 V = C 8 C 7 Z = F 7 + F 6 + F 5 + F 4 + F 3 + F 2 + F + F 0 N = F 7 9-3.* = S + S = S + S S S S0 C in C 0 dder

More information

CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015

CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015 CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015 Name of the person on your left : Name of the person on your right: 1. 20 points 2. 20 points 3. 20 points 4. 15 points 5. 15 points 6. 10

More information

Simple Instruction-Pipelining. Pipelined Harvard Datapath

Simple Instruction-Pipelining. Pipelined Harvard Datapath 6.823, L8--1 Simple ruction-pipelining Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Pipelined Harvard path 6.823, L8--2. I fetch decode & eg-fetch execute memory Clock period

More information

ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H Lipasti. Fall 2010 University i of Wisconsin-Madison

ECE/CS 552: Introduction To Computer Architecture 1. Instructor:Mikko H Lipasti. Fall 2010 University i of Wisconsin-Madison ECE/CS 552: Arithmetic I Instructor:Mikko H Lipasti Fall 2010 Univsity i of Wisconsin-Madison i Lecture notes partially based on set created by Mark Hill. Basic Arithmetic and the ALU Numb representations:

More information

CS/COE0447: Computer Organization

CS/COE0447: Computer Organization CS/COE0447: Computer Organization and Assembly Language Logic Design Review Sangyeun Cho Dept. of Computer Science Logic design? Digital hardware is implemented by way of logic design Digital circuits

More information

Pipelined Datapath. Reading. Sections Practice Problems: 1, 3, 8, 12 (2) Lecture notes from MKP, H. H. Lee and S.

Pipelined Datapath. Reading. Sections Practice Problems: 1, 3, 8, 12 (2) Lecture notes from MKP, H. H. Lee and S. Pipelined Datapath Lectre notes from KP, H. H. Lee and S. Yalamanchili Sections 4.5 4. Practice Problems:, 3, 8, 2 Reading (2) Pipeline Performance Assme time for stages is v ps for register read or write

More information

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design

CMPEN 411 VLSI Digital Circuits Spring Lecture 19: Adder Design CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 19: Adder Design [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp11 CMPEN 411 L19

More information

ECE 3401 Lecture 23. Pipeline Design. State Table for 2-Cycle Instructions. Control Unit. ISA: Instruction Specifications (for reference)

ECE 3401 Lecture 23. Pipeline Design. State Table for 2-Cycle Instructions. Control Unit. ISA: Instruction Specifications (for reference) ECE 3401 Lecture 23 Pipeline Design Control State Register Combinational Control Logic New/ Modified Control Word ISA: Instruction Specifications (for reference) P C P C + 1 I N F I R M [ P C ] E X 0 PC

More information

Goals for Performance Lecture

Goals for Performance Lecture Goals for Performance Lecture Understand performance, speedup, throughput, latency Relationship between cycle time, cycles/instruction (CPI), number of instructions (the performance equation) Amdahl s

More information

Logic design? Transistor as a switch. Layered design approach. CS/COE1541: Introduction to Computer Architecture. Logic Design Review.

Logic design? Transistor as a switch. Layered design approach. CS/COE1541: Introduction to Computer Architecture. Logic Design Review. Logic design? CS/COE54: Introduction to Computer rchitecture Digital hardware is implemented by way of logic design Digital circuits process and produce two discrete values: and Example: -bit full adder

More information

CS/COE0447: Computer Organization

CS/COE0447: Computer Organization Logic design? CS/COE0447: Computer Organization and Assembly Language Logic Design Review Digital hardware is implemented by way of logic design Digital circuits process and produce two discrete values:

More information

CSE140: Components and Design Techniques for Digital Systems. Introduction. Prof. Tajana Simunic Rosing

CSE140: Components and Design Techniques for Digital Systems. Introduction. Prof. Tajana Simunic Rosing CSE4: Components and Design Techniques for Digital Systems Introduction Prof. Tajana Simunic Rosing Welcome to CSE 4! Instructor: Tajana Simunic Rosing Email: tajana.teach.ucsd@gmail.com; please put CSE4

More information

Fig. 7-6 Single Bus versus Dedicated Multiplexers

Fig. 7-6 Single Bus versus Dedicated Multiplexers 7- Select SSS2 LLL2 LLL2 S 2 to MUX R R Select S 2 to MUX R S S 3 to MUX 2 us R S 2 to MUX R2 R2 (a) Dedicated multiplexers (b) Sigle us Fig. 7-6 Sigle us versus Dedicated Multiplexers 2 Pretice Hall,

More information

CSE Computer Architecture I

CSE Computer Architecture I Single cycle Conrol Implemenaion CSE 332 Compuer Archiecure I l x I Lecure 7 - uli Cycle achines i i [ ] I I r l ichael Niemier Deparmen of Compuer Science and Engineering I ] i X.S. Hu 5- X.S. Hu 5-2

More information

Combinatorial Logic Design Multiplexers and ALUs CS 64: Computer Organization and Design Logic Lecture #13

Combinatorial Logic Design Multiplexers and ALUs CS 64: Computer Organization and Design Logic Lecture #13 Combinatorial Logic Design Multiplexers and ALUs CS 64: Computer Organization and Design Logic Lecture #13 Ziad Matni Dept. of Computer Science, UCSB Administrative Re: Midterm Exam #2 Graded! 5/22/18

More information

In 1980, the yield = 48% and the Die Area = 0.16 from figure In 1992, the yield = 48% and the Die Area = 0.97 from figure 1.31.

In 1980, the yield = 48% and the Die Area = 0.16 from figure In 1992, the yield = 48% and the Die Area = 0.97 from figure 1.31. CS152 Homework 1 Solutions Spring 2004 1.51 Yield = 1 / ((1 + (Defects per area * Die Area / 2))^2) Thus, if die area increases, defects per area must decrease. 1.52 Solving the yield equation for Defects

More information

Load. Load. Load 1 0 MUX B. MB select. Bus A. A B n H select S 2:0 C S. G select 4 V C N Z. unit (ALU) G. Zero Detect.

Load. Load. Load 1 0 MUX B. MB select. Bus A. A B n H select S 2:0 C S. G select 4 V C N Z. unit (ALU) G. Zero Detect. 9- Write D data Load eable A address A select B address B select Load R 2 2 Load Load R R2 UX 2 3 UX 2 3 2 3 Decoder D address 2 Costat i Destiatio select 28 Pearso Educatio, Ic.. orris ao & Charles R.

More information

CMP N 301 Computer Architecture. Appendix C

CMP N 301 Computer Architecture. Appendix C CMP N 301 Computer Architecture Appendix C Outline Introduction Pipelining Hazards Pipelining Implementation Exception Handling Advanced Issues (Dynamic Scheduling, Out of order Issue, Superscalar, etc)

More information

Instructions. An 8.5 x 11 Cheat Sheet may also be used as an aid for this test. MUST be original handwriting.

Instructions. An 8.5 x 11 Cheat Sheet may also be used as an aid for this test. MUST be original handwriting. ID: B CSE 2021 Computer Orgniztion Midterm Test (Fll 2009) Instrutions This is losed ook, 80 minutes exm. The MIPS referene sheet my e used s n id for this test. An 8.5 x 11 Chet Sheet my lso e used s

More information

CS/COE0447: Computer Organization and Assembly Language

CS/COE0447: Computer Organization and Assembly Language CS/COE0447: Computer Organization and Assembly Language Logic Design Introduction (Brief?) Appendix B: The Basics of Logic Design Dept. of Computer Science Logic design? Digital hardware is implemented

More information

Review for Final Exam

Review for Final Exam CSE140: Components and Design Techniques for Digital Systems Review for Final Exam Mohsen Imani CAPE Please submit your evaluations!!!! RTL design Use the RTL design process to design a system that has

More information

Four Important Number Systems

Four Important Number Systems Four Important Number Systems System Why? Remarks Decimal Base 10: (10 fingers) Most used system Binary Base 2: On/Off systems 3-4 times more digits than decimal Octal Base 8: Shorthand notation for working

More information

ADD B,W,L s = Dn d = x x x x x x x x (Add) d = Dn s = x x x x x x x x x x x x

ADD B,W,L s = Dn d = x x x x x x x x (Add) d = Dn s = x x x x x x x x x x x x T ABLE C.4 68000 instruction set Addressing mode Mnemonic (Name) Size Addressing mo de Dn An ABCD B s = Dn d = x (Add BCD) s = d = x + d d(an,xi) Abs.W Abs.L d(pc) ADD B,W,L s = Dn d = x x x x x x x x

More information

Name: ID# a) Complete the state transition table for the aforementioned circuit

Name:   ID# a) Complete the state transition table for the aforementioned circuit UNIVERSITY OF CALIFORNIA Department of Electrical Engineering and Computer Sciences EECS150 Fall 2001 Prof. Subramanian Final Examination 1) You are to design a sequential circuit with two JK FFs A and

More information

Professor Fearing EECS150/Problem Set Solution Fall 2013 Due at 10 am, Thu. Oct. 3 (homework box under stairs)

Professor Fearing EECS150/Problem Set Solution Fall 2013 Due at 10 am, Thu. Oct. 3 (homework box under stairs) Professor Fearing EECS50/Problem Set Solution Fall 203 Due at 0 am, Thu. Oct. 3 (homework box under stairs). (25 pts) List Processor Timing. The list processor as discussed in lecture is described in RT

More information

Simple Instruction-Pipelining. Pipelined Harvard Datapath

Simple Instruction-Pipelining. Pipelined Harvard Datapath 6.823, L8--1 Simple ruction-pipelining Updated March 6, 2000 Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Pipelined Harvard path 6.823, L8--2. fetch decode & eg-fetch execute

More information

Hardware implementations of ECC

Hardware implementations of ECC Hardware implementations of ECC The University of Electro- Communications Introduction Public- key Cryptography (PKC) The most famous PKC is RSA and ECC Used for key agreement (Diffie- Hellman), digital

More information

mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 2 Dominique Thiébaut

mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 2 Dominique Thiébaut mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 2 Dominique Thiébaut dthiebaut@smith.edu Lab 1: Lessons Learned a0 b0 adder c0 S0 a1 b1 a0 b0 adder adder S1 S0 a31

More information

CPS 104 Computer Organization and Programming Lecture 11: Gates, Buses, Latches. Robert Wagner

CPS 104 Computer Organization and Programming Lecture 11: Gates, Buses, Latches. Robert Wagner CPS 4 Computer Organization and Programming Lecture : Gates, Buses, Latches. Robert Wagner CPS4 GBL. RW Fall 2 Overview of Today s Lecture: The MIPS ALU Shifter The Tristate driver Bus Interconnections

More information

Figure 4.9 MARIE s Datapath

Figure 4.9 MARIE s Datapath Term Control Word Microoperation Hardwired Control Microprogrammed Control Discussion A set of signals that executes a microoperation. A register transfer or other operation that the CPU can execute in

More information

CprE 281: Digital Logic

CprE 281: Digital Logic CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Simple Processor CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Digital

More information

Simple Instruction-Pipelining (cont.) Pipelining Jumps

Simple Instruction-Pipelining (cont.) Pipelining Jumps 6.823, L9--1 Simple ruction-pipelining (cont.) + Interrupts Updated March 6, 2000 Laboratory for Computer Science M.I.T. http://www.csg.lcs.mit.edu/6.823 Src1 ( j / ~j ) Src2 ( / Ind) Pipelining Jumps

More information

Linear Feedback Shift Registers (LFSRs) 4-bit LFSR

Linear Feedback Shift Registers (LFSRs) 4-bit LFSR Linear Feedback Shift Registers (LFSRs) These are n-bit counters exhibiting pseudo-random behavior. Built from simple shift-registers with a small number of xor gates. Used for: random number generation

More information

Exam 1. March 12th, CS525 - Midterm Exam Solutions

Exam 1. March 12th, CS525 - Midterm Exam Solutions Name CWID Exam 1 March 12th, 2014 CS525 - Midterm Exam s Please leave this empty! 1 2 3 4 5 Sum Things that you are not allowed to use Personal notes Textbook Printed lecture notes Phone The exam is 90

More information

Unit 1 - Digital System Design

Unit 1 - Digital System Design LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-37: Computer Hardare esign Winter 8 IGITAL SYSTM MOL FSM (CONTROL) + ATAPATH CIRCUIT Unit - igital System esign ATAPATH CIRCUIT Inputs clock FINIT

More information

A crash course in Digital Logic

A crash course in Digital Logic crash course in Digital Logic Computer rchitecture 1DT016 distance Fall 2017 http://xyx.se/1dt016/index.php Per Foyer Mail: per.foyer@it.uu.se Per.Foyer@it.uu.se 2017 1 We start from here Gates Flip-flops

More information

/ : Computer Architecture and Design

/ : Computer Architecture and Design 16.482 / 16.561: Computer Architecture and Design Summer 2015 Homework #5 Solution 1. Dynamic scheduling (30 points) Given the loop below: DADDI R3, R0, #4 outer: DADDI R2, R1, #32 inner: L.D F0, 0(R1)

More information

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO

BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO UN IVERSIT Y O F CA LIFO RNI A AT BERKELEY BER KELEY D AV IS IR VINE LOS AN GELES RIVERS IDE SAN D IEGO S AN FRANCISCO SAN TA BARBA RA S AN TA CRUZ De p a r tm en t of Ele ctr i ca l En gin e e rin g a

More information

EECS150 - Digital Design Lecture 27 - misc2

EECS150 - Digital Design Lecture 27 - misc2 EECS150 - Digital Design Lecture 27 - misc2 May 1, 2002 John Wawrzynek Spring 2002 EECS150 - Lec27-misc2 Page 1 Outline Linear Feedback Shift Registers Theory and practice Simple hardware division algorithms

More information