Instruction register. Data. Registers. Register # Memory data register

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1 Where we are headed Single Cycle Problems: what if we had a more complicated instrction like floating point? wastefl of area One Soltion: se a smaller cycle time have different instrctions take different nmbers of cycles a mlticycle path: PC Address emory Data or emory Data Register # Registers Register # Register # A B ALU ALUOt lticycle Approach We will be resing fnctional nits ALU sed to compte address and to increment PC emory sed for instrction and Or control signals will not be determined solely by instrction e.g., what shold the ALU do for a sbtract instrction? We ll se a finite state machine for control

2 Review: finite state machines Finite state machines: a set of states and net state fnction (determined by crrent state and the inpt) otpt fnction (determined by crrent state and possibly inpt) Crrent state Net-state fnction Net state Inpts Clock Otpt fnction Otpts We ll se a oore machine (otpt based only on crrent state) Review: finite state machines Eample: B. A friend wold like yo to bild an electronic eye for se as a fake secrity device. The device consists of three lights lined p in a row, controlled by the otpts Left, iddle, and Right, which, if asserted, indicate that a light shold be on. Only one light is on at a time, and the light moves from left to right and then from right to left, ths scaring away thieves who believe that the device is monitoring their activity. Draw the graphical representation for the finite state machine sed to specify the electronic eye. Note that the rate of the eye s movement will be controlled by the clock speed (which shold not be too great) and that there are essentially no inpts.

3 lticycle Approach Break p the instrctions into steps, each step takes a cycle balance the amont of work to be done restrict each cycle to se only one major fnctional nit At the end of a cycle store vales for se in later cycles (easiest thing to do) introdce additional internal s PC Address emory emdata [5 ] [ 6] [5 ] [5 ] emory [5 ] 6 Registers Sign etend Shift left A B Zero ALU ALU reslt ALUOt 5 lticycle Datapath with control signals IorD e m R e ad e m W rite IR W rite R eg D st R eg W r ite A L U S rca P C A d dr e ss em o ry e md a ta W rite da ta Instr ctio n [ 5 ] Instr ctio n [ 6 ] Instr ctio n [ 5 ] In str ctio n re g is ter In str ction [ 5 ] R e a d R e a d R e a d da ta R e g iste rs W rite R e a d r eg iste r da ta W rite d a ta A B Z e ro A L U A L U res lt A LU O t In str ctio n [ 5 ] e m o ry d a ta r eg is te r 6 S ig n e ten d S h ift le ft A L U c o ntro l In str ctio n [5 ] e m to R e g A L U S r cb A L U O p 6

4 lticycle Datapath & Control Cond PCSorce IorD em em emtoreg IR Otpts Control Op [5 ] ALUOp ALUSrcB ALUSrcA Reg RegDst PC Address emory emdata [-6] [5 ] [ 6] [5 ] [5 ] [5 ] 6 8 Shift [5 ] Registers A B left PC [-8] Zero ALU ALU reslt Jmp address [-] ALUOt emory 6 Sign etend Shift left ALU control [5 ] 7 Five Eection Steps Fetch Decode and Register Fetch Eection, emory Address Comptation, or Branch Completion emory Access or R-type instrction completion -back step INSTRUCTIONS TAKE FRO - 5 CYCLES! 8

5 High level view of finite state machine control Start fetch/decode and fetch (Figre 5.7) emory access instrctions (Figre 5.8) R-type instrctions (Figre 5.9) Branch instrction (Figre 5.) Jmp instrction (Figre 5.) 9 Step : Fetch Use PC to get instrction and pt it in the Register. Increment the PC by and pt the reslt back in the PC. Can be described sccinctly sing RTL "Register-Transfer Langage" IR = emory[pc]; PC = PC + ; Can we figre ot the vales of the control signals? What is the advantage of pdating the PC now?

6 Step : Decode and Register Fetch s rs and rt in case we need them Compte the branch address in case the instrction is a branch RTL: A = Reg[IR[5-]]; B = Reg[IR[-6]]; ALUOt = PC + (sign-etend(ir[5-]) << ); We aren't setting any control lines based on the instrction type (we are bsy "decoding" it in or control logic) Fetch & Decode Start (Op = 'LW') or (Op = 'SW') fetch em ALUSrcA = IorD = IR ALUSrcB = ALUOp = PCSorce = (Op = R-type) (Op = 'BEQ') decode/ Register fetch ALUSrcA = ALUSrcB = ALUOp = (Op = 'JP') emory reference FS (Figre 5.8) R-type FS (Figre 5.9) Branch FS (Figre 5.) Jmp FS (Figre 5.)

7 Step (instrction dependent) ALU is performing one of three fnctions, based on instrction type emory Reference: ALUOt = A + sign-etend(ir[5-]); R-type: ALUOt = A op B; Branch: if (A==B) PC = ALUOt; Step (R-type or memory-access) Loads and stores access memory DR = emory[aluot]; or emory[aluot] = B; R-type instrctions finish Reg[IR[5-]] = ALUOt; The write actally takes place at the end of the cycle on the edge

8 -back step Reg[IR[-6]]= DR; What abot all the other instrctions? 5 Finite state machine for memory access instrctions From state ALUSrcA = ALUSrcB = ALUOp = (Op = 'LW') or (Op = 'SW') emory address comptation (Op = 'LW') emory access (Op = 'SW') 5 emory access em IorD = em IorD = -back step Reg emtoreg = RegDst = To state (Figre 5.7) 6

9 Finite state machine for R-format instrctions From state (Op = R-type) 6 Eection ALUSrcA = ALUSrcB = ALUOp = 7 R-type completion RegDst = Reg emtoreg = To state (Figre 5.7) 7 Finite state machine for branch instrction 8 From state (Op = 'BEQ') ALUSrcA = ALUSrcB = ALUOp = Cond PCSorce = Branch completion To state (Figre 5.7) 8

10 Finite State achine for jmp From state (Op = 'J') 9 Jmp completion PCSorce = To state (Figre 5.7) 9 Smmary: Step name fetch decode/ fetch Action for R-type instrctions Action for memory-reference Action for instrctions branches IR = emory[pc] PC = PC + A = Reg [IR[5-]] B = Reg [IR[-6]] ALUOt = PC + (sign-etend (IR[5-]) << ) Action for jmps Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then PC = PC [-8] II comptation, branch/ (IR[5-]) PC = ALUOt (IR[5-]<<) jmp completion emory access or R-type Reg [IR[5-]] = Load: DR = emory[aluot] completion ALUOt or Store: emory [ALUOt] = B emory read completion Load: Reg[IR[-6]] = DR

11 Complete Finite State achine emory address comptation decode/ fetch fetch em ALUSrcA = IorD = ALUSrcA = Start IR ALUSrcB = ALUSrcB = ALUOp = ALUOp = PCSorce = Branch Eection completion Jmp completion ALUSrcA = ALUSrcA = ALUSrcA = ALUSrcB = ALUSrcB = ALUSrcB = ALUOp = ALUOp = PCSorce = ALUOp = Cond PCSorce = (Op = 'LW') or (Op = 'SW') (Op = R-type) (Op = 'BE Q') (Op = 'J') (Op = 'LW') emory access (Op = 'SW') 5 emory access 7 R-type completion em IorD = em IorD = RegDst = Reg emtoreg = -back step RegDst = Reg emtoreg = Simple Qestions How many cycles will it take to eecte this code? lw $t, ($t) lw $t, ($t) beq $t, $t, Label add $t5, $t, $t sw $t5, 8($t) Label:... #assme not What is going on dring the 8th cycle of eection? In what cycle does the actal addition of $t and $t takes place?

12 Eceptions Hardest part of control is to implement eceptions & interrpts Type of event From where? IPS terminology I/O device reqest Eternal Interrpt Invoke the operating system from ser program Arithmetic overflow Internal Internal Eception Eception Using an ndefined instrction Hardware malfnctions Internal Internal or Eternal Eception Eception or interrpt How are eceptions handled? In or design, we will consider two types of eceptions Arithmetic overflow Eection of an ndefined instrction Actions on eception Save address of offending instrction in the Eception Program Conter (EPC) Transfer control to the operating system at a pre-specified address (eception handler) OS then takes appropriate action

13 Eception handling For the OS to take appropriate action, it mst know the reason for the eception Two ways to commnicate reason to OS Have a Stats which holds a field that indicates the reason for the eception Vectored interrpts Address to which control is transferred depends pon the case of the eception IPS ses first method above; it has a called Case (in addition to the EPC ) 5 Datapath & Control with spport for eceptions Cond IorD em em emtoreg IR Otpts Control Op [5 ] Case IntCase E PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst PC Address emory emdata [-6] [5 ] [ 6] [5 ] [5 ] emory [5 ] 6 8 Shift [5 ] 6 Registers Sign etend Shift left A B ALU control left PC [-8] ALU Zero ALU reslt Jmp address [-] CO ALUOt EPC Case [5 ] 6

14 Eception Handling Datapath additions EPC, Case (for ndefined instrction, Case =, arithmetic overflow Case = ) Control Signals E, Case IntCase (sets the Case ) PCSrc has to be modified so that one of its sorces is the OS entry point Three steps. Case. EPC = PC (Have to se ALU, so need to epand mltipleors for ALUSrcA and ALUSrcB. PC 7 Datapath & Control with spport for eceptions Cond IorD em em emtoreg IR Otpts Control Op [5 ] Case IntCase E PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst PC Address emory emdata [-6] [5 ] [ 6] [5 ] [5 ] emory [5 ] 6 8 Shift [5 ] 6 Registers Sign etend Shift left A B ALU control left PC [-8] ALU Zero ALU reslt Jmp address [-] CO ALUOt EPC Case [5 ] 8

15 States for handling eceptions IntCase = Case ALUSrcA = ALUSrcB = ALUOp = E PC++Sorce = IntCase = Case ALUSrcA = ALUSrcB = ALUOp = E PCSorce = PCSorce = To state to begin net instrction 9 Complete FS inclding spport for eceptions emory address comptation ALUSrcA = ALUSrcB = ALUOp = Start (Op = 'LW') or (Op = 'SW') 6 fetch em ALUSrcA = IorD = IR ALUSrcB = ALUOp = PCSorce = Eection ALUSrcA = ALUSrcB = ALUOp = 8 (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = Cond PCSorce = (Op = 'BEQ') decode/ Register fetch 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') (Op = other) Jmp completion PCSorce = (Op = 'LW') (Op = 'SW') emory access 5 em IorD = emory access R-type completion IntCase = 7 Case RegDst = ALUSrcA = em Reg Overflow ALUSrcB = IorD = emtoreg = ALUOp = E PCSorce = IntCase = Case ALUSrcA = ALUSrcB = ALUOp = E PCSorce = -back step Overflow Reg emtoreg = RegDst =

16 Implementing the Control Vale of control signals is dependent pon: what instrction is being eected which step is being performed Use the information we ve acclmated to specify a finite state machine specify the finite state machine graphically, or se microprogramming Implementation can be derived from specification Graphical Specification of FS emory address comptation A LUSrcA = ALUSrcB = ALUOp = decode/ fetch re gister fetch em Re ad ALUSrcA = IorD = ALUSrcA = Start IR ALUSrcB = ALUSrcB = ALUOp = ALUOp = PC Sorce = (Op = 'LW ') or (Op = 'SW ') (Op = R-type) Branch Eection co m pletion (Op = 'BEQ') Jmp comp letio n AL USrcA = ALU SrcA = ALUSrcB = ALUSrcB = ALUOp = PCSorce = ALUOp = PC Co nd PC So rce = (Op = 'J') (Op = 'LW') emory access (Op = 'SW') 5 em ory access 7 R-type completion em IorD = em IorD = RegDst = Reg em toreg = -back step Reg Dst = Reg emtoreg =

17 Finite State achine for Control Implementation: Control logic Inpts Otpts Cond IorD em em IR em toreg PCSorce ALUOp ALUSrcB ALUSrcA Reg RegDst NS NS NS NS Op5 Op Op Op Op Op S S S S opcode field State PLA Implementation If I picked a horizontal or vertical line cold yo eplain it? Op5 Op Op Op Op Op S S S S Cond IorD em em IR emtoreg PCSorce PCSorce ALUOp ALUOp ALUSrcB ALUSrcB ALUSrcA Reg RegDst NS NS NS NS

18 RO Implementation RO = " Only emory" vales of memory locations are fied ahead of time A RO can be sed to implement a trth table if the address is m-bits, we can address m entries in the RO. or otpts are the bits of that the address points to. m n m is the "height", and n is the "width" 5 RO Implementation How many inpts are there? 6 bits for opcode, bits for state = address lines (i.e., = different addresses) How many otpts are there? 6 path-control otpts, state bits = otpts RO is = K bits (and a rather nsal size) Rather wastefl, since for lots of the entries, the otpts are the same i.e., opcode is often ignored 6

19 RO vs PLA Break p the table into two parts state bits tell yo the 6 otpts, 6 bits of RO bits tell yo the net state bits, bits of RO Total:.K bits of RO PLA is mch smaller can share prodct terms only need entries that prodce an active otpt can take into accont don't cares Size is (#inpts? #prodct-terms) + (#otpts? #prodct-terms) For this eample = (7)+(7) = 6 PLA cells PLA cells sally abot the size of a RO cell (slightly bigger) 7 The Big Pictre Initial representation Finite state diagram icroprogram Seqencing control Eplicit net state fnction icroprogram conter + dispatch ROS Logic representation Logic eqations Trth tables Implementation techniqe Programmable logic array only memory 8