Computer Architecture Lecture 5: ISA Wrap-Up and Single-Cycle Microarchitectures

Transcription

1 8-447 Compter Architectre Lectre 5: ISA Wrap-Up and Single-Cycle icroarchitectres Prof. Onr tl Carnegie ellon University Spring 22, /25/22

2 Homework Was de Wednesday! 34 received 2

3 Reminder: Homeworks for Net Two Weeks Homework De onday Jan 28, right before lectre Trn in via AFS (hand-in directories) IPS warmp, ISA concepts, basic performance evalation Homework 2 Will be assigned net week. Stay tned 3

4 Reminder: Lab Assignment De net Friday (Feb ), at the end of Friday lab A fnctional C-level simlator for a sbset of the IPS ISA Stdy the IPS ISA Ttorial TAs will cover this in Lab Sessions this week 4

5 A Note on Lab and Homework Dates Intended dates are on yor syllabs a=syllabs mtl-s3.pdf We will try to stick to them. Last year s website can provide yo a good lookahead into what is coming res 5

6 Readings for Net Lectre P&P, Revised Appendi C icroarchitectre of the LC-3b Appendi A (LC-3b ISA) will be sefl in following this P&H, Appendi D apping Control to Hardware Optional arice Wilkes, The Best Way to Design an Atomatic Calclating achine, anchester Univ. Compter Inagral Conf., 95. 6

7 Review of Last Lectre: ISA Tradeoffs Comple vs. simple instrctions: concept of semantic gap Use of translation to change the tradeoffs Fied vs. variable length, niform vs. non-niform decode Nmber of registers What is the benefit of translating comple instrctions to simple instrctions before eecting them? In hardware (a la Intel, AD)? In software (a la Transmeta)? Which ISA is easier to etend: fied length or variable length? How can yo have a variable length, niform decode ISA? 7

8 Review: 86 vs. Alpha Instrction Formats 86: Alpha: 8

9 Review: ISA-level Tradeoffs: Nmber of Registers Affects: Nmber of bits sed for encoding register address Nmber of vales kept in fast storage (register file) (arch) Size, access time, power consmption of register file Large nmber of registers: + Enables better register allocation (and optimizations) by compiler fewer saves/restores -- Larger instrction size -- Larger register file size 9

10 ISA-level Tradeoffs: Addressing odes Addressing mode specifies how to obtain an operand of an instrction Register Immediate emory (displacement, register indirect, indeed, absolte, memory indirect, atoincrement, atodecrement, ) ore modes: + help better spport programming constrcts (arrays, pointerbased accesses) -- make it harder for the architect to design -- too many choices for the compiler? any ways to do the same thing complicates compiler design Wlf, Compilers and Compter Architectre, IEEE Compter 98

11 86 vs. Alpha Instrction Formats 86: Alpha:

12 86 register indirect absolte register + displacement register 2

13 86 indeed (base + inde) scaled (base + inde*4) 3

14 X86 SIB-D Addressing ode 86 anal Vol., page see corse resorces on website Also, see Section and

15 X86 anal: Sggested Uses of Addressing odes 86 anal Vol., page see corse resorces on website Also, see Section and

16 X86 anal: Sggested Uses of Addressing odes 86 anal Vol., page see corse resorces on website Also, see Section and

17 Other Eample ISA-level Tradeoffs Condition codes vs. not VLIW vs. single instrction Precise vs. imprecise eceptions Virtal memory vs. not Unaligned access vs. not Hardware interlocks vs. software-garanteed interlocking Software vs. hardware managed page falt handling Cache coherence (hardware vs. software) 7

18 Back to Programmer vs. (icro)architect any ISA featres designed to aid programmers Bt, complicate the hardware designer s job Virtal memory vs. overlay programming Shold the programmer be concerned abot the size of code blocks fitting physical memory? Addressing modes Unaligned memory access Compile/programmer needs to align data 8

19 IPS: Aligned Access SB byte-3 byte-2 byte- byte- byte-7 byte-6 byte-5 byte-4 LSB LW/SW alignment restriction: 4-byte word-alignment not designed to fetch memory bytes not within a word bondary not designed to rotate naligned bytes into registers Provide separate opcodes for the infreqent case A B C D LWL rd 6(r) LWR rd 3(r) byte-6 byte-5 byte-4 D byte-6 byte-5 byte-4 byte-3 LWL/LWR is slower Note LWL and LWR still fetch within word bondary 9

20 X86: Unaligned Access LD/ST instrctions atomatically align data that spans a word bondary Programmer/compiler does not need to worry abot where data is stored (whether or not in a word-aligned location) 2

21 X86: Unaligned Access 2

22 Aligned vs. Unaligned Access Pros of having no restrictions on alignment Cons of having no restrictions on alignment Filling in the above: an eercise for yo 22

23 Implementing the ISA: icroarchitectre Basics 23

24 How Does a achine Process Instrctions? What does processing an instrction mean? Remember the von Nemann model A = Architectral (programmer visible) state before an instrction is processed Process instrction A = Architectral (programmer visible) state after an instrction is processed Processing an instrction: Transforming A to A according to the ISA specification of the instrction 24

25 The Process instrction Step ISA specifies abstractly what A shold be, given an instrction and A It defines an abstract finite state machine where State = programmer-visible state Net-state logic = instrction eection specification From ISA point of view, there are no intermediate states between A and A dring instrction eection One state transition per instrction icroarchitectre implements how A is transformed to A There are many choices in implementation We can have programmer-invisible state to optimize the speed of instrction eection: mltiple state transitions per instrction Choice : A A (transform A to A in a single clock cycle) Choice 2: A A+S A+S2 A+S3 A (take mltiple clock cycles to transform A to A ) 25

26 A Very Basic Instrction Processing Engine Each instrction takes a single clock cycle to eecte Only combinational logic is sed to implement instrction eection No intermediate, programmer-invisible state pdates A = Architectral (programmer visible) state at the beginning of a clock cycle Process instrction in one clock cycle A = Architectral (programmer visible) state at the end of a clock cycle 26

27 A Very Basic Instrction Processing Engine Single-cycle machine Combinational Logic A Net Seqential Logic (State) A What is the clock cycle time determined by? What is the critical path of the combinational logic determined by? 27

28 Remember: Programmer Visible (Architectral) State [] [] [2] [3] [4] Registers - given special names in the ISA (as opposed to addresses) - general vs. special prpose [N-] emory array of storage locations indeed by an address Program Conter memory address of the crrent instrction Instrctions (and programs) specify how to transform the vales of programmer visible state 28

29 Single-cycle vs. lti-cycle achines Single-cycle machines Each instrction takes a single clock cycle All state pdates made at the end of an instrction s eection Big disadvantage: The slowest instrction determines cycle time long clock cycle time lti-cycle machines Instrction processing broken into mltiple cycles/stages State pdates can be made dring an instrction s eection Architectral state pdates made only at the end of an instrction s eection Advantage over single-cycle: The slowest stage determines cycle time Both single-cycle and mlti-cycle machines literally follow the von Nemann model at the microarchitectre level 29

30 Instrction Processing Cycle Instrctions are processed nder the direction of a control nit step by step. Instrction cycle: Seqence of steps to process an instrction Fndamentally, there are si phases: Fetch Decode Evalate Address Fetch Operands Eecte Store Reslt Not all instrctions reqire all si stages (see P&P Ch. 4) 3

31 Instrction Processing Cycle vs. achine Clock Cycle Single-cycle machine: All si phases of the instrction processing cycle take a single machine clock cycle to complete lti-cycle machine: All si phases of the instrction processing cycle can take mltiple machine clock cycles to complete In fact, each phase can take mltiple clock cycles to complete 3

32 Instrction Processing Viewed Another Way Instrctions transform Data (AS) to Data (AS ) This transformation is done by fnctional nits Units that operate on data These nits need to be told what to do to the data An instrction processing engine consists of two components Datapath: Consists of hardware elements that deal with and transform data signals fnctional nits that operate on data hardware strctres (e.g. wires and mes) that enable the flow of data into the fnctional nits and registers storage nits that store data (e.g., registers) Control logic: Consists of hardware elements that determine control signals, i.e., signals that specify what the datapath elements shold do to the data 32

33 Single-cycle vs. lti-cycle: Control & Data Single-cycle machine: Control signals are generated in the same clock cycle as data signals are operated on Everything related to an instrction happens in one clock cycle lti-cycle machine: Control signals needed in the net cycle can be generated in the previos cycle Latency of control processing can be overlapped with latency of datapath operation We will see the difference clearly in microprogrammed mlti-cycle microarchitectre 33

34 any Ways of Datapath and Control Design There are many ways of designing the data path and control logic Single-cycle, mlti-cycle, pipelined datapath and control Single-bs vs. mlti-bs datapaths See yor homework 2 qestion Hardwired/combinational vs. microcoded/microprogrammed control Control signals generated by combinational logic verss Control signals stored in a memory strctre Control signals and strctre depend on the datapath design 34

35 Flash-Forward: Performance Analysis Eection time of an instrction {CPI} {clock cycle time} Eection time of a program Sm over all instrctions [{CPI} {clock cycle time}] {# of instrctions} {Average CPI} {clock cycle time} Single cycle microarchitectre performance CPI = Clock cycle time = long lti-cycle microarchitectre performance CPI = different for each instrction Average CPI hopeflly small Clock cycle time = short Now, we have two degrees of freedom to optimize independently 35

36 A Single-Cycle icroarchitectre A Closer Look 36

37 Remember Single-cycle machine Combinational Logic AS Net Seqential Logic (State) AS 37

38 Let s Start with the State Elements Data and control inpts n P C In s tr c tio n o n r y R e g is te r n m b e rs A d d D a ta re g iste r d a ta 5 S m re g iste r 2 R e g is te rs re g iste r d a ta d a ta 2 R e g D a ta A L c tio n m e m o r y b. P ro g ra m c o n te r c. A d d e r a. R e g iste rs b e m In str c tio n a d d r e s s In str c tio n m e m o r y In s tr c tio n A d d re s s P C d a ta D a ta m e m o ry d a ta A d d S m 6 S ig n e te n d a. In str c tio n m e m o r y b. P ro g ra m c o n te r e m c. A d d e r **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] a. D a ta m e m o ry n it 38 b. S ig n -e te n

39 For Now, We Will Assme agic memory and register file Combinational read otpt of the read data port is a combinational fnction of the register file contents and the corresponding read select port Synchronos write the selected register is pdated on the positive edge clock transition when write enable is asserted Cannot affect read otpt in between clock edges Can affect read otpt at clock edges (bt who cares?) Single-cycle, synchronos memory Contrast this with memory that tells when the data is ready i.e., Ready bit: indicating the read or write is done 39

40 Instrction Processing 5 generic steps (P&H) IF Instrction fetch (IF) Instrction decode and register operand fetch (ID/RF) Eecte/Evalate memory address (EX/AG) emory operand fetch (E) Store/writeback reslt (WB) D a ta R e g is ter # WB P C A d d re s s In s tr c tio n R e gis te rs A L U In s tr c tion m e m ory ID/RF R e g is ter # R e g is ter # EX/AG A d dre s s D a ta m e m ory D ata E **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 4

41 What Is To Come: The Fll Datapath Instrction [25 ] S h ift Jm p address [3 ] left PCSrc =Jmp 4 A d d PC +4 [3 28] RegD st J m p B ra n ch S h ift le ft 2 A d d A LU re s lt PCSrc 2 =Br Taken Instrction [3 26] C o ntro l e m e m to R eg A L U O p e m ALU Src Reg P C ad d re ss In s trc tio n m e m or y In strc tio n [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] R ea d register R ea d da ta da ta register 2 R eg iste rs da ta 2 re giste r bcond Z e ro A L U A L U re s lt A d d re ss d ata D ata m e m o ry d ata Instrction [5 ] S ig n e te n d A L U co n tro l ALU operation In str ction [5 ] **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] JAL, JR, JALR omitted 4

42 Single-Cycle Datapath for Arithmetic and Logical Instrctions 42

43 R-Type ALU Instrctions Assembly (e.g., register-register signed addition) ADD rd reg rs reg rt reg achine encoding 6-bit rs 5-bit rt 5-bit rd 5-bit 5-bit ADD 6-bit R-type Semantics if E[PC] == ADD rd rs rt GPR[rd] GPR[rs] + GPR[rt] PC PC

44 ALU Datapath A d d 4 P C a d d re ss In s tr c tio n m e m o ry In s tr ctio n In str c tio n 25:2 2:6 5: re g is te r re g is te r 2 R e g is te rs re g is te r d a ta d a ta d a ta 2 3 A L U o p e ra tio n Z e ro A L U A L U re s lt R e g if E[PC] == ADD rd rs rt GPR[rd] GPR[rs] + GPR[rt] PC PC + 4 **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] IF ID EX E WB Combinational state pdate logic 44

45 I-Type ALU Instrctions Assembly (e.g., register-immediate signed additions) ADDI rt reg rs reg immediate 6 achine encoding ADDI 6-bit rs 5-bit rt 5-bit immediate 6-bit I-type Semantics if E[PC] == ADDI rt rs immediate GPR[rt] GPR[rs] + sign-etend (immediate) PC PC

46 Datapath for R and I-Type ALU Insts. A d d 4 P C a d d re ss In s tr c tio n m e m o ry In s tr ctio n 25:2 2:6 In s tr c tio n 5: RegDest isitype re g is te r re g is te r 2 R e g is te r s re g is te r d a ta R e g d a ta d a ta S ig n e te n d 3 A L U ALUSrc isitype A L U o p e r a tio n Z e r o A L U re s lt A d d re s s d a ta e m D a ta m e m o e m if E[PC] == ADDI rt rs immediate GPR[rt] GPR[rs] + sign-etend (immediate) PC PC + 4 **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] IF ID EX E WB Combinational state pdate logic 46

47 Single-Cycle Datapath for Data ovement Instrctions 47

48 Load Instrctions Assembly (e.g., load 4-byte word) LW rt reg offset 6 (base reg ) achine encoding LW 6-bit base 5-bit rt 5-bit offset 6-bit I-type Semantics if E[PC]==LW rt offset 6 (base) EA = sign-etend(offset) + GPR[base] GPR[rt] E[ translate(ea) ] PC PC

49 LW Datapath A d d P C a d d re ss In s tr c tio n m e m o ry 4 In s tr ctio n In s tr c tio n RegDest isitype re g is te r re g is te r 2 R e g is te r s re g is te r d a ta R e g d a ta d a ta S ig n e te n d add 3 A L U ALUSrc isitype A L U o p e r a tio n Z e r o A L U res lt A d d re s s d a ta A d d re s s d a ta D a ta d a ta m e m o ry D a ta d a ta e m m e m o ry e m e m e m a. D a ta m e m o ry n it 6 b. S i if E[PC]==LW rt offset 6 (base) EA = sign-etend(offset) + GPR[base] GPR[rt] E[ translate(ea) ] PC PC + 4 IF ID EX E WB Combinational state pdate logic 49

50 Store Instrctions Assembly (e.g., store 4-byte word) SW rt reg offset 6 (base reg ) achine encoding SW 6-bit base 5-bit rt 5-bit offset 6-bit I-type Semantics if E[PC]==SW rt offset 6 (base) EA = sign-etend(offset) + GPR[base] E[ translate(ea) ] GPR[rt] PC PC + 4 5

51 SW Datapath A d d P C a d d re ss In s tr c tio n m e m o ry 4 In s tr ctio n In s tr c tio n RegDest isitype re g is te r re g is te r 2 R e g is te r s re g is te r d a ta R e g d a ta d a ta S ig n e te n d add 3 A L U ALUSrc isitype A L U o p e r a tio n Z e r o A L U res lt A d d re s s d a ta A d d re s s d a ta D a ta d a ta m e m o ry D a ta d a ta e m m e m o ry e m e m e m a. D a ta m e m o ry n it 6 b. S i if E[PC]==SW rt offset 6 (base) EA = sign-etend(offset) + GPR[base] E[ translate(ea) ] GPR[rt] PC PC + 4 IF ID EX E WB Combinational state pdate logic 5

52 Load-Store Datapath A d d P C a d d re ss In s tr c tio n m e m o ry 4 In s tr c tio n In s tr ctio n RegDest isitype re g is te r re g is te r 2 R e g is te r s re g is te r d a ta R e g!isstore d a ta d a ta S ig n e te n d add 3 A L U ALUSrc isitype A L U o p e r a tio n Z e r o A L U re s lt A d d re s s d a ta isstore e m D a ta m e m o ry isload d a ta e m **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 52

53 Datapath for Non-Control-Flow Insts. A d d P C a d d re ss In s tr c tio n m e m o ry 4 In s tr c tio n In s tr ctio n RegDest isitype re g is te r re g is te r 2 R e g is te r s re g is te r d a ta R e g!isstore d a ta d a ta S ig n e te n d 3 A L U ALUSrc isitype A L U o p e r a tio n Z e r o A L U re s lt A d d re s s d a ta isstore e m D a ta m e m o ry isload d a ta e m emtoreg isload **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 53

54 Single-Cycle Datapath for Control Flow Instrctions 54

55 Unconditional Jmp Instrctions Assembly J immediate 26 achine encoding J 6-bit immediate 26-bit J-type Semantics if E[PC]==J immediate 26 target = { PC[3:28], immediate 26, 2 b } PC target 55

56 Unconditional Jmp Datapath isj PCSrc concat P C a d d re ss In s tr c tio n m e m o ry **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 4 A d d In s tr c tio n In s tr ctio n? re g is te r re g is te r 2 R e g is te r s re g is te r d a ta R e g d a ta d a ta S ig n e te n d X 3 X A L U ALUSrc A L U o p e r a tio n Z e r o A L U re s lt A d d re s s d a ta e m D a ta m e m o ry d a ta e m if E[PC]==J immediate26 PC = { PC[3:28], immediate26, 2 b } What abot JR, JAL, JALR? 56

57 Conditional Branch Instrctions Assembly (e.g., branch if eqal) BEQ rs reg rt reg immediate 6 achine encoding BEQ 6-bit rs 5-bit rt 5-bit immediate 6-bit I-type Semantics (assming no branch delay slot) if E[PC]==BEQ rs rt immediate 6 target = PC sign-etend(immediate) 4 if GPR[rs]==GPR[rt] then PC target else PC PC

58 Conditional Branch Datapath (For Yo to Fi) watch ot PCSrc 4 A d d P C + 4 fro m in str c tio n d a ta p a th A d d S m B ra n c h ta rg e t S h ift concat P C a d d re ss In s tr c tio n m e m o ry In s tr ctio n In s tr c tio n re g is te r re g is te r 2 R e g is te rs re g is te r d a ta d a ta d a ta 2 le ft 2 sb 3 A L U o p e r a tio n T o b ra n c h A L U bcond Z e ro c o n tro l lo g ic R e g S ig n e te n d **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] How to phold the delayed branch semantics? 58

59 Ptting It All Together Instrction [25 ] S h ift Jm p address [3 ] left PCSrc =Jmp 4 A d d PC +4 [3 28] RegD st J m p B ra n ch S h ift le ft 2 A d d A LU re s lt PCSrc 2 =Br Taken Instrction [3 26] C o ntro l e m e m to R eg A L U O p e m ALU Src Reg P C ad d re ss In s trc tio n m e m or y In strc tio n [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] R ea d register R ea d da ta da ta register 2 R eg iste rs da ta 2 re giste r bcond Z e ro A L U A L U re s lt A d d re ss d ata D ata m e m o ry d ata Instrction [5 ] S ig n e te n d A L U co n tro l ALU operation In str ction [5 ] **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] JAL, JR, JALR omitted 59

60 We did not cover the following slides in lectre. These are for yor preparation for the net lectre.

61 Single-Cycle Control Logic 6

62 Single-Cycle Hardwired Control As combinational fnction of Inst=E[PC] 3 6-bit 3 opcode 6-bit 3 opcode 6-bit rs 5-bit rs 5-bit 2 2 rt 5-bit rt 5-bit immediate 26-bit 6 6 rd 5-bit immediate 6-bit shamt 5-bit 6 fnct 6-bit R-type I-type J-type Consider All R-type and I-type ALU instrctions LW and SW BEQ, BNE, BLEZ, BGTZ J, JR, JAL, JALR 62

63 Single-Bit Control Signals When De-asserted When asserted Eqation RegDest GPR write select according to rt, i.e., inst[2:6] GPR write select according to rd, i.e., inst[5:] opcode== ALUSrc 2 nd ALU inpt from 2 nd GPR read port 2 nd ALU inpt from signetended 6-bit immediate (opcode!=) && (opcode!=beq) && (opcode!=bne) emtoreg Steer ALU reslt to GPR write port steer memory load to GPR wr. port opcode==lw GPR write disabled GPR write enabled (opcode!=sw) && RegWrite (opcode!=b) && (opcode!=j) && (opcode!=jr)) JAL and JALR reqire additional RegDest and emtoreg options 63

64 Single-Bit Control Signals When De-asserted When asserted Eqation emread emory read disabled emory read port retrn load vale opcode==lw emwrite emory write disabled emory write enabled opcode==sw PCSrc bit immediate jmp According to PCSrc 2 net PC is based on 26- target PCSrc 2 net PC = PC + 4 net PC is based on 6- bit immediate branch target (opcode==j) (opcode==jal) (opcode==b) && bcond is satisfied JR and JALR reqire additional PCSrc options 64

65 ALU Control case opcode select operation according to fnct ALUi selection operation according to opcode LW select addition SW select addition B select bcond generation fnction don t care Eample ALU operations ADD, SUB, AND, OR, XOR, NOR, etc. bcond on eqal, not eqal, LE zero, GT zero, etc. 65

66 R-Type ALU Instrction [25 ] S h ift Jm p address [3 ] left PCSrc =Jmp 4 A d d PC +4 [3 28] RegD st J m p B ra n ch S h ift le ft 2 A d d A LU re s lt PCSrc 2 =Br Taken Instrction [3 26] C o ntro l e m e m to R eg A L U O p e m P C ad d re ss In s trc tio n m e m or y In strc tio n [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] ALU Src Reg R ea d register R ea d da ta da ta register 2 R eg iste rs da ta 2 re giste r A L U bcond Z e ro A L U re s lt A d d re ss d ata D ata m e m o ry d ata Instrction [5 ] In str ction [5 ] S ig n e te n d A L U fnct co n tro l ALU operation **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 66

67 I-Type ALU Instrction [25 ] S h ift Jm p address [3 ] left PCSrc =Jmp 4 A d d PC +4 [3 28] RegD st J m p B ra n ch S h ift le ft 2 A d d A LU re s lt PCSrc 2 =Br Taken Instrction [3 26] C o ntro l e m e m to R eg A L U O p e m P C ad d re ss In s trc tio n m e m or y In strc tio n [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] ALU Src Reg R ea d register R ea d da ta da ta register 2 R eg iste rs da ta 2 re giste r A L U bcond Z e ro A L U re s lt A d d re ss d ata D ata m e m o ry d ata Instrction [5 ] In str ction [5 ] S ig n e te n d A L U opcode n tro l ALU operation **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 67

68 LW Instrction [25 ] S h ift Jm p address [3 ] left PCSrc =Jmp 4 A d d PC +4 [3 28] RegD st J m p B ra n ch S h ift le ft 2 A d d A LU re s lt PCSrc 2 =Br Taken Instrction [3 26] C o ntro l e m e m to R eg A L U O p e m P C ad d re ss In s trc tio n m e m or y In strc tio n [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] ALU Src Reg R ea d register R ea d da ta da ta register 2 R eg iste rs da ta 2 re giste r A L U bcond Z e ro A L U re s lt A d d re ss d ata D ata m e m o ry d ata Instrction [5 ] In str ction [5 ] S ig n e te n d A L U Add co n tro l ALU operation **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 68

69 SW Instrction [25 ] S h ift Jm p address [3 ] left PCSrc =Jmp 4 A d d PC +4 [3 28] RegD st J m p B ra n ch S h ift le ft 2 A d d A LU re s lt PCSrc 2 =Br Taken Instrction [3 26] C o ntro l e m e m to R eg A L U O p e m P C ad d re ss In s trc tio n m e m or y In strc tio n [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] * ALU Src Reg R ea d register R ea d da ta da ta register 2 R eg iste rs da ta 2 re giste r A L U bcond Z e ro A L U re s lt A d d re ss d ata D ata m e m o ry d ata * Instrction [5 ] In str ction [5 ] S ig n e te n d A L U Add co n tro l ALU operation **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 69

70 Branch Not Taken Instrction [25 ] S h ift Jm p address [3 ] left PCSrc =Jmp 4 A d d PC +4 [3 28] RegD st J m p B ra n ch S h ift le ft 2 A d d A LU re s lt PCSrc 2 =Br Taken Instrction [3 26] C o ntro l e m e m to R eg A L U O p e m P C ad d re ss In s trc tio n m e m or y In strc tio n [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] * ALU Src Reg R ea d register R ea d da ta da ta register 2 R eg iste rs da ta 2 re giste r A L U bcond Z e ro A L U re s lt A d d re ss d ata D ata m e m o ry d ata * Instrction [5 ] In str ction [5 ] S ig n e te n d A L U bcond n tro l ALU operation **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 7

71 Branch Taken Instrction [25 ] S h ift Jm p address [3 ] left PCSrc =Jmp 4 A d d PC +4 [3 28] RegD st J m p B ra n ch S h ift le ft 2 A d d A LU re s lt PCSrc 2 =Br Taken Instrction [3 26] C o ntro l e m e m to R eg A L U O p e m P C ad d re ss In s trc tio n m e m or y In strc tio n [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] * ALU Src Reg R ea d register R ea d da ta da ta register 2 R eg iste rs da ta 2 re giste r A L U bcond Z e ro A L U re s lt A d d re ss d ata D ata m e m o ry d ata * Instrction [5 ] In str ction [5 ] S ig n e te n d A L U bcond n tro l ALU operation **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 7

72 Jmp Instrction [25 ] S h ift Jm p address [3 ] left PCSrc =Jmp 4 A d d PC +4 [3 28] RegD st J m p B ra n ch S h ift le ft 2 A d d A LU re s lt * PCSrc 2 =Br Taken Instrction [3 26] C o ntro l e m e m to R eg A L U O p e m P C ad d re ss In s trc tio n m e m or y In strc tio n [3 ] Instrction [25 2] Instrction [2 6] Instrction [5 ] * ALU Src Reg R ea d register R ea d da ta da ta register 2 R eg iste rs da ta 2 re giste r * A L U bcond Z e ro A L U re s lt A d d re ss d ata D ata m e m o ry d ata * Instrction [5 ] In str ction [5 ] S ig n e te n d * A L U co n tro l ALU operation **Based on original figre from [P&H CO&D, COPYRIGHT 24 Elsevier. ALL RIGHTS RESERVED.] 72

73 What is in That Control Bo? Combinational Logic Hardwired Control Idea: Control signals generated combinationally based on instrction Seqential Logic Seqential/icroprogrammed Control Control Store Idea: A memory strctre contains the control signals associated with an instrction 73