CPU DESIGN The Single-Cycle Implementation

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1 22 ompter Organization Seqential vs. ombinational ircits Digital circits can be classified into two categories: DESIGN The Single-ycle Implementation. ombinational ircits: m, 2. Seqential ircits: flip-flops, registers, memory Shakil. Khan (adapted from rof. H. Romani) Dept of S & Eng, York niversity -22 Jne locks eriodic signal oscillating between low and high states with fied cycle time lock freqency = inverse of clock cycle time l o c k p e r i o d R i s i n g e d g e lock controls when the state of a memory element changes F a l l i n g e d g e DESIGN The Datapath Single-ycle ontrol erformance S t a t e e l e m e n t o m b i n a t i o n a l l o g i c S t a t e e l e m e n t 2 Focs on the Sbset: addi, add/sb/and/or/slt, lw/sw, beq, j l o c k c y c l e -22 Jne Jne The Basic Datapath omponents () Bilding the Datapath. rogram conter contains address of net instrction 6 2 e t e n d 2. Sign-etension nit etends a 6-bit integer to a 2-bit integer c o n t r o l d d S m r e s l t. dder adds two 2-bit integers. add/sbtract/and/or/compare two 2-bit integers -22 Jne /Romani

2 The Basic Datapath omponents (2) e m The Basic Datapath omponents () I n s t r c t i o n I n s t r c t i o n e m o r y I n s t r c t i o n d d r e s s 5.Instrction memory Register nmbers Data 5 6. n i t 5 5 Re g i s t e r s 2 e m I R e g 7. Register Files -22 Jne BS -22 Jne The Basic Datapath [comptational R-Type] Recall the Formats: R opode rs rt rd sa fnode I I opode rs rt immediate 6 26 J opode immediate Register rs = sorce, rt = target, rd = destination. -22 Jne Jne The Basic Datapath [comptational R-Type] The ircitry I I Jne Jne /Romani 2

3 Recall the Formats: dd spport for comptational I-Types R opode rs rt rd sa fnode I opode rs rt immediate 6 26 J opode immediate I Register rs = sorce, rt = target, rd = destination. -22 Jne Jne dd spport for comptational I-Types dd spport for lw I I D -22 Jne Jne dd spport for lw dd spport for sw I D I D -22 Jne Jne /Romani

4 dd Spport for branch ombined Datapath (w/o Jmp) I sll D d d I n s t r c t i o n I n s t r c t i o n 2 R e g 6 2 e t e n d S r c d d r e s l t S r c o p e r a t i o n r e s l t d d r e s s e m e m e m t o R e g 2-22 Jne Jne add/sb/or/and/slt $s,$s2,$s lw $s, offset($s2) S r c S r c d d I n s t r c t i o n I n s t r c t i o n 2 R e g 6 2 e t e n d S r c d d r e s l t o p e r a t i o n r e s l t d d r e s s e m e m e m t o R e g d d I n s t r c t i o n I n s t r c t i o n 2 R e g 6 2 e t e n d S r c d d r e s l t o p e r a t i o n r e s l t d d r e s s e m e m e m t o R e g Jne Jne sw $s, offset($s2) beq $s, $s2, w_offset S r c S r c d d I n s t r c t i o n I n s t r c t i o n 2 R e g 6 2 e t e n d S r c d d r e s l t o p e r a t i o n r e s l t d d r e s s e m e m e m t o R e g d d I n s t r c t i o n I n s t r c t i o n 2 R e g 6 2 e t e n d S r c d d r e s l t o p e r a t i o n r e s l t d d r e s s e m e m e m t o R e g Jne Jne /Romani

5 Instrction [25 ] Shift Jmp address [ ] left address Instrction memory dd Instrction [ ] + [ 28] Instrction [ 26] Instrction [25 2] Instrction [2 6] Instrction [5 ] ontrol Jmp em emtoreg Op emwrite Src register register 2 Registers Write register Write data data data 2 Shift left 2 dd reslt Zero reslt ddress Write data Data memory data Bilding the ontrol Instrction [5 ] 6 2 Sign etend Instrction [5 ] control -22 Jne ontrol clk I clk sll D Eercise add $t, $s, $a SIGN VE Src emtoreg em emwrite Jmp Operation (-bit) -22 Jne Jne Eercise sw $t, 5($s) Eercise beq $t, $s, SIGN Src emtoreg em emwrite Jmp Operation (-bit) VE SIGN Src emtoreg em emwrite Jmp Operation (-bit) VE -22 Jne Jne /Romani 5

6 Generating the ontrol Signals Splitting the ontrol ll signals depend on the instrction, i.e. on a total of 2 bits comple. Note that non- signals depend only on the 6-bit op_code simpler. Hence, split the control into a main control nit that sees only the opcode, and an ailiary one that sees the fntion code. The two commnicate via a new signal, op 26 5 ain ontrol nit ontrol nit control signals Operation -22 Jne Jne The Operation Signal -bit signal throgh which the ailiary control nit tells the to: = and = or = add = sb = slt The op Signal 2-bit signal throgh which the main control nit tells the ailiary to: = add (no matter what the fn_code is) = sbtract (no matter what the fn_code is) = R-Type (follow the fn_code) -22 Jne Jne The ain ontrol nit -26 ombinational ogic op- op- src emtoreg em emwrite Jmp The ain ontrol nit () Inpts of ontrol nit: Instrction Opcode in Decimal Instrction Src emtoreg emrd emwrt Op Op R-format lw sw X X beq X X -22 Jne Jne Opcode in Binary Op5 Op Op Op2 Op Op R-format ten lw 5 ten sw ten beq ten Otpts of ontrol nit: 5 22/Romani 6

7 The ain ontrol nit (2) ontrol Inpts Op5 Op op- op- Op Op2 Op Op R-format Iw sw beq Otpts Src emtoreg 5- XIRY ontrol nit Operation-2 Operation- Operation- em emwrite Op OpO -22 Jne Jne ontroller Implementation () ontroller Implementation (2) Op Op (F F) Instrction (opcode) Inpts Op (Op Op) Fnction Field (F5 F) Desired action Otpts Operation (Op Op) lw (I) ( ) X X X X X X add sw (I) ( ) X X X X X X add beq (I) ( ) X X X X X X sb Op Op Op Op Op F2 Op2 Op O F control block add (2) ( ) X X add sb () X ( ) X X sb and (6) ( ) X X and or (7) ( ) X X or slt (2) X ( ) X X slt F (5 ) F F2 F F Operation2 Operation Operation Operation -22 Jne Jne The Single-ycle erformance erformance nalysis oad = 5 fnctional nits: inst. fetch, register access,, data memory access, register access Store = fnctional nits: instrction fetch, register access,, data memory access R-type = fnctional nits: instrction fetch, register access,, register access = fnctional nits: instrction fetch, register access, Jmp = fnctional nit: instrction fetch -22 Jne Jne /Romani 7

8 omponent Delays =5, =, and E (both I and D)=2 ps. ompte Time to eecte varios instrctions j, beq, add, sw, lw ompte a GHz for the lock nswer:.66 GHz ritiqe of S/ycle +very simple -caters to the slowest -h/w redndancy -22 Jne /Romani 8

Review. Combined Datapath

Review. Combined Datapath Review Topics:. A single cycle implementation 2. State Diagrams. A mltiple cycle implementation COSC 22: Compter Organization Instrctor: Dr. Amir Asif Department of Compter Science York University Handot