中村宏 工学部計数工学科 情報理工学系研究科システム情報学専攻 計算システム論第 2 1

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1 計算システム論第 2 (3 章 ) 中村宏 工学部計数工学科 情報理工学系研究科システム情報学専攻 計算システム論第 2

2 IPS Assembly Langage ( 抜粋 ) IPS operands Name Eample Comments $s-$s7, $t-$t9, $zero, Fast locations for data. In IPS, data mst be in registers to perform 32 registers $a-$a3, $v-$v, $gp, arithmetic. IPS register $zero alw ays eqals. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants. emory[], Accessed only by data transfer instrctions. IPS ses byte addresses, so 2 3 memory emory[4],..., seqential w ords differ by 4. emory holds data strctres, sch as arrays, words emory[ ] and spilled registers, sch as those saved on procedre calls. IPS assembly langage Category Eample eaning Comments add add $s, $s2, $s3 $s = $s2 + $s3 Three operands; data in registers Arithmetic sbtract sb $s, $s2, $s3 $s = $s2 - $s3 Three operands; data in registers add immediate addi $s, $s2, $s = $s2 + Used to add constants load word lw $s, ($s2) $s = emory[$s2 + ] Word from memory to register store word sw $s, ($s2) emory[$s2 + ] = $s Word from register to memory Data transfer load byte lb $s, ($s2) $s = emory[$s2 + ] Byte from memory to register store byte sb $s, ($s2) emory[$s2 + ] = $s Byte from register to memory load pper immediate li $s, $s = * 2 6 Loads constant in pper 6 bits branch on eqal beq $s, $s2, 25 if ($s == $s2) go to PC branch on not eqal bne $s, $s2, 25 if ($s!= $s2) go to Conditional PC branch set on less than slt $s, $s2, $s3 if ($s2 < $s3) $s = ; else $s = Eqal test; PC-relative branch Not eqal test; PC-relative Compare less than; for beq, bne set less than immediate slti $s, $s2, if ( $s2 < ) $s = ; else $s = Compare less than constant jmp j 25 go to Jmp to target address Uncondi- jmp register jr $ra go to $ra For switch, procedre retrn tional jmp jmp and link jal 25 $ra = PC + 4; go to For procedre call 計算システム論第 2 2

3 命令の sbset ADD and SUB addu rd, rs, rt (nsigned) sbu rd, rs, rt 3 OR Immediate: ori rt, rs, imm6 LOAD and STORE Word lw rt, rs, imm6 sw rt, rs, imm6 BRANCH: beq rs, rt, imm op rs rt rd shamt fnct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits op rs rt immediate 6 bits 5 bits 5 bits 6 bits 26 命令フォーマット 2 6 op rs rt immediate 6 bits 5 bits 5 bits 6 bits 6 計算システム論第 2 3

4 実現すべき動作 PC (Program Conter) で指定された番地のメモリから命令を取る. PC は +4する ( 分岐命令以外 ) op rs rt rd shamt fnct = E[ PC ] addu, sbu op rs rt Imm6 = E[ PC ] ori, lw, sw, beq 2 つの命令フォーマット 命令 実現すべき動作 addu R[rd] < R[rs] + R[rt]; PC < PC + 4 sbu R[rd] < R[rs] R[rt]; PC < PC + 4 ori R[rt] < OR(R[rs], zero_et(imm6) ); PC < PC + 4 lw R[rt] < E[ R[rs] + sign_et(imm6)]; PC < PC + 4 sw E[ R[rs] + sign_et(imm6) ] < R[rt]; PC < PC + 4 beq if ( R[rs] == R[rt] ) then PC < PC + sign_et(imm6)] else PC < PC + 4 計算システム論第 2 4

5 命令の種類と各ステージにおける処理 Step name fetch decode/register fetch 制御信号の作り方 Action for R-type instrctions Action for memory-reference instrctions IR = emory[pc] PC = PC + 4 A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = PC + (sign-etend (IR[5-]) << 2) Action for branches Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then comptation, branch/ (IR[5-]) PC = ALUOt jmp completion emory access or R-typ Reg [IR[5-]] = Load: DR = emory[aluot] completion ALUOt or Store: emory [ALUOt] = B emory read completion Load: Reg[IR[2-6]] = DR 制御信号は, 命令の種類, および現在のステップ ( 状態 ) に依存 状態遷移機械 (FS : Finite State achine) として記述可能 計算システム論第 2 5

6 データパスと制御論理 PC Address Write data emory emdata [25 2] [2 6] [5 ] register [5 ] emory data register Cond IorD Otpts em emwrite emtoreg IRWrite Control Op [5 ] [5 ] PCSorce ALUOp ALUSrcB 6 ALUSrcA RegWrite RegDst [25 ] Shift left 2 [3-26] PC [3-28] register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B ALU control Zero ALU ALU reslt Jmp address [3-] ALUOt 2 [5 ] 計算システム論第 2 6

7 例 : 状態 Step name fetch decode/register fetch Action for R-type instrctions Action for memory-reference instrctions IR = emory[pc] PC = PC + 4 A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = PC + (sign-etend (IR[5-]) << 2) Action for branches Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then comptation, branch/ (IR[5-]) PC = ALUOt jmp completion emory access or R-typ Reg [IR[5-]] = Load: DR = emory[aluot] completion ALUOt or Store: emory [ALUOt] = B emory read completion Load: Reg[IR[2-6]] = DR 計算システム論第 2 7

8 状態 におけるデータの流れ IR = emory[pc], PC=PC+4 PC Address Write data emory emdata [3-26] [25 2] [2 6] [5 ] register [5 ] emory data register Cond IorD Otpts em emwrite emtoreg IRWrite [25 ] Control Op [5 ] [5 ] PCSorce ALUOp ALUSrcB 6 ALUSrcA RegWrite RegDst register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B Shift left 2 ALU control PC [3-28] Zero ALU ALU reslt Jmp address [3-] ALUOt 2 [5 ] 必要な制御信号 IorD= (: PC em) ALUsrcA= (: PC ALU) em= ALUsrcB= (: 4 ALU) IRwrite= ALUop= (ALU : 足し算 ) PCwrite= PCSorce= (ALU 出力をPCへ ) 計算システム論第 2 8

9 制御信号の定義 計算システム論第 2 9

10 FS で記述した 制御論理状態 2 emory address comptation ALUSrcA = ALUSrcB = ALUOp = Start fetch em ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCSorce = 6 (Op = 'LW') or (Op = 'SW') Eection ALUSrcA = ALUSrcB = ALUOp= 8 (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = Cond PCSorce = decode/ register fetch (Op = 'BEQ') 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jmp completion PCSorce = 3 (Op = 'LW') emory access (Op = 'SW') 5 emory access 7 R-type completion em IorD = emwrite IorD = RegDst = RegWrite emtoreg = 4 Write-back step RegDst = RegWrite emtoreg = 計算システム論第 2

11 例 : 状態 Step name fetch decode/register fetch Action for R-type instrctions Action for memory-reference instrctions IR = emory[pc] PC = PC + 4 A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = PC + (sign-etend (IR[5-]) << 2) Action for branches Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then comptation, branch/ (IR[5-]) PC = ALUOt jmp completion emory access or R-typ Reg [IR[5-]] = Load: DR = emory[aluot] completion ALUOt or Store: emory [ALUOt] = B emory read completion Load: Reg[IR[2-6]] = DR 計算システム論第 2

12 状態 におけるデータの流れ A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = PC + (sign-etend (IR[5-]) << 2) PC Address Write data emory emdata [3-26] [25 2] [2 6] [5 ] register [5 ] emory data register Cond IorD Otpts em emwrite emtoreg IRWrite [25 ] Control Op [5 ] [5 ] PCSorce ALUOp ALUSrcB 6 ALUSrcA RegWrite RegDst register register 2 Registers Write register Write data Sign etend data data 2 32 Shift left 2 A B Shift left 2 ALU control PC [3-28] Zero ALU ALU reslt Jmp address [3-] ALUOt 2 [5 ] 計算システム論第 2 2

13 FSで記述した fetch 制御論理 em ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCSorce = 状態 2 emory address comptation ALUSrcA = ALUSrcB = ALUOp = Start 6 (Op = 'LW') or (Op = 'SW') Eection ALUSrcA = ALUSrcB = ALUOp= 8 (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = Cond PCSorce = decode/ register fetch (Op = 'BEQ') 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jmp completion PCSorce = 3 (Op = 'LW') emory access (Op = 'SW') 5 emory access 7 R-type completion em IorD = emwrite IorD = RegDst = RegWrite emtoreg = 4 Write-back step RegDst = RegWrite emtoreg = 計算システム論第 2 3

14 状態遷移図の作り方 Step name fetch decode/register fetch Action for R-type instrctions Action for memory-reference instrctions IR = emory[pc] PC = PC + 4 A = Reg [IR[25-2]] B = Reg [IR[2-6]] ALUOt = PC + (sign-etend (IR[5-]) << 2) Action for branches Eection, address ALUOt = A op B ALUOt = A + sign-etend if (A ==B) then comptation, branch/ 6 2 (IR[5-]) PC = ALUOt jmp completion emory access or R-typ Reg [IR[5-]] = Load: DR = emory[aluot] completion 7 ALUOt or 5 Store: emory [ALUOt] = B emory read completion 3 4 Load: Reg[IR[2-6]] = DR ステップ間の因果関係を状態遷移図で表す 8 計算システム論第 2 4

15 wired logic ( 布線論理 ) を用いた制御回路の実現 Op5 Op4 組み合わせ論理を PLA で記述 Op3 Op2 Op O p 5 O p 4 組み合わせ回路 C o n t r o l l o g i c O p 3 O p 2 O p I n s t r c t i o n r e g i s t e r o p c o d e f i e l d I n p t s O p 命令内の op フィールド S 3 S 2 O t p t s S S S t a t e r e g i s t e r P C W r i t e P C W r i t e C o n d I o r D e m R e a d e m W r i t e I R W r i t e e m t o R e g P C S o r c e A L U O p A L U S r c B A L U S r c A R e g W r i t e R e g D s t N S 3 N S 2 N S N S 4 ビットで 9 状態 Op S3 S2 S S AND 平面 Cond IorD em emwrite IRWrite emtoreg PCSorce PCSorce ALUOp ALUOp ALUSrcB ALUSrcB ALUSrcA RegWrite RegDst NS3 NS2 NS NS RegWrite=^S3 S2 ^S ^S + ^S3 S2 S S OR 平面 計算システム論第 2 5

16 RegWrite は? 状態 4() と状態 7() 2 ^S3 S2 ^S ^S + ^S3 S2 S S 3 emory address comptation ALUSrcA = ALUSrcB = ALUOp = (Op = 'LW') emory access (Op = 'SW') 5 Start emory access fetch em ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCSorce = 6 (Op = 'LW') or (Op = 'SW') 7 Eection ALUSrcA = ALUSrcB = ALUOp= 8 R-type completion (Op = R-type) Branch completion ALUSrcA = ALUSrcB = ALUOp = Cond PCSorce = (Op = 'BEQ') decode/ register fetch 9 ALUSrcA = ALUSrcB = ALUOp = (Op = 'J') Jmp completion PCSorce = em IorD = emwrite IorD = RegDst = RegWrite emtoreg = 4 Write-back step RegDst = RegWrite emtoreg = 計算システム論第 2 6

17 microprogram による制御論理の実現 C o n t r o l n i t i c r o c o d e m e m o r y マイクロ命令を格納 I n p t O t p t s P C W r i t e P C W r i t e C o n d I o r D e m R e a d e m W r i t e I R W r i t e B W r i t e e m t o R e g P C S o r c e A L U O p A L U S r c B A L U S r c A R e g W r i t e R e g D s t A d d r C t l D a t a p a t h A d d e r 次に実行すべきマイクロ命令を指定 i c r o p r o g r a m c o n t e r A d d r e s s s e l e c t l o g i c O p [ 5 ] A d d e r microcode memory microprogram conter 3 2 A d r C t l I n s t r c t i o n r e g i s t e r o p c o d e f i e l d D i s p a t c h R O 2 D i s p a t c h R O A d d r e s s s e l e c t l o g i c O p I n s t r c t i o n r e g i s t e r o p c o d e f i e l d 計算システム論第 2 7

18 microprogram による制御論理の実現 Dispatch RO Op Opcode name Vale R-format jmp beq lw sw Dispatch RO 2 Op Opcode name Vale lw sw Label ALU control SRC SRC2 Register control emory control Seqencing Fetch Add PC 4 PC ALU Seq Add PC Etshft Dispatch em Add A Etend Dispatch 2 LW2 ALU Seq Write DR Fetch SW2 Write ALU Fetch Rformat Fnc code A B Seq Write ALU Fetch BEQ Sbt A B ALUOt-cond Fetch JUP Jmp address Fetch データパスに与える制御信号 microcode memory に保持される microcode 次のマイクロ命令を指定 計算システム論第 2 8

19 microcode のフォーマット Field name Vale Signals active Comment Add ALUOp = Case the ALU to add. ALU control Sbt ALUOp = Case the ALU to sbtract; this implements the compare for branches. Fnc code ALUOp = Use the instrction's fnction code to determine ALU control. SRC PC ALUSrcA = Use the PC as the first ALU inpt. A ALUSrcA = Register A is the first ALU inpt. B ALUSrcB = Register B is the second ALU inpt. SRC2 4 ALUSrcB = Use 4 as the second ALU inpt. Etend ALUSrcB = Use otpt of the sign etension nit as the second ALU inpt. Etshft ALUSrcB = Use the otpt of the shift-by-two nit as the second ALU inpt. two registers sing the rs and rt fields of the IR as the register nmbers and ptting the data into registers A and B. Write ALU RegWrite, Write a register sing the rd field of the IR as the register nmber and Register RegDst =, the contents of the ALUOt as the data. control emtoreg = Write DR RegWrite, Write a register sing the rt field of the IR as the register nmber and RegDst =, the contents of the DR as the data. emtoreg = PC em, memory sing the PC as address; write reslt into IR (and lord = the DR). emory ALU em, memory sing the ALUOt as address; write reslt into DR. lord = Write ALU emwrite, Write memory sing the ALUOt as address, contents of B as the lord = data. ALU PCSorce = Write the otpt of the ALU into the PC. PC write control ALUOt-cond PCSorce =, If the Zero otpt of the ALU is active, write the PC with the contents Cond of the register ALUOt. jmp address PCSorce =, Write the PC with the jmp address from the instrction. Seq AddrCtl = Choose the net microinstrction seqentially. Seqencing Fetch AddrCtl = Go to the first microinstrction to begin a new instrction. Dispatch AddrCtl = Dispatch sing the RO. Dispatch 2 AddrCtl = Dispatch sing the RO 2. 計算システム論第 2 9

20 水平 vs. 垂直マイクロプログラム 2bit bit 2bit 3bit 3bit 4bit 2bit Label ALU control SRC SRC2 Register control emory control Seqencing Fetch Add PC 4 PC ALU Seq Add PC Etshft Dispatch em Add A Etend Dispatch 2 LW2 ALU Seq Write DR Fetch SW2 Write ALU Fetch Rformat Fnc code A B Seq Write ALU Fetch BEQ Sbt A B ALUOt-cond Fetch JUP Jmp address Fetch bit 折りたたんでフィールドを共有する 2bit bit 2bit 3bit 2bit ALU Register Label U/L control SRC SRC2 control Seqencing 命令ステップは U/L emory PC Write Control Fetch U Add PC 4 Seq 僅かプラス2 L PC ALU Seq U Add PC Etshft Dispatch ' em U Add A Etend Dispatch 2' マイクロ命令用 LW2 L ALU Seq U Write DR Fetch メモリ量減少 SW2 L Write ALU Fetch Rformat U Fnc code A B Seq 7bit = 7bit L Write ALU Fetch BEQ U Sbt A B Seq bit 2 = 32bit L ALU Ot-Cond Fetch JUP L Jmp address計算システム論第 Fetch 2 2