Review. Combined Datapath

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Lizbeth Wilkinson
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1 Review Topics:. A single cycle implementation 2. State Diagrams. A mltiple cycle implementation COSC 22: Compter Organization Instrctor: Dr. Amir Asif Department of Compter Science York University Handot # Designing a IPS Processor I: Control Patterson: Section. and Appendi D. D. Goal: Implement a sbset of core instrctions from the IPS instrction set, given below Category Instrction Eample eaning Comments Arithmetic and Logical Data Transfer Branch add add $s,$s2,$s $s! $s2+$s sbtract sb $s,$s2,$s $s! $s2-$s and add $s,$s2,$s $s! $s2&$s & => and or or $s,$s2,$s $s! $s2 $s => or slt slt $s,$s2,$s If $s < $s, $s! else $s! load word lw $s,($s2) $s! em[$s2+] store word sw $s,($s2) em[$s2+]! $s branch on eqal beq $s,$s2,l if($s==$s2) go to L nconditional jmp j 25 go to 2 Combined Datapath add/sb/or/and/slt $s,$s2,$s Combined Datapath: Arithmetic Operations (add,sb,or,and,slt) S r c S r c r e s l t r e s l t I n s t r c t i o n I n s t r c t i o n 2 R e g 6 2 e t e n d o p e r a t i o n r e s l t r e s s e m e m e m t o R e g I n s t r c t i o n I n s t r c t i o n 2 R e g 6 2 e t e n d o p e r a t i o n r e s l t r e s s e m e m e m t o R e g

2 lw $s, offset($s2) Combined Datapath: Data Transfer (load) Review: Data Transfer (store) sw $s, offset($s2) S r c S r c r e s l t r e s l t I n s t r c t i o n I n s t r c t i o n 2 R e g 6 2 e t e n d o p e r a t i o n r e s l t r e s s e m e m e m t o R e g I n s t r c t i o n I n s t r c t i o n 2 R e g 6 2 e t e n d o p e r a t i o n r e s l t r e s s e m e m e m t o R e g 5 6 beq $s, $s2, w_offset Review: Data Transfer (branch) Types of Datapath I n s t r c t i o n I n s t r c t i o n 2 R e g 6 2 e t e n d r e s l t o p e r a t i o n r e s l t S r c r e s s e m e m e m t o R e g! Datapaths can be divided into two categories.! Single cycle datapath: An instrction (e.g. lw) is performed in clock cycle 2.! ltiple cycle datapath: An instrction is performed in mltiple clock cycles! Advantage of single datapath: Keeps the design simpler! Disadvantage of single datapath:.! No datapath resorce can be sed more than once in a clock cycle 2.! Elements being accessed more than once in an instrction be dplicated or have mltiple inpts and otpts..! An instrction memory separate from data memory is reqired! In section., a single cycle datapath is considered. We epand the discssion to mltiple cycle datapaths later. 7 8

3 Control Control: ALU Control Unit ()! What needs to be added to complete the design of the single cycle datapath?! Control Unit activates appropriate controls at.! ALU 2.! UX s ().! Read/write signals for register file.! Read/write signals for data memory! Consider the design of the ALU Control Unit ALU Control Lines Reslt o p e r a t i o n! Inpts to ALU Control:.! Fnction fields of instrctions 2.! 2-bit control field ()! Otpt of ALU Control:.! -bit signal that controls the ALU Instrctions [5-] 5 ALU Control a b ALU reslt AND OR Add Sbtract SLT NOR a b C a r r y O t R e s l t O v e r f l o w 9 2 Control: ALU Control Unit (2) Control: ALU Control Unit () I-format: op ( 26) rs (25 2) rt (2 6) Immediate / Offset (5 ).! I-format instrctions (lw/sw/beq) does not have a fnction field 2.! Use to differentiate the operation from the rest e.g., = for lw/sw; = for beq R-format: op ( 26) rs (25 2) rt (2 6) rd (5 ) shamt ( 6) fnct (5 ).! R-format instrctions (add/sb/and/or) does have a fnction field 2.! = for all instrctions.! Fnction field is 2 for add, for sb, 6 for AND, 7 for OR, and 2 for SLT Instrction (opcode) Inpts ( ) Fnction Field (F5 F) Desired ALU action Otpts Operation (Op Op) lw (I) X X X X X X add sw (I) X X X X X X add beq (I) X X X X X X sb add (2) add sb () sb and (6) and or (7) or slt (2) slt.! The first two rows of the trth table are the same. 2.! Nmber of inpts in the trth table are 6 while nmber of rows in the table are 8..! Only 8 of the 2 6 = 2 possible combinations of inpt are being sed..! Some DO NOT CARE entries can be added to simplify the above trth table. 2

4 Control: ALU Control Unit () Instrction (opcode) Inpts ( ) Fnction Field (F5 F) Desired ALU action Otpts Operation (Op Op) lw (I) ( ) X X X X X X add sw (I) ( ) X X X X X X add beq (I) ( ) X X X X X X sb add (2) ( ) X X add sb () X ( ) X X sb and (6) ( ) X X and or (7) ( ) X X or slt (2) X ( ) X X slt does not se encoding, so, and may be replaced with X. The first two fields of the fnction fields are always, so, they are replaced by XX. Control: ALU Control Unit () Trth Table for Operation2 = : Simplified Epressions: Fnction code fields F5 F F F2 F F X X X X X X X X X X X() X() Op2 = + ALUOP" F The trth table above shows the inpt combinations for which the ALU Control shold be,,, or (the other combinations are not sed). Control: ALU Control Unit () Trth Table for Operation = : Fnction code fields F5 F F F2 F F X X X X X X X X() X X X X X() X() Simplified Epressions: Op = + F2 Op2 = + ALUOP F Control: ALU Control Unit () Trth Table for Operation = : Fnction code fields F5 F F F2 F F X X X X X X X X X X X X Simplified Epressions: Op = (F + F) Op = + F2 Op2 = + ALUOP F 5 6

5 Control: ALU Control Unit (5) Op = (F + F) Op = + F2 Op2 = + ALUOP F O p b l o c k O p O p F ( 5 ) F F 2 F O p e r a t i o n 2 O p e r a t i o n O p e r a t i o n F O p e r a t i o n ain Control () R-format: op ( 26) rs (25 2) rt (2 6) rd (5 ) shamt ( 6) fnct (5 ) I-format: op ( 26) rs (25 2) rt (2 6) Immediate / Offset (5 ).! Opcode is contained in bits ! Registers specified by rs (bits 25 2) and rt (bits 2 6) are always read.! Base register (w/ base address) for lw/sw instrction is specified by rs (bits 25 2).! 6-bit offset for beq, lw, and sw is always specified in bits 5. 5.! Destination register is specified in one of the two places:! For R-type instrctions (add/sb/and/or), destination register is specified by bits (5 )! For lw instrction, destination register is specified by bits (2 6) Using information ( 5), we can add the instrction labels and additional UX s to the datapath that we have constrcted. Combinational Circit for the ALU Control Unit 7 8 ain Control (2) ain Control () S r c Control Inpt Effect when Deasserted () Effect when asserted () R e g r e s l t RegDst Regwrite Destination register nmber comes from bits 2 6 of the instrction (sw) None Destination register nmber comes from bits 5 of the instrction (add,sb,or,and,slt) Data on the write data inpt is written on the register specified on the write register inpt (lw, add,sb,or,and) I n s t r c t i o n [ ] I n s t r c t i o n I n s t r c t i o n [ ] I n s t r c t i o n [ 2 6 ] I n s t r c t i o n [ 5 ] I n s t r c t i o n [ 5 ] e t e n d I n s t r c t i o n [ 5 ] O p r e s l t e m r e s s e m e m t o R e g ALUSrc emread emwrite emtoreg PCSrc Second operand to ALU comes from the second register file otpt (add,sb,or,and,beq,slt) None None Data from the otpt of ALU is fed into write data inpt of the register file (add,sb,or,and,slt) PC is replaced by the otpt of adder which adds to the eisting content of PC (ecept for beq) Second operand to ALU is sign etended, lower 6 bits of instrction(lw,sw) Data from memory location specified by address inpt is placed on the read data otpt (lw) Data from write data inpt replaces memory location specified by address inpt (sw) Data from the read data otpt of data memory is fed into write data inpt of the register file (lw) PC is replaced by the otpt of adder which comptes branch target by adding eisting content of PC with 2-bit right shifted offset (beq) Nmber of control lines is ( for UX s, for ALU control, 2 for data memory, for register file) 9 Net step in the design of datapath is to add a control nit that generates the control inpts to UX s 2

6 ain Control () ain Control (5) I n s t r c t i o n [ 2 6 ] e m e m t o R e g O p e m R e g r e s l t S r c Inpts of Control Unit: Instrction Opcode in Decimal Opcode in Binary Op5 Op Op Op2 Op Op R-format ten lw 5 ten sw ten beq ten I n s t r c t i o n I n s t r c t i o n [ ] I n s t r c t i o n [ 25 2 ] I n s t r c t i o n [ 2 6 ] I n s t r c t i o n [ 5 ] I n s t r c t i o n [ 5 ] e t e n d r e s l t r e s s Otpts of Control Unit: Instrction RegDst ALUSrc emtoreg RegWrite emread emwrite Branch R-format lw sw X X beq X X I n s t r c t i o n [ 5 ] 2 which constittes the trth table 22 I n p t s ain Control (6) O p 5 O p O p O p 2 O p O p R - f o r m a t I w s w b e q O t p t s Eample: R-type Instrction (step: fetch instrction & increment PC) I n s t r c t i o n [ 2 6 ] e m e m t o R e g O p e m R e g r e s l t e m t o R e g R e g e m e m O p 2 O p O I n s t r c t i o n Step. Fetch instrction I n s t r c t i o n [ ] 2. Add to the vale of PC I n s t r c t i o n [ ] I n s t r c t i o n [ 2 6 ] I n s t r c t i o n [ 5 ] I n s t r c t i o n [ 5 ] 2 I n s t r c t i o n [ 5 ] 6 2 e t e n d r e s l t r e s s 2

7 Eample: R-type Instrction (step2: Read two sorce registers) Eample: R-type Instrction (step: ALU operates on operands) I n s t r c t i o n [ 2 6 ] e m e m t o R e g O p e m R e g r e s l t I n s t r c t i o n [ 2 6 ] e m e m t o R e g O p e m R e g r e s l t I n s t r c t i o n I n s t r c t i o n [ ] I n s t r c t i o n [ ] I n s t r c t i o n [ 2 6 ] I n s t r c t i o n [ 5 ] I n s t r c t i o n [ 5 ] Step 2:. Sorce registers are read from the register file 2. Control nit ses the opcode to activate nits. = set based on opcode 2 I n s t r c t i o n [ 5 ] 6 2 e t e n d r e s l t r e s s 25 I n s t r c t i o n Step :. ALUSrc = I n s t r c t i o n [ ] I n s t r c t i o n [ ] I n s t r c t i o n [ 2 6 ] I n s t r c t i o n [ 5 ] I n s t r c t i o n [ 5 ] 2. Control line vales of ALU set by ALU-control 2. ALU performs desired operation on inpt data 2 I n s t r c t i o n [ 5 ] 6 2 e t e n d r e s l t r e s s 26 Eample: R-type Instrction (step : Write reslt in destination register) Why single-cycle implementation is not sed? I n s t r c t i o n I n s t r c t i o n [ ] Step :. emtoreg = ; RegDst = ; I n s t r c t i o n [ 2 6 ] I n s t r c t i o n [ ] I n s t r c t i o n [ 2 6 ] I n s t r c t i o n [ 5 ] I n s t r c t i o n [ 5 ] e m e m t o R e g O p e m R e g e t e n d r e s l t r e s l t r e s s Assming no delay at adder, sign etension nit, shift left nit, PC, control nit, and UX:! Load cycle reqires 5 fnctional nits: instrction fetch, register access, ALU, data memory access, register access! Store cycle reqires fnctional nits: instrction fetch, register access, ALU, data memory access! R-type instrction cycle reqires fnctional nits: instrction fetch, register access, ALU, register access! Path for a branch instrction reqires fnctional nits: instrction fetch, register access, ALU! Path for a jmp instrction reqires fnctional nit: instrction fetch Using a clock cycle of eqal dration for each instrction is a waste of resorces. 2. Reslt of ALU is written in specified register I n s t r c t i o n [ 5 ]. PC is incremented by 27 28

Topics: A multiple cycle implementation. Distributed Notes

Topics: A multiple cycle implementation. Distributed Notes COSC 22: Compter Organization Instrctor: Dr. Amir Asif Department of Compter Science York University Handot # lticycle Implementation of a IPS Processor Topics: A mltiple cycle implementation Distribted