61C In the News. Processor Design: 5 steps

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1 The Thai floods have already claimed the lives of hundreds of pele, with tens of thousands more having had to flee their homes in Bangkok. On a financial scale too the floods have wreaked havoc Around 25 percent of the world s hard drive manufacturing plants are situated in and around Bangkok 6C In the News Thailand Floods Take Toll on Makers Sylvie Barak //2 Western Digital corp., the world s largest producer of hard disc drives has had to close all its factories in Thailand down completely, as has Toshiba corp. and a number of other smaller HDD makers, leaving the industry with just two months worth of remaining inventory. We epect sales to be lower than epected. As a result, we epect weakness in DRAM prices, a Samsung eecutive said // Fall Lecture #29 CS 6C: Great Ideas in Computer Architecture (Machine Structures) Lecture 29: Single- Cycle CPU path Control Part 2 ructors: Mike Franklin Dan Garcia hlp://inst.eecs.berkeley.edu/~cs6c/fa // Fall Lecture #29 2 Review: Processor Design 5 steps Step : Analyze instrucuon set to determine datapath Meaning of each instrucuon is given by register transfers path must include storage element for ISA registers path must support each register transfer Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the Step : Analyze implementauon of each instrucuon to determine se[ng of control points that realizes the register transfer Step 5: Assemble the control logic // Fall Lecture #29 3 Processor Design: 5 steps Step : Analyze instrucuon set to determine datapath Meaning of each instrucuon is given by register transfers path must include storage element for ISA registers path must support each register transfer Step 2: Select set of datapath components & establish clock methodology Step 3: Assemble datapath components that meet the Step : Analyze implementauon of each instrucuon to determine se[ng of control points that realizes the register transfer Step 5: Assemble the control logic Fall Lecture #29 Old Value Rs, Rt, Rd, Op, Func Register- Register Timing: One Complete Cycle (Add/Sub) rucuon Access Time Old Value Delay through Control Logic Old Value RegWr Old Value Register File Access Time, B Old Value Delay Old Value RegWr Rd Rs Rt Register Write Occurs Here // Fall Lecture #29 5 3c: Logical Op (or) with Immediate R[rt] = R[rs] ZeroEt[] 6 bits 5 bits 5 bits 5 RegDst immediate Wri/ng to Rt register (not Rd)!! What about Rt Read? ZeroEt Src // Fall Lecture #29 7

2 3d: Load OperaUons R[rt] = Mem[R[rs] + SignEt[]] Eample: lw rt,rs, 6 bits 5 bits 5 bits RegDst Rw Ra Rb // Fall Lecture #29 9 Src MemtoReg 3e: Store OperaUons Mem[ R[rs] + SignEt[] ] = R[rt] E.: sw rt, rs, 6 bits 5 bits 5 bits RegDst MemtoReg Src In WrEn 3e: Store OperaUons Mem[ R[rs] + SignEt[] ] = R[rt] E.: sw rt, rs, 6 bits 5 bits 5 bits RegDst MemtoReg Src In WrEn 3f: The Branch rucuon 6 bits 5 bits 5 bits beq rs, rt, mem[] Fetch the instrucuon from memory Equal = R[rs] == R[rt] Calculate branch condiuon if (Equal) Calculate the net instrucuon s address = + + ( SignEt() ) else = + path for Branch OperaUons beq rs, rt, 6 bits 5 bits 5 bits path generates condiuon (Equal) Address Equal Already have mu, adder, need special sign etender for, need equal compare (sub?) = ruc2on Fetch Unit including Branch if (Zero == ) then = + + SignEt[]* ; else = + Equal MUX ctrl rucuon<:> How to encode? Direct MUX select? Branch inst. / not branch inst. Let s pick 2nd Uon zero? MUX Fall Lecture #27 Q: What logic gate? 2

3 Pu[ng it All Together:A Single Cycle path <2:25> <:2> <:5> Rs Rt Rd RegDst <:5> Imm Equal ruction<:> Src MemtoReg = In WrEn path Control Signals : zero, sign src: regb; immed : ADD, SUB, OR RegDst Address & Equal Rw Ra Rb : write memory MemtoReg: ; Mem RegDst: rt ; rd RegWr: write register MemtoReg // Fall Lecture #29 Src In WrEn Given path: RTL à Control rucuon<:> <26:> <:5> Op Fun <2:25> <:2> Rd <:5> <:5> Imm RegWr RegDst Src Rt Rs Control MemtoReg RTL: The Add rucuon 6 rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits add rd, rs, rt MEM[] Fetch the instrucuon from memory R[rd] = R[rs] + R[rt] The actual erauon = + Calculate the net instrucuon s address DATA PATH // Fall Lecture #27 7 Fall Lecture #29 8 rucuon Fetch Unit at the Beginning of Add Fetch the instrucuon from rucuon memory: rucuon = MEM[] same for all instrucuons Address rucuon<:> Fall Lecture #29 9 Single Cycle path during Add 6 rs rt rd shamt funct R[rd] = R[rs] + R[rt] RegDst= Rd RegWr= Rs Rt =+ Rw Rt Ra Rb = instr fetch unit Rs Rt Rd Imm zero =ADD MemtoReg= Src= rucuon<:> <2:25> = In <:2> = <:5> WrEn <:5> Fall Lecture #29 2 3

4 rucuon Fetch Unit at End of Add = + Same for all instrucuons ecept: Branch and P&H Figure.7 =+ Address Fall Lecture #29 2 Fall Lecture #29 22 Summary of the Control Signals (/2) inst!register Transfer! add!r[rd] R[rs] + R[rt]; +!!src=regb, = ADD, RegDst=rd, RegWr, = +!! sub!r[rd] R[rs] R[rt]; +!!src=regb, = SUB, RegDst=rd, RegWr, = +! ori!r[rt] R[rs] + zero_et(imm); +!!src=im, Et= Z, = OR, RegDst=rt,RegWr, = +! lw!r[rt] MEM[ R[rs] + sign_et(imm)]; +!!src=im, Et= sn, = ADD, MemtoReg, RegDst=rt, RegWr,! = +! sw!mem[ R[rs] + sign_et(imm)] R[rs]; +!!src=im, Et= sn, = ADD,, = +! beq!if (R[rs] == R[rt]) then + sign_et(imm)]!else +!! = br, = SUB! // Fall Lecture #27 23 Summary of the Control Signals (2/2) See func We Don t Care :- ) Appendi A add sub ori lw sw beq RegDst Src MemtoReg RegWrite ite nsel <2:> Add Subtract Or Add Add Subtract 6 R- type rs rt rd shamt funct add, sub I- type // Lecture #27 Fall 2? ori, lw, sw, beq Boolean Epressions for Controller Controller ImplementaUon RegDst = add + sub Src = ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw ite = sw nsel = beq = = lw + sw [] = sub + beq (assume is ADD, SUB, OR) [] = or! Where:! rtype = ~ 5 ~ ~ 3 ~ 2 ~ ~, ori = ~ 5 ~ 3 2 ~ lw = 5 ~ ~ 3 ~ 2 sw = 5 ~ 3 ~ 2 beq = ~ 5 ~ ~ 3 2 ~ ~ = ~ 5 ~ ~ 3 ~ 2 ~! How do we implement this in gates? code func AND logic add sub ori lw sw beq OR logic RegDst Src MemtoReg RegWrite ite nsel [] [] add = rtype func 5 ~func ~func 3 ~func 2 ~func ~func sub = rtype func 5 ~func ~func 3 ~func 2 func ~func! // Fall Lecture #27 25 // Fall Lecture #27 26

5 Peer rucuon ) We should use the main to compute =+ in order to save some gates 2) The is inacuve for memory reads (loads) or writes (stores). 2 a) FF b) FT c) TF d) TT e) Help! Summary: Single- cycle Processor Five steps to design a processor:. Analyze instrucuon set à Processor datapath Control 2. Select set of datapath components & establish path clock methodology 3. Assemble datapath meeung the. Analyze implementauon of each instrucuon to determine se[ng of control points that effects the register transfer. 5. Assemble the control logic Formulate Logic EquaUons Design Circuits // Fall Lecture #27 28 Input Output Bonus Slides How to implement Single Cycle path during New = { [..28],, } = RegDst = RegWr = Rs Rt = - bit Registers = Src = rucxon Fetch Unit In Rt Rs Rd Imm TA26 MemtoReg = Zero = rucuon<:> <2:25> <:2> WrEn <:5> <:5> <:25> Fall Lecture #29 29 = Fall Lecture #27 3 Single Cycle path during = rucuon<:> =? rucxon Fetch Unit RegDst = RegWr = Rs Rt = Rt Rs Rd Imm TA26 MemtoReg = Zero = - bit Registers WrEn New = { [..28],, } Src = In = Fall Lecture #27 <2:25> <:2> <:5> <:5> <:25> ruc2on Fetch Unit at the End of New = { [..28],, } Zero n_mux_sel rucuon<:> How do we modify this to account for s? Fall Lecture #27 5

6 ruc2on Fetch Unit at the End of New = { [..28],, } Zero n_mux_sel TA 26 (MSBs) rucuon<:> Query Can Zero sull get asserted? Does need to be? If not, what? Fall Lecture #

Computer Engineering Department. CC 311- Computer Architecture. Chapter 4. The Processor: Datapath and Control. Single Cycle

Computer Engineering Department CC 311- Computer Architecture Chapter 4 The Processor: Datapath and Control Single Cycle Introduction The 5 classic components of a computer Processor Input Control Memory