Multi-Voltage Floorplan Design with Optimal Voltage Assignment

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1 Mlti-Voltage Floorplan Design with Optimal Voltage Assignment ABSTRACT Qian Zaichen Department of CSE The Chinese University of Hong Kong Shatin,N.T., Hong Kong In this paper, we stdy the mltiple voltage assignment (MVA) problem nder timing constraints in floorplanning, which is generally an NP-hard problem. We will present an effective vale-oriented branch-and-bond based algorithm to solve it optimally in a reasonable amont of time. A convex cost integer dal network flow approach is sed to obtain a feasible pper bond soltion, while a lower bond is obtained by a linear relaxation of a general formlation of the problem. We then adopt a vale-oriented breadth-first branch-and-bond method with pper and lower bonds as described above to search for the optimal soltion. Favorable reslts can be obtained in comparison with previos methods sing a general linear programming solver. We integrate this algorithm into a mlti-stage floorplanner. At the first stage, an initial floorplan is obtained by simlated annealing sing the convex cost integer dal network flow approach as an evalator. We then perform optimal voltage assignment to this initial floorplan. Finally, a post-processing step is done to modify the floorplan slightly to optimize the power network roting resorce before invoking once more the optimal voltage assignment step at the end. Experimental reslts show that we can improve over the most pdated work on this problem [7] by frther redcing 6% of power consmption while maintaining the performance on other factors Categories and Sbject Descriptors B.7. [Integrated Circit]: Design Aid Layot General Terms Algorithms, Performance The work described in this paper was partially spported by a grant from the Research Concil of the Hong Kong Special Administrative Region, China (Project No ). Permission to make digital or hard copies of all or part of this work for personal or classroom se is granted withot fee provided that copies are not made or distribted for profit or commercial advantage and that copies bear this notice and the fll citation on the first page. To copy otherwise, to repblish, to post on servers or to redistribte to lists, reqires prior specific permission and/or a fee. ISPD 09, March 9 April, 009, San Diego, California, USA. Copyright 009 ACM /09/03...$5.00. Evangeline F.Y. Yong Department of CSE The Chinese University of Hong Kong Shatin,N.T., Hong Kong fyyong@cse.chk.ed.hk Keywords mlti-voltage assignment optimization branch-and-bond. INTRODUCTION Mltiple Spply Voltages (MSV) is developed to deal with the power problem in today s high performance circits. In MSV designs, modles lying on critical paths can be operated at higher voltage levels to meet timing constraints, while modles on noncritical paths will be operated at lower voltages to redce power consmption withot affecting the circit performance. However, a nmber of isses mst be handled first before this approach becomes practical, for example, voltage selection and assignment, MSV-aware floorplanning and placement, etc. Among them, Mltiple Voltage Assignment (MVA) is an important problem that has attracted the attention of many researchers in the past few years. Given a netlist of modles which can be operated at several different spply voltages, the MVA problem is to assign a spply voltage to each modle to minimize the total power consmption while satisfying the circit s timing constraints. In MSV designs, the timing slacks of the modles are traded for power saving nder a performance garantee of the circit. Therefore, an efficient voltage assignment method is desirable to minimize power consmption nder timing constraints. Besides, it is absoltely beneficial to consider this mlti-voltage design isse at the floorplanning level so that those important physical information like interconnect delay, modle location (for estimating the power network roting resorces) and area overhead de to level shifters, etc. can be taken into accont in an early stage. A nmber of previos works were on these MSV related problems. MSV was considered at varios design stages, inclding the floorplanning and placement stage [3, 4], and the post-floorplanning and post-placement stage [, 5, 6]. In [9], Lee et al. sed a dynamic programming based algorithm to solve the voltage assignment problem. In [7], Ma et al. transformed this power assignment problem to a convex cost integer dal network flow problem [8] which can be solved in polynomial time. However, none of them can prodce optimal soltion for the problem in general. Lee et al. [] formlated the problem as a mixed integer linear program (MILP), and sed a general linear programming solver to obtain optimal soltion bt the rntime can be excessively long. Chang and Pedram [] proved that the MVA problem was an NP-hard problem, even if each modle had only two voltage choices (the two choices cold be different for different modles thogh). In this paper, we will first develop a techniqe that can 3

2 solve the general voltage assignment problem nder timing constraint optimally in a reasonable amont of time, assming that the delay-power crve for each modle is convex []. Given a floorplanning reslt containing a netlist of modles, a nmber of working voltage levels for each modle with the corresponding delays (delay choices can be continos or discrete in the real or integral domain), interconnect delays and a timing constraint T, a voltage level will be assigned to each modle sch that the maximm power saving is achieved withot violating the timing constraint. Secondly, we develop a floorplanning strategy with this optimal voltage assignment techniqe that can perform better on power saving than the most pdated work [7] on the NSV-driven floorplanning problem while maintaining the performance on other factors. In section, we present a general formlation of this voltage assignment problem. In section 3, we show how to solve this problem optimally by sing a vale-oriented branchand-bond based algorithm. In section 4, we integrate this optimal voltage assignment with floorplanning. In section 5, we show the experimental reslts.. PROBLEM FORMULATION We are given a set of n modles m, m,..., m n with areas and aspect ratios. Each modle m i is given k i choices of spply voltage v q i, for q ki, and the corresponding delays d q i. We are also given the delay and power for one level shifter that mst be inserted in a signal line connecting a low voltage cell to a high voltage cell and a timing reqirement T cycle. (This is called the clock cycle time and is an pper bond for all critical path delays.) In the following, we define the mlti-voltage floorplanning problem. Definition.. Mlti-voltage Floorplanning - Given a netlist of modles, each of which has mltiple choices of spply voltages and corresponding delays, and a clock cycle, generate a floorplan with a voltage assignment to each modle sch that the timing constraint is satisfied and a weighted sm of the total power consmption (de to cells and level shifters), power network roting resorces, area and wire length is minimized. The power-delay trade-off in m i is represented by a delaypower crve (DP Crve), {(d i, p i),(d i, p i),...(d k i i, pk i i )}, where each pair (d q i, pq i ) for q =,,..., ki is the corresponding delay and power consmption when m i is operated at v q i. Note that each d q i and pq i can be any real or integer nmber as long as the DP-Crve (after piecewise linearization) is convex. In or formlation, we se binary variable i(q) to represent whether m i works at voltage p q i : i(q) = if mi works at voltage p q i and i(q) = 0 otherwise. Therefore, Σ k i q=i(q) =. We denote a netlist by a directed acyclic graph (DAG), G = (V, E). Each vertex i V denotes a modle m i, while each directed edge (i, j) E denotes an interconnect from m i to m j. In this DAG, each vertex is associated with a DP crve representing the power-delay tradeoff of the corresponding modle, while each edge is attribted with a wire delay. For each edge e(i, j), we se a binary variable LS(i, j) to represent whethor a level shifter is needed. Let ϕ and ρ denote the power consmption and delay respectively of one 3 (a) (b) Figre : DAG Transformation level shifter. 0 if a level shifter is not needed on e(i, j) LS(i, j) = if a level shifter is needed on e(i, j) The wire delay of e(i, j) is compted as w(i, j) = δ l(i, j) where w(i, j) and l(i, j) are the wire delay and wire length of e(i, j) and δ is a constant scaling factor. Now we can define the voltage assignment problem as follows: Definition.. Voltage Assignment Problem - Given a clock cycle time T cycle and a DAG, G = (V, E), where each vertex v i V is associated with a set of binary variables { i(), i()..., i(k i)} that indicate the working voltage of v i and each edge e(i, j) is associated with a wire delay w(i, j) and a binary variable LS(i, j) to indicate the existence of a level shifter on e(i, j), select a proper vale from {0, } to each i(q) where q =,,..., k i for every v i sch that Σ k i q=i(q) = for each vi, the total power consmption de to the cells and level shifters are minimized and the timing constriant is satisfied. For formlation simplicity, we will transform G = (V, E) into a new graph Ḡ = ( V, Ē) by adding a virtal modle m 0 as well as a set of virtal edges E 0. Hence V = V {m 0} and Ē = E E0. The set E0 contains (i) edges e(0, i) for all m i which have no incoming edges in G and, (ii) edges e(i,0) for all m i which have no otgoing edges in G. An example is shown in Figre in which sb-figre (a) is the DAG G and sb-figre (b) is the corresponding Ḡ. We will pt 0(q) = 0 q and pt w(i, j) = 0 and LS(i, j) = 0 e(i,j) E 0. According to the definition and notation above, the voltage assignment problem can be easily formlated into the following mathematical program. Minimize : Sbject to : Σ vi V Σ k i q= pq i i(q) + Σ e(i,j) ELS(i, j) ϕ 4 5 (a) Σ k i q=i(q) = vi V (b) Σ e(i,j) c (Σ k i q= dq i i(q) + ρls(i, j) + w(i, j)) T cycle c Φ k (c) { 0 ki LS(i, j) = q= vq i i(q) k j q= vq j j(q) otherwise (d) i(q) {0, }, q =,,..., k i, v i V (e) 4

3 () () 0 () 3 () 0 3 ( k ) 0 ( k ) () () 0 ( k ) 0 S S S k3 S O () 0 () ( k ) 0 () () 0 () 0 3 () 0 3 ( k ) 0 ( k ) 3 3 S k () 0 () 0 ( k ) Figre : Sample of Branch-and-Bond Method where Φ k is the set of all cycles in Ḡ. The objective fnction (a) is the sm of all modles and level shifters power. Constraint (b) is sed to ensre that each modle m i is working at only one voltage level. Constraint (c) is the timing constraint that reqires the delay of every path to be smaller than the clock cycle. 3. A VALUE-ORIENTED BRANCH-AND-BOUND ALGORITHM In this section, we will show how to solve the MVA problem optimally. As we mentioned before, the MVA problem is an NP-hard problem, so we developed a branch-andbond based techniqe to solve it. We will first describe the basic vale-oriented branch-and-bond algorithm and then explain how to compte the pper and lower bonds. The branch-and-bond approach solves problems by searching sccessive partitions of the soltion space. As sal, we will describe the searching process by a search tree in which an internal node represent a set of soltions while a leaf node represent a single soltion. 3. Branching Rles In or searching approach, we visit different parts of the soltion space by confining the vale of some selected variables. An example is shown in Figre. Node zero represents the set of all soltions (an optimal one exists for the original problem). In the first iteration, we may select a modle m i (we will describe the selection criteria in the following) and branch to k i children nodes, which represent the soltion space of k i different sbproblems where k i is the nmber of spply voltage choices of modle m i. W.l.o.g., we assme that this m i is m in the following discssion. In figre, S is the first sch sbproblem which is obtained by adding the following constraint () to constraints (a)-(e): () =, () = 0,..., (k ) = 0 () Similarly, sbproblem S is obtained by adding to constraints (a)-(e), () and a new constraint (3): 3() =, 3() = 0,..., 3(k 3) = 0 (3) In this way, we will branch ot to many sbproblems and search the whole soltion space of the original problem. Next, we will discss selection criteria for braching ct. In [7], the athor presented an algorithm that can give an optimal soltion for the MVA problem when the voltage choices are continos. Bt this may not be tre in many real applications. For example, in a problem with two spply voltage choices for each modle, e.g., modle m i has two choices (p i,d i ) and (p i,d i ), the approach in [7] may retrn a delay vale d optimal i for m i where d i d optimal i d i (assming d i < d i). Notice that if d optimal i is eqal to d i or d i exactly, we say that the soltion is feasible; otherwise, it is infeasible. Therefore, to branch ot from a node, we will select the modle with the lowest index whose soltion retrned by [7] is infeasible. For instance, given a MVA problem, we first solve it sing the approach in [7] and obtain a soltion {(p, d ),(p, d ),..., (p k, d k)} for modle m, m,...m k, we will check starting from i = to k whether modle m i can work at (p i, d i ), and select the first modle whose soltion is infeasible to branch ot to the children nodes. After selecting one modle m i, we will constrct k i sbproblems with additional constraints to confine the voltage level of m i where k i is the nmber of voltage choices for m i. 3. Upper Bonds For a branch-and-bond based algorithm, tight pper and lower bonds are important for efficiency. As we mentioned above, the approach in [7] may prodce infeasible soltion, becase the convex cost integer dal network flow algorithm may retrn voltage vales lying between two feasible voltage levels. Table : NUMBER OF CELLS WITH INFEASI- BLE VOLTAGE LEVELS n0 n30 n50 n00 n00 n300 No. of cells with infeasible voltage We have collected some statistics (Table ) that shows the nmber of infeasible assignments voltages retrned by the approach in [7]. Since the nmber of infeasible voltages is relatively small, one good and straight forward way to obtain an pper bond for the searching process is to choose a feasible soltion as close as possible to the soltion retrned by [7]. Given a soltion {(p, d ),(p, d ),...(d n, d n)} for modles m, m,...m n, n is the nmber of modles, if some (p i, d i ) for i n is not feasible, we can se the largest possible d i in (p i, d i) sch that (p i, d i) {(p i,d i ),(p i,d i),...(p k i i, dk i i )} and satisfying d i d i as the voltage level for m i. After assigning spply voltages to all modles, we will check for each net (i, j), whether a level shifter shold be inserted. We will then se the sm of the power consmptions de to the modles and the level shifters as an pper bond. Note that we will do this comptation whenever a new node in the search tree is visited and will pdate the pper bond (which is global) if a better one is fond. 5

4 3.3 Lower Bonds The lower bond is obtained by a linear relaxation of the problem. Before we explain it, let s rebild the formlation of Problem (). Let k be the total nmber of spply voltages among all the modles. For example, if we have three modles m, m and m 3 where m has only one spply voltage choice p =.0v, m has two, p =.0v and p =.v, and m 3 has two, p 3 =.v and p 3 =.4v, then we will have k = 4 different voltage levels.0v,.v,.v,.4v for all the modles. Now, we will sbstitte each k i in Problem () by k and replace i(q) for q =,,..., k i by i(q) for q =,,..., k. For the above example, before this step, modle m 3 will have k 3 = voltage choices, and after this step, k = 4 bt 3() and 3(3) are always zero becase they represent.0v and.v respectively and m 3 cannot work at these two voltages. In the linear relaxation, we first replace (e) by 0 i(q), q =,,..., k, v i V Then we can sbstitte (d) by LS(ij) i(q ) + j(q ) e(i, j) E, q q s.t. (0 q, q k) (q > q ) (4) So Problem () becomes the following after this linear relaxation step: Minimize : Sbject to : Σ vi V Σ k q=p q i i(q) + Σ e(i,j) ELS(i, j) ϕ (5a) Σ k q= i(q) = v i V (5b) Σ e(i,j) c (Σ k q=d q i i(q) + ρls(i, j) + w(i, j)) T cycle c Φ k (5c) LS(i, j) i(q ) + j(q ) e(i, j) E, q q s.t. (0 q, q k) (q > q ) (5d) 0 LS(i, j), e(i,j) E (5e) 0 i(q), q =,,..., k, v i V (5f) Note that the optimal soltion to Problem () is inclded in the soltion space of Problem (5), so the power consmption of the optimal soltion of (5) is a lower bond for or Problem (). Problem (5) is a simple linear program which can be solved easily with the simplex algorithm in polynomial time to give a lower bond to or original problem. 3.4 Prning Rles and Vale-Oriented Searching Rles With the pper and lower bonds obtained above, we can constrct or prning rles. Some nodes with their sbtrees together will never contribte an optimal soltion, and good prning rles help to find sch nodes to redce rntime. If a node is infeasible, that is, we cannot find a feasible soltion satisfying the timing constraint even assming a continos domain for the modle voltages (this can be verified by invoking the approach in [7]), it will be prned. Besides, if a node s lower bond is greater than or eqal to the global pper bond, it will also be prned. This is correct since we can never find a better soltion by traversing into its sbtree. With the above bonds and prning rles, we can search the soltion space faster. Or vale-oriented branch-andbond searching algorithm is divided into ronds. In each rond, we set a target which is sed as a threshold to decide whether a node shold be visited in this rond. For example, in the first rond, the target will be compted as: target = α(o pbond + O lowbond ) where 0 α is a constant (set to 0.6 in or experiments), and O pbond and O lowbond are the pper and lower bonds of the original problem (node 0 in Figre ). When we reach a node S, we will check whether S lowbond < target where S lowbond is the lower bond at S. If so, we will contine to visit the sbtree of S; otherwise, this node S will be marked and will not be visited in this rond (may be visited in the following ronds). After one rond, the vale of target will be pdated as target = target+c where C is a constant (set to 5% of O pbond in or experiments). Note that a sbtree which is explored in a previos rond will not be repeatedly visited in any sbseqent ronds. In general, this valeoriented searching strategy will search nodes with smaller lower bonds in earlier ronds and we can pper bond the deviation of a soltion obtained from sch vale-oriented search from the tre optimal soltion. This idea is derived from the target-oriented brand-and-bond algorithm in [0], In or vale-oriented branch-and-bond algorithm, There are two conditions nder which we can stop searching: (i) a feasible soltion is fond at a node of which the objective fnction vale is eqal to the smallest lower bond (obtained by the linear relaxation) ever seen dring the search; (ii) all possible nodes are visited and searched. Ptting all the above steps together, we have the following psedo-code for or vale-oriented brand-and-bond algorithm: Algorithm VALUE-ORIENTED BRANCH-AND- BOUND : // Procedre to find optimal soltion to the voltage assignment problem : P MV A //soltion to the mltiple voltage assignment problem assming continos domain for voltage choices 3: pool = // a qee for searching nodes 4: basket = // a stack for searching nodes 5: node 0 = constrct first node from P MV A 6: pt node 0 into pool 7: while (pool is not empty) do 8: node x = get a node from pool 9: psh node x into basket 0: while (basket is not empty) do : node x = Pop node ot of basket : if (node x can be ct) then 3: contine 4: end if 5: if (node x can be stored in the pool for sbseqent iterations) then 6: store node x in pool 7: contine 8: end if 9: branch at node x 0: psh all sbproblems into basket : end while : end while 6

5 4. FLOORPLANNING We integrated the above optimal voltage assignment algorithm into the floorplanning step. Or floorplanner is mltistage. In the first stage, we will invoke the simlated annealing based floorplanner in [4] to give an initial floorplan. After an initial floorplan is generated, we will perform or optimal voltage assignment on it. Finally, a post-processing step will be performed to incrementally change the floorplan to redce the network roting resorces before a final optimal voltage assignment is performed once again. The postprocessing step is done by invoking an ordinary simlated annealing based floorplanner which will move blocks arond to minimize an objective fnction which is a weighted sm of area, wire length and power network roting resorces (no power consmption in the cost fnction). After this fast floorplanning step, the timing constraint may be violated, so we need to perform once again the optimal voltage assignment to assign a final voltage to each block. The floorplanner [7] is sed to prodce the initial floorplan becase their approach is very similar in natre with or optimal voltage assignment method and the second stage ths will not make a large nmber of block voltage changes, which, basically, will invalidate and waste the optimization done in the first stage. To verify this point, we have done a simple experiment to compare the reslts of the minimm cost network flow approach sed in [7] and or optimal voltage assignment method. We randomly generate 0 floorplans for each benchmark and compare or approach (called VOBB) and [7] in terms of average power consmption and the nmber of modles with different voltage assignments. The reslts are shown in Table. 5. EXPERIMENTAL RESULTS We implemented or algorithms in the C programming langage and experimented on a PC with an Intel.6GHz CPU and GB memory. We have done two sets of experiments as described below. 5. OPTIMAL VOLTAGE ASSIGNMENT In this set of experiments, we want to compare or optimal voltage assignment method with the most pdated previos work [] that also tried to solve the same problem optimally sing MILP. A general linear programming solver called lp solve is sed in []. The reslts are shown in Table 3. The rn time limit for each data set is ten hors, and an asterisk indicates that the program does not rn to the end after 0 hors (so, the soltion is sboptimal). Or techniqe can obtain optimal soltions in a reasonable amont of time for most testbenches and has ot-performed [] qite a lot. Dring the experiments, we fond that the rntime depends more on the complexity of the circit rather than the nmber of modles. The word complexity here means the total nmber of constraints (c). In the experimental reslts, the rntime for n00 is even longer than that for n300. For larger problem instances, we can set a threshold difference between the global pper bond and the lower bond at the end of each rond e.t. the target, dring the seaching process. When the difference is smaller than the threshold, we will accept the pper bond as the final reslt. We have also tried to rectify (c) sing edge-based timing constraints [], bt we fond that this new formlation did not have any advantages over or formlation. 5. FLOORPLANNING RESULTS In this set of experiments, we compare the reslts of or mlti-stage floorplanner with those in [7]. The reslts are shown in Table 4. We can see that or floorplanner can ot-perform [7] in almost all aspects except having arond 0.8% more deadspaces. Or floorplanner can give a floorplan with abot 6% more power saving sing abot 50% less level shifters. 6. CONCLUSION In this paper, we proposed a method to solve the Mltiple Voltage Assignment problem optimally, and integrated it into a floorplanner. We show that the general MVA problem nder timing constraints can be solved optimally by or vale-oriented branch-and-bond based algorithm in a reasonable amont of time, by constrcting proper pper bonds and lower bonds. We embed this techniqe into a floorplanner to prodce mlti-voltage aware floorplans. Experimental reslts show that or floorplanner can save abot 6% more power compared with the most pdated reslts on this problem sing arond 30% less level shifters. 7. REFERENCES [] W.R. Davis, A-.M. Sle and H-. Ha, Mlti-Parameter Power Minimization of Synthesized Datapaths, Proceedings of the ISVLSI, 004. [] W.-P.Lee, H.-Y. Li and Y.-W. Chang, An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning, Proceedings of International Conference on Compter-Aided Design, 007. [3] J.H, Y.Shin, N.Dhanwada, and R. Marclesc, Architecting Voltage Islands in Core-based System-on-a-chip Designs, Proceedings of International Symposim on Low Power Electronics and Design, pp.80-85, 004 [4] Q. Ma and Evangeline FY. Yong, Voltage Island-Driven Floorplanning, Proceedings of International Conference on Compter-Aided Design, pp , 007. [5] W.-K. Mak and J.-W. Chen, Voltage Island Generation nder Performance Reqirement for SoC Designs, Proceedings of Asia and Soth Pacific Design Atomation Conference, 007. [6] H. W, D.F. Wong, and I.-M. Li, Timing-Constrained and Voltage-Island-Aware Voltage Assignment, Proceedings of Design Atomation Conference, pp.49-43, 006. [7] Q. Ma and Evangeline FY. Yong, Network Flow Based Power Optimization Under Timing Constraints in MSV-Driven Floorplanning Proceedings of International Conference on Compter-Aided Design, 008. [8] R.K Ahja, D.S. Hochbam, and J.B. Orlin, Solving The Convex Cost Integer Dal Network Flow Problem, management Science, 49(7): , Jly 003. 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6 Table : VOLTAGE ASSIGNMENT COMPARISONS BETWEEN VOBB AND [7] Testbenches Power Ratio Average No. of Blocks [7] VOBB with Different Voltages n %.7 n %.9 n % 7.8 n % 9.9 Table 3: COMPARISONS BETWEEN VOBB AND [] Power Rn time Testbenches VOBB [] VOBB [] n s 0.0 s n s 0 h n s. m n00 33 * m 0 h n00 *99 *634 0 h 0 h n * m 0 h Average Table 4: FLOORPLANNING RESULT COMPARISONS BETWEEN OUR VOBB-BASED FLOORPLAN- NER AND [7] Data Max Power Power Cost with Power Saving Power Network Level Shifter Dead Space Wire Set (MaxP) Level Shifters (P) (%) Roting Resorces Nmber (%) Length VOBB [7] VOBB [7] VOBB [7] VOBB [7] VOBB [7] VOBB [7] n n n n n n Average