CSE Computer Architecture I
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1 Single cycle Conrol Implemenaion CSE 332 Compuer Archiecure I l x I Lecure 7 - uli Cycle achines i i [ ] I I r l ichael Niemier Deparmen of Compuer Science and Engineering I ] i X.S. Hu 5- X.S. Hu 5-2 How o Deermine Cycle Lengh?! Calculae cycle ime assuming negligible delays excep: " memory (2ns), ALU and adders (2ns), regiser file access (ns) " R-ype: max {mem + RF + ALU + RF, Add} = 6ns " LW: max{mem + RF + ALU + mem + RF, Add} = 8ns " SW: max{mem + RF + ALU + mem, Add} = 7ns " BEQ: max{mem + RF + ALU, max{add, mem + Add}} = 5ns Some Observaions! Daapah: " How many imes is each componen used during an insrucion execuion? Once " Componens can be combined by overlapping differen insrucion ypes # Regiser file by all insrucion ypes #How abou ALU? # How abou sign-exension uni?! Conrol: " For each ype of insrucion, idenify conrol signals for each pah componen involved " Conrol signals are generaed from he insrucion opcode (insr[3:26]) X.S. Hu 5-3 X.S. Hu 5-4
2 Single-Cycle Implemenaion! Single-cycle, fixed-lengh clock: " CPI = " Clock cycle = propagaion delay of he longes pah operaions among all insrucion ypes " Easy o implemen! Single-cycle, variable-lengh clock: " CPI = " Clock cycle =! (%(ype-i insrucions) * propagaion delay of he ype-i insrucion pah operaions) " beer han he previous one bu impracical o implemen! Disadvanages: " Wha if we have floaing-poin operaions? " How abou componen usage? uliple Cycle Alernaive! Break an insrucion ino smaller seps! Execue each sep in one cycle! Execuion sequence: " Balance he amoun of work o be done, why? " Resric each cycle o use only one major funcional uni, why? " A he end of a cycle # sore values for use in laer cycles, why? # inroduce addiional inernal regisers! The advanages: " Cycle ime is much shorer " Differen insrucions ake differen number of cycles o complee " Allows a funcional uni o be used more han once per insrucion X.S. Hu 5-5 X.S. Hu 5-6 uliple-cycle Implemenaion! Daapah " Componen sharing: ALU, /Daa memory #ALU used o compue address and o incremen PC # used for insrucion and " Addiional elemens: UX s, Insr Regiser, Targe Regiser #If a value needs o be alive during muliple cycles, i should say unchanged during he whole ime.! Conrol: " Needed for each pah elemen during each clock cycle Wha o be Done for Each?!"#$%&'()# *"$+,"!"#$%&+-"./(,) 3.4#"&5/$6 "$2#"! How many cycles should he above ake?! You are he archiec so you decide!! Less cylces => more o be done in one cycle X.S. Hu 5-7 X.S. Hu 5-8
3 Five Sep Execuion. Fech (Ifech): " Fech insrucion a address ($PC) " Sore he insrucion in regiser IR " Incremen PC 2. Decode and Regiser (Decode): " Decode he insrucion ype and read regiser " Sore he regiser conens in regisers A and B " Compue new PC address and sore i in ALUOu 3. Execuion, Address Compuaion, or Branch Compleion (Execue): " Compue memory address (for LW and SW), or " Perform R-ype operaion (for R-ype insrucion), or " Updae PC (for Branch and Jump) " Sore memory address or regiser operaion resul in ALUOu Five Sep Execuion (con d) 4. Access or R-ype insrucion compleion (em/regwrie/emwrie): " memory a address ALUOu and sore i in DR " Wrie ALUOu conen ino regiser file, or " Wrie memory a address ALUOu wih he value in B 5. Wrie-back sep (WrBack): " Wrie he memory conen read ino regiser file! Number of cycles for an insrucion: " R-ype: 4 " lw: 5 " sw: 4 " Branch or Jump: 3 X.S. Hu 5-9 X.S. Hu 5- Some Simple Quesions Sep : Fech! How many cycles will i ake o execue his code? lw $2, ($3) lw $3, 4($3) beq $2, $3, Label #assume branch is no aken add $5, $2, $3 sw $5, 8($3) Label: =2! Wha is being done during he 8h cycle of execuion? Compue memory address: 4+$3! In wha cycle does he acual addiion of $2 and $3 akes place? 6! Use PC o fech insrucion and pu i in he Regiser.! Incremen he PC by 4 and pu he resul back in he PC.! How abou express his in RTL? IR=em[PC], PC=PC+4! Wha is he advanage of updaing he PC now?! Basic principle: do i ASAP! X.S. Hu 5- X.S. Hu 5-2
4 Sep 2: Decode and Regiser! regisers rs and r in case we need hem! Compue he branch address in case he insrucion is a branch! RTL: A = RF[IR[25:2]], B = RF[IR[2:6]], ALUOu = PC +(sign-exend(ir[5-]))<<2! Did we se any conrol lines based on he insrucion ype? Sep 3 Execue ( Dependen)! ALU is performing one of hree funcions, based on insrucion ype! RTL " Reference: ALUOu = A + sign_ex(ir[5:]); " R-ype: ALUOu = A op B; " Branch: if (A=B) hen (PC = ALUOu); X.S. Hu 5-3 X.S. Hu 5-4 Sep 4 RegWrie/em! Loads and sores access memory DR = em[aluou]; or em[aluou] = B;! R-ype insrucions finish RF[IR[5:]] = ALUOu; Sep 5: Wrie-Back! Which ype of insrucion needs his?! RTL RF[IR[2:6]]= DR;! Wha abou all he oher insrucions? X.S. Hu 5-5 X.S. Hu 5-6
5 RTL Descripion: Pu All Togeher () Ifech: -> Decode, IR = em[pc], PC = PC + 4; Decode: ->Execue, A= RF[IR[25:2]], B= RF[IR[2:6]], ALUOu = PC + Sign_Ex(IR[5:]) << 2); Execue: if (opcode=lw) or (opcode=sw) hen -> /RegWrie, ALUOu = A + Sign_Ex(IR[5:]); if (opcode= R-ype ) hen -> /RegWrie, ALUOu = A op B; if (opcode=branch) hen -> Ifech, if (A=B) hen PC= ALUou; if (opcode=jump) hen -> Ifech, PC=PC[3:28] IR[25:] ; RTL Descripion: Pu All Togeher (2) /RegWrie: if (opcode=lw) hen -> WrieBack, DR = em[aluou]; if (opcode=sw) hen -> Ifech, em[aluou] = DR; RF[IR[5:]] = ALUOu, ->Ifech; WrieBack: em[aluou] = DR, ->Ifech; X.S. Hu 5-7 X.S. Hu 5-8 Execuion Sequence Summary A uliple Cycle Daapah Sep name fech decode/regiser fech Acion for R-ype insrucions Acion for memory-reference insrucions IR = em[pc], PC = PC + 4 A =RF [IR[25:2]], B = RF [IR[2:6]], Acion for branches ALUOu = PC + (sign-exend (IR[:-]) << 2) Acion for jumps Execuion, address ALUOu = A op B ALUOu = A + sign-exend if (A =B) hen PC = PC [3:28] compuaion, branch/ (IR[5:]) PC = ALUOu (IR[25:]<<2) jump compleion PC Address Daa or regiser regiser Daa Regiser A Regisers Regiser B Regiser W A B ALU ALUOu access or R-ype RF [IR[5:]] = Load: DR = em[aluou] compleion ALUOu or Sore: em[aluou]= B read compleion Load: RF[IR[2:6]] = DR! Where do we need o inser m s?! Any oher funcional unis? X.S. Hu 5-9 X.S. Hu 5-2
6 uliple Cycle Design! Break up he insrucions ino seps, each sep akes a cycle " balance he amoun of work o be done " resric each cycle o use only one major funcional uni! A he end of a cycle " sore values for use in laer cycles (easies hing o do) " inroduce addiional inernal regisers Exercise: Add a New! Le s ry jal! RTL: PC = (PC+4)[3:] TargeAddr[25:], RF[3] = PC + 4; PC Address [25 2] regiser A [2 6] regiser 2 emdaa Regisers Wrie [5 ] regiser 2 B Wrie [5 ] Wrie 4 regiser 2 3 [5 ] regiser 6 32 Sign exend Shif lef 2 Zero ALU ALU resul ALUOu PC Address Wrie emdaa [25 2] [2 6] [5 ] regiser [5 ] regiser [5 ] regiser regiser 2 Regisers Wrie regiser 2 Wrie 6 32 Sign exend Shif lef 2 A B Zero ALU ALU resul ALUOu X.S. Hu 5-2 X.S. Hu 5-22 Conrol Signals! PC: PCWrie, PCWrieCond, PCSource! : IorD, em, emwrie! Regiser: IRWrie! Regiser File: RegWrie, emoreg, RegDs! ALU: ALUSrcA, ALUSrcB, ALUOp, Implemening he Conrol! Value of conrol signals is dependen upon: " wha insrucion is being execued " which sep is being performed! How o represen all he informaion? " finie sae diagram " microprogramming! Realizaion of a conrol uni is independen of he represenaion used " Conrol oupus: random logic, RO, PLA " Nex-sae funcion: same as above or an explici sequencer X.S. Hu 5-23 X.S. Hu 5-24
7 Finie Sae Diagram 2 address compuaion ALUSrcA = ALUSrcB = ALUOp = Sar fech em ALUSrcA = IorD = IRWrie ALUSrcB = ALUOp = PCWre PCSource = 6 (Op = 'LW') or (Op = 'SW') Execuon ALUSrcA = ALUSrcB = ALUOp= (Op = R-ype) Branch compleion 8 ALUSrcA = ALUSrcB = ALUOp = PCWreCond PCSource = decode/ regiser fech i (Op = 'BEQ') 9 ALUSrcA= ALUSrcB = ALUOp = (Op = J') Jump compleon PCWrie PCSource = 3 (Op = 'LW') access em IorD = ( Op = 'SW') 5 access emwrie IorD = 7 RegDs = RegWrie emoreg = R-ype compleon 4 Wre-back sep RegDs= RegWrie emoreg= X.S. Hu 5-25
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