Concepts Introduced. Digital Electronics. Logic Blocks. Truth Tables

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Marvin Lang
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1 Concepts Introdced Digital Electronics trth tables, logic eqations, and gates combinational logic seqential logic Digital electronics operate at either high or low voltage. Compters se a binary representation since it matches the nderlying electronic states. Rather than referring to voltage levels, designers refer to signals as being asserted (logically tre) or deasserted (logically false). Logic locks Trth Tables logic block is a grop of logic elements that are connected in some way. Logic blocks are categorized into two types. combinational logic - logic system whose blocks do not contain memory and compte the same otpts given the same inpts. seqential logic - logic system that contains memory (state) whose vale depends on the inpts as well as the crrent contents of the memory. trth table is a table sed in logic to specify the otpts for each possible set of inpts, which is sefl for specifying combinational logic since combinational logic otpt only depends on its inpts. For a logic block with n inpts, there are 2 n entries in the trth table.

2 Trth Table Eample ssme D is tre if at least one inpt is tre, E is tre if eactly two inpts are tre, and F is tre only if all three inpts are tre. C D E F Logic Eqations Logic eqations provide a more concise way to specify logic. Logical OR operator for operands and is written as +. The reslt of the operation is called a logical sm. Logical ND operator for operands and is written as. The reslt of the operation is called a logical prodct. Logical not operator for operand is written as or. logic eqation performs logical operations on one or more inpts and prodces a single otpt. Logic Eqations Eample Gates What are the logic eqations for D, E, and F in the previos trth table, where D is tre if at least one inpt is tre, E is tre if eactly two inpts are tre, and F is tre only if all three inpts are tre? D = + + C E = ( C) + ( C) + ( C) F = C gate is a electronic device that implements basic logic fnctions. and or or not ^

3 NOR and NND Gates Logic locks ny logical fnction can be constrcted sing ND gates, OR gates, and inversion (NOT gates). ll logical fnctions can be constrcted with a single niversal gate type, if that gate is inverting. Two common inverting gates are the NOR and NND gates. nor nand Logic blocks are bilt from gates that implement basic logic fnctions. The eample below shows the logic gate implementation of + sing eplicit inverts on the left and bbbled inpts and otpts on the right. + Common Logic locks Decoders Gates connected together with no state elements are called combinational logic as its otpts depend only on its inpts. There are several combinational logic blocks that are commonly sed. decoders mltipleors programmable logic arrays (PLs) 3 decoder is a logic block that has an n-bit inpt and 2 n otpts, where only the ith otpt signal is asserted when the inpt combination represents the binary vale i. The following eample depicts 3-bit decoder and a trth table. This decoder is also called a 3-to-8 decoder since there are 3 inpts and 8 (2 3 ) otpts. Decoder Ot0 Ot1 Ot2 Ot3 Ot4 Ot5 Ot6 Ot Ot7 Ot6 Ot5 Ot4 Ot3 Ot2 Ot1 Ot a. 3-bit decoder b. The trth table for a 3-bit decoder

4 Implementing a 2-to-4 Decoder ltipleors elow is the trth table and logic block for a 2-to-4 decoder. The logic eqations for the trth table are: D0 = D1 = D2 = D3 = mltipleor is a device that selects from dierent inpt vales based on the setting of control lines. The gre below shows the symbol for a two-inpt mltipleor and its implementation with gates on the right. D3 D2 D1 D D0 D1 D2 0 1 C C D3 S S ltipleors in General rray of Logic Elements In general, if there are n data inpts, then there has to be log 2 n selector inpts. mltipleor consists of three parts. decoder that generates n signals, each indicating a dierent inpt vale. n array of n ND gates, each combining one of the inpts with a signal from the decoder. single OR gate that takes as inpt the otpts of the ND gates. any combinational operations are performed on data that is 32 bits wide. We can bild an array of similar logic elements and show that a given operation will occr on a collection of inpts. bs is a collection of data lines treated as one logical signal.

5 rray of Logic Elements Eample Two Level Logic Select Select C C31 C30 ny logic fnction can be written in a canonical form, where every inpt is a tre or complemented variable and there are only two levels of gates, consisting of one level being ND gates and the other level being OR gates. sm of prodcts is a canonical form that employs a logical sm (OR) of prodcts (terms joined sing the ND operator) C0 prodct of sms is a canonical form that employs a logical prodct (ND) of sms (terms joined sing the OR operator). a. 32-bit wide 2-to-1 mltipleor b. The 32-bit wide mltipleor is actally an array of 32 1-bit mltipleors Prodcing Sm of Prodcts from a Trth Table sm of prodcts representation can be prodced from a trth table. logical prodct is all the inpts or their complements when an entry is a 1 or 0, respectively. The sm of prodcts is the logical sm of the prodcts where the otpt is tre. Sm of prodcts for the otpts in the trth table are: D = C + C + C+ C + C + C+ C E = C + C + C F = C C D E F Programmable Logic rray (PL) Programmable logic arrays (PLs) are logic implementations that bild on the sm of prodcts representation. Has two stages of logic: First stage is an array of ND gates to form a set of prodct terms. Second stage is an array of OR gates to form a logical sm of the prodct terms. Prodct terms ND gates OR gates

6 PL Eample Read-Only emory (RO) elow is an eample PL implementing the logic fnction represented by the trth table. When drawing a logic block, dots are sed to indicate the connection between signal, inpt, and otpt lines. C D E F C D E F Read-only memory (RO) is ed at the time the RO is manfactred. RO has a set of inpt address lines and a set of otpts. RO with 2 m addressable entries (height) has m inpt lines. The nmber of bits in each addressable entry is eqal to the nmber of otpt bits (width). RO can encode the logic fnctions associated with a trth table. The entries in the inpt portion of the trth table represents the addresses of the entries of the RO. The contents of the otpt portion of the trth table comprise the contents of the RO. RO is similar to PL, ecept that the RO prodces a fll otpt word for every possible inpt combination (flly decoded). Universal LU Symbol elow is the niversal symbol that is sed to represent a complete LU. a LU operation LU Zero Reslt Overflow Clocks clock is a signal that ocsillates between low and high voltages in a ed period of time. The clock cycle time or clock period is the time between two transitions from a low voltage to high voltage (rising edges) or the time between two transitions from a high voltage to a low voltage (falling edges). Edge-triggered clocking means all state changes occr on the active (rising or falling) clock edge. Falling edge b CarryOt Clock period Rising edge

7 State Elements state element has some type of internal storage and at least two inpts and one otpt. The reqired inpts to a state element are the data vale to be written and the clock signal, which indicates when the data vale is to be written. The otpt from a state element is the vale that was written on a previos cycle. Some state elements are only written when there is an eplicit write signal is active. Synchronos System signal is valid when it is stable (not changing) and the vale will not change again ntil the inpts change. synchronos system is a logic system that employs clocks and data signals are read only when the clock indicates that the signal vales are stable (not changing). In a synchonos system, state elements provide inpts to a combinational logic block and the otpts of the combinational logic are stored in state elements, which occrs only on the active clock edge. State element 1 Combinational logic State element 2 Clock cycle Latches and Flip-Flops Latches and ip-ops are the simplest state elements. The dierence is the point at which the clock cases the state to change. In a clocked latch, the state can change when the clock signal is asserted and in a ip-op, the state is changed only on an active clock edge. Register Files register le of 32-bit vales can be implemented as an array of registers bilt from ip-ops, where each register reqires 32 ip-ops. Typically a register le has at least two read ports and one write port. Read register nmber 1 Read register nmber 2 Register file Write register Write data Write Read data 1 Read data 2

8 SR DR SR - Static Random ccess emory Used in caches. Usally has a single access port that can provide either a read or write access. Reqires 6 transistors per bit to prevent data from being corrpted when read and reqires 4 times the amont of space as compared to DR for each stored bit. Each bit vale is stored in a cell by sing a pair of inverting gates and the vale can be kept indenitely as long as power is applied, which is why SR is called static. SR assess time is abot 5 to 10 times faster than DR. SR is perhaps 20 times more epensive than DR. Synchronos SR (SSR) has a synchronos interface to allow brst transfers, where a clock is sed to transfer sccessive words given only a starting address and length. DR - Dynamic Random ccess emory Used for main memory. Reqires a single transistor per bit, which is lost after being read, so each read reqires that the data be written back. The vale representing a bit is kept in a cell that is stored as a charge in a capacitor that is accessed by the single transistor. DR reqires that the data be refreshed periodically, abot 1% to 2% of the cycles, which is why DR is called dynamic and is accomplished by reading the data and writing it back. Finite State achines The behavior of seqential systems depends on both the inpts and the contents of internal memory and nite state machines (FSs) are sed to describe their behavior. nite state machine consists of: set of states net-state fnction that given the crrent state and crrent inpts determines the net state. n otpt fnction that prodces a set of otpts from: the crrent state only (oore machine) the crrent state and the crrent inpts (ealy machine) The nite state machines we will eamine are synchronos meaning that a new state is compted once per clock cycle. Implementing a Finite State achine FS is implemented with a state register that holds the crrent state and a combinational logic block to compte the net state and the otpts. Combinational logic State register Net state

Instruction register. Data. Registers. Register # Memory data register

Instruction register. Data. Registers. Register # Memory data register Where we are headed Single Cycle Problems: what if we had a more complicated instrction like floating point? wastefl of area One Soltion: se a smaller cycle time have different instrctions take different