Konstruktion av Vippor och Latchar
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1 Konstruktion av Vippor och Latchar Datorarkitektur 1 (1DT038) Fördjupning November 2009 karl.marklund@it.uu.se
2 Om du läser IT (1DT038) är detta material överkurs du bör dock redan vara bekant med hur det går till att konstruera minnesceller (vippor och latchar) mha grindar från kursen i elkretsteori.
3 A simple cominational circuit Q = 1 when at least one of A and B equals 1 Q = 1 when both A and B equal 0 A B Q Q Q = 0 when at least one of A and B equals Q = 0 when at least one of A or B equal 1
4 When Q 0 is true, the bottom NOR-gate actcs like an inverter (no matter the value of S) and Q 1 becomes false... What happens if we change to true here?... which becomes the input to the top NOR-gate Q 1 = true = Q 0 (Q is unchanged) A pair of cross-coupled NOR-gates. Due to the feedback loop, this is no longer a cominational circuit - it s an sequential circuit.
5 What happens if we change back to false again? Asserting R will give Q = false which becomes the input to the bottom NORgate Q = true... which becomes the input to the upper NORgate Q = false
6 Deasserting R won t change anything, Q remains false no matter the value of R. What happens if we change to true here? When both R and S are deasserted, the cross-coupled NOR-gats remembers the values of Q and Q
7 What happens if we change S back to false?... which becomes the input to the top NOR-gate Q = true Asserting S gives Q = false...
8 Again, when both R and S are deasserted, the crosscoupled NOR-gats remembers the values of Q and Q Deasserting S won t change anything...
9 R S Q n+1 Q n Q n Q n ?? Logisim DEMO
10 R S Q n+1 Q n+1 both zero 0 0 Q n Q n Overriding the memory feedback action. What happens if both R and S drops (voltage change is not instanteneous) to zero simultaneously?
11 R drops first resulting in Q = 1 S drops first resulting in Q = 0
12 An example of sequential logic: The output depends not only on the present input but also on the history of the input. R S Q n+1 Q n Q n Q n Restricted If both R and S drops to zero at the same time metastability
13 R S Q Q R S Q n+1 Q n Q n Q n Restricted A SR Latch (Set and Reset Latch) can store 1-bit of data.
14 SR Latch Setting C to 1 will only reset Q if D is 0 at the same time. D Latch D can only function as Set when C (clock/ enable) is true.
15 C D Q n+1 Q n+1 Comment 0 X Q n Q n No Change Reset Set
16 C Q A D Latch (Data Latch) can store 1-bit of data. D Q C D Q n+1 Q n+1 Comment 0 X Q n Q n No Change Reset Set
17 R S Q Q A latch is a sequential device that watches all of its inputs continuously and changes its outputs at any time. SR Latch R S Q n+1 Q n Q n Q n Restricted A flip-flop is a sequential device that samples its inputs and changes its outputs only at times determined by a clocking signal. C D Q Q D Latch / Flip-Flop C D Q n+1 Q n+1 Comment 0 X Q n Q n No Change Reset Set
18 C D Q Q D Latch C D Q n+1 Q n+1 Comment 0 X Q n Q n No Change Reset Set D C Q When the latch is open (C=1) Q follows D (a transparent latch)
19 Changing C back to zero The output Q of the master latch follows input D when clock is high (which closes the slave latch).
20 Changing C back to zero opens the slave latch taking the Q output of the master latch as D input.
21 D C Q Output Q only changes on falling clock edges (non transparent).
22 C D Q n+1 Q n+1 Comment non-falling X Q n Q n No Change Set Reset
23 The triangle indicates an edge-trigged latch a flip flop. C Q A D Flip-Flop The inversion bubble on the clock input indicate a falling-edge triggered flip-flop D Q C D Q n+1 Q n+1 Comment non-falling X Q n Q n No Change Set Reset
24 Logisim DEMO 8 bit D flip-flop register
25 Clock 8 D Flip-Flops used to form a 8 bit register A falling edge trigged D flip-flop C Q D Q
26 Clock goes to high... output remains unchanged
27 Clock falls back to low... output equals input
28 Changing input... does not affect ouput
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