Gate Delay Calculation Considering the Crosstalk Capacitances. Soroush Abbaspour and Massoud Pedram. University of Southern California Los Angeles CA

Transcription

1 Gate Delay Calculation Considering the Crosstalk Capacitances Soroush Abbaspour and Massoud Pedram University of Southern California Los Angeles CA Asia and South Pacific Design Automation Conference 2004 Outline! Motivation! Background! Effective Capacitance Calculation! RC Loads! Coupled Capacitive Loads! Coupled RC Loads! Conclusions 1

2 Motivation! The stage delay in a VLSI circuit consists of the gate propagation delay and wire propagation delay.! This paper focuses on the problem of calculating the gate propagation delay.! For highest accuracy, we most carefully consider the effect of the resistive shielding and the capacitive coupling. Motivation (Cont d)! Because of the complexity of the problem, the simplest way is to ignore:! coupling capacitance between interconnects, and! resistive shielding of the interconnects! We only consider the capacitive loading on cell/gate propagation delay. 2

3 Gate Propagation Delay for Capacitive Loads! In the case of a purely capacitive load, the gate propagation delay is a function of:! input transition time, and! output load.! In commercial ASIC cell libraries, it is possible to characterize various output transition times as a function of the input transition time and output capacitance, i.e., tα = fα( Tin, CL)! α% denotes the percentage of the output transition.! t α is the output delay with respect to the 50% point of the input signal.! f α is the corresponding delay function. Gate Propagation Delay Algorithm: Capacitive Load Draw_Output_Waveform (δ, T in, C L ) 1. For α=10%, 50%, and 90% do t α =Calc_Delay (δ, T in, C L, Table(T in, C L, α)) 2. Draw the output waveform according to above data. Calc_Delay (δ, T in, C L, Table(T in,c L,α)) 1. From Table(T in,c L,α) according to T in and C L, find the 50% input to α% output propagation delay, add δ to this value, and call it t α 2. Return t α 3

4 Resistance Shielding and Effective Capacitance Approach! In VDSM technologies, we cannot neglect the effect of interconnect resistances of the load.! Using the sum of all load capacitances as the capacitive load provides an overly pessimistic approximation. Sum of all capacitive load Resistance Shielding! A more accurate approximation for an n th order load seen by the gate/cell (i.e., a load with n distributed capacitances to ground) is to use a second order RC-π model. RC-π load for effective capacitance algorithms! For efficient and accurate gate delay calculation, we then convert the second order RC-π model into an effective capacitance value and use that value as the output load of the gate. T in Gate /Cell Rπ C 1 C 2 C eff = C 1 + kc 2 where 0 k 1 4

5 Crosstalk Capacitance! As technology scales, the effect of coupling capacitances becomes more noticeable.! Given a complex load with two types of capacitive couplings (loadto-load and input-to-load couplings), one can use moment matching techniques to model the load and the parasitic elements as an RC network (see below).! Notice that the gate propagation delay calculation becomes challenging, potentially requiring large multi-dimensional lookup tables. t in,a t out,a R π,a C (a,b) C 1,a C 1,c C 2,a C 2,c C (b,a) t in,b t out,b R π,b C 1,b C 2,b Outline! Motivation! Background! Effective Capacitance Calculation! RC Loads! Coupled Capacitive Loads! Coupled RC Loads! Conclusions 5

6 Prior Work! C. Ratzlaff, S. Pullela, and L. Pillage, Modeling the RC Interconnect effects in a Hierarchical Timing Analyzer, CICC 1992.! M. Sriram and S. M. Kang, Fast Approximation of the Transient Response of Lossy Transmission Line Trees, DAC 1993.! R. Macys, S. McCormick, A New Algorithm for Computing the Effective Capacitance in Deep Sub-micron Circuits, CICC 1998,.! C.V. Kashyap, C.J. Alpert, A. Devgan, An effective capacitance based delay metric for RC interconnect ICCAD 2000.! S. Abbaspour, M. Pedram, Calculating the effective capacitance for the RC interconnect in VDSM technologies, ASP-DAC A New Effective Capacitance Calculation Algorithm! Consider a unit step voltage source that drives an RC circuit. The current flowing into the RC circuit in Laplace domain is calculated as: C I() s = V() s Y() s = src + 1! By calculating the total charge induced into the capacitance up to time T and equating with the total charge induced into the corresponding effective capacitance, we can write: ( ) T RC C = C(1 e ) eff 6

7 Effective Capacitance Calculation (Cont d)! Similarly, the effective capacitance for an RC-π model load can be written as: ( ktout Rπ C2 C = C + (1 e ) ) C eff 1 2! k is a dimensionless constant! t out is the gate output transition time.! As in Macys work, we define: C1 t Ceff = = out = α β γ ( C + C ) RC π 2 ( C + C )! Based on Macy s output-transition-time and gate-configuration independent table that relates these three parameters, we can rewrite the effective capacitance equation as: C C eff k + C 1 2 β ( 1 e )( 1 ) = γ = α + α Effective Capacitance Calculation (Cont d)! If we replace the output transition time (t out ) by 50% propagation delay we can rewrite the equation as: ( )( ) C eff ' 1 kt β = γ = α + e 1 α C1+ C2! where β is the ratio between the 50% propagation delay and the R π C 2 product.! k t is a fixed value which can be obtained from a lookup table (compiled from circuit simulation results), and which is constant for the calculated α and β. 7

8 Effective Capacitance Calculation (Cont d)! This plot shows k t values for 50% propagation delays for different α and β values in a 0.1µm CMOS technology k t α β' 16 Advantage of The Proposed Equation to Macys Equation! An analytical expression for effective capacitance! Our approach results in a more stable effective capacitance estimation. tout tout t t ( t ) ( t ) C out out out out tout tout eff Hγ = = C C == eff eff C eff = γ C eff t out γ C1 C2 C 1 C2 C + + eff t out t t t k t C k C out out out t out eff t eff H = = = k t kt kt tout Ceff kt Ceff tout kt tout Ceff Ceff kt t C k out eff = = H t γ Ceff tout kt Ceff kt Ceff coeff C 2 '(1 ) k ' eff k t t kt β α e β = kt Ceff α + (1 e kt β ' )(1 α) 8

9 Advantage (Cont d)! This coefficient is always less than 1. Therefore our output transition time equation is less sensitive to parameter error 0.2 coeff α 1 4 β' Gate Propagation Delay Algorithm: RC Load Draw_for_RCπ_Load (T in, Load Parameters) 1. For α=10, 50, and 90 do Find_Transition_Point (T in, C 1, R π, C 2, Table (50%-α%),Table(k t )) 2. Draw output waveform according to the results Find_Transition_Point (T in,c 1,C 2,R π,table(50%-α%), Table(k t )) 1. Guess an initial value for C eff 2. Compute α value (Macys notation) from the load values 3. Obtain t α from Table(50%-α%) based on values of C eff and T in 4. Compute β' from t α and load elements 5. Find k t from Table(k t ) according to α and β' 6. Calculate C eff 7. Find the new value of t α for the obtained C eff from Table(50%-α%) 8. Compare the new t α with the old t α 9. If not within acceptable tolerance, then return to step 4 until t α converges 10. Return t α 9

10 Proof of Convergence! Theorem 1: The iterative algorithm, always converges independently of the initial guess. Furthermore, its solution is unique.! Proof: Because ( β' ) ( β' ) d kt ' d kt dc e ktβ C 2 t ' 2 e k β < C2 dceff dc2 dceff dc = k ' 2 e ktβ' k ' e ktβ' tβ tβ < 1 for ( ktβ') > 0 dc eff! Therefore, d dceff ( β ') (1 ' d k t t C ) t ' 1 e k β C k 2 e β + = C2 < 1 dceff Experimental Results 10

11 Outline! Motivation! Background! Effective Capacitance Calculation! RC Loads! Coupled Capacitive Loads! Coupled RC Loads! Conclusions Problem Statement! Two CMOS drivers, a and b, are given where their corresponding input transition times are t in (a) and t in (b)! δ a and δ b denote the 50% transition points of the input waveforms of driver a and b.! There is a δ=δ b -δ a delay between their input waveforms! Furthermore, the output waveform of drivers a and b are t out (a) and t out (b), respectively.! The objective is to find the output waveforms of the two drivers. 11

12 Problem Statement (Cont d)! In fact, we must solve a nonlinear equation: ST ( in, CL, CC, Tout ) = 0 where t in( a) t out( a) T T C C a in = out L CC C t = c in( b) t = = out( b) Cb which is a daunting task. So we must look for a different approach. Miller Capacitance Based Solution! Equating the current sources in grounded capacitance and the coupling capacitance, we end up: V 1 0 C, (1 b eff a = Ca + Cc ) where Vb = Vb Vb Vth, a V 1 0 C, (1 a eff b = Cb + Cc ) where Va = Va Va V th, b where V th,a identifies the transition point of interest, say V th,a =0.5V dd and V b is the output voltage transition of driver b from when the output waveform of driver a transits from 0 to its transition point. 12

13 Gate Propagation Delay Algorithm: Coupled Capacitive Load Find_Waveforms_Capacitive_Cross_Coupled(δ(a),δ(b),t in (a), t in (b), C a, C b, C c ) 1. Guess an initial value for output capacitive load as C L (a) and C L (b) 2. t out,a =Draw_Output_Waveform(δ(a),t in (a),c L (a)) 3. t out,b =Draw_Output_Waveform(δ(b),tin(b),C L (b)) 4. Repeat until the output waveform converges For (V th,a,v th,b )={(50%,50%),(50%,90%), (90%,50%), (50%,10%), (10%,50%)} do Find_Output(t out,a,t out,b,v th,a,v th,b,c L (a), C L (b),c c ) Find_Output(t out,a,t out,b,v th,a, V th,b, C L (a), C L (b), C c ) V 1. ( ) ( ) (1 b V CLa CLa + C c ) and CLb ( ) CLb ( ) + C (1 a c ) V tha, V thb, 2. Update t out,a and t out,b 3. If t out,a and t out,b tolerance are within acceptable range, then return t out,a and t out,b 4. Find_Output (t out,a,t out,b,v th,a,v th,b,c L (a),c L (b),c c ) Proof of Convergence! Theorem 2: The Find_Waveforms_Capacitive_Cross_Coupled algorithm converges to its unique solution independently of the initial guess for the value of the effective capacitance to ground.! Proof: the algorithm can be written as : Tout = F( Tin, CL + CEFF ) Tout = F( Tin, CL + G( CC, Tout )) CEFF = G( CC, Tout )! which is equivalent to prove:! where: T out ( FT C GC T ) (, + (, )) < 1 in L C out ( + ( 1 )) ( ( )) 1 k 1 ( ) f 1 Ca Cc kg1 t kg tout a out( a) GC ( C, Tout ) = Cc FT ( in, CL Ceff ) + = 1 kg2 t out( b) kf 2 Cb + Cc 1 kg2 tout( b) 13

14 Proof of Convergence (Cont d)! Therefore, it can be inferred : Fa Fa tout( a) t out( b) ( FT ( in, CL + GC ( C, Tout ))) = T out Fb F b tout( a) tout( b) Fa Fb Fa F = b = k k C k k t t t t out( a) out( b) out( b) out( a) 2 f1 f 2 c g1 g2! The worst case values confirms above inequality, which turns out the correctness of the theorem. Experimental Results 14

15 Outline! Motivation! Background! Effective Capacitance Calculation! RC Loads! Coupled Capacitive Loads! Coupled RC Loads! Conclusions Problem Statement! Problem Statement: The problem statement is the same as the one in for coupled capacitive loads, except that the load is now the one that is depicted in following figure. We are interested in determining the output waveforms at the near ends. t in,a t out,n(a) R π,a t out,f(a) C (a,b) C 1,a C 1,c C 2,a C 2,c C (b,a) t in,b t out,n(b) R π,b t out,f(b) C 1,b C 2,b 15

16 Gate Propagation Delay Algorithm: Coupled RC Loads Find_Output_Waveforms (t in,a,t in,b, Load Parameters) 1. Model each coupling capacitance as a capacitance to ground 2. (t out,n (a),t out,f (a))=draw_for_rcπ_load(t in,a, Load Parameters) 3. (t out,n (b),t out,f (b))=draw_for_rcπ_load(t in,b, Load Parameters) 4. Repeat For (V th,a,v th,b )={(50%,50%),(50%,90%), (90%,50%), (50%,10%), (10%,50%)} do Update_Voltage_Waveforms (Voltage Waveforms, V th,a, V th,b, Load Parameters) 5. Until the output waveforms converges Update_Voltage_Waveforms (Voltage Waveforms, V th,a, V th,b, Load Parameters) 1. Update equivalent Miller capacitance values 2. Draw_for_RCπ_Load (t in,a, Load Parameters) 3. Draw_for_RCπ_Load (t in,b, Load Parameters) 4. If voltage waveforms are within acceptable tolerance, then return values 5. Update_Voltage_Waveforms (Voltage Waveforms, V th,a, V th,b, Load Parameters) Experimental Results 16

17 Conclusion! Gate delays can vary widely as a function of input slews, driver sizes, input transition time skews, and output loads.! We presented three efficient iterative algorithms with provable convergence property for calculating the effective capacitance.! The error for calculating the gate propagation delay is quite small 1-6% depending on the complexity of the load and coupling configuration. 17