Miller Factor for Gate-Level Coupling Delay Calculation

Transcription

1 for Gate-Level Coupling Delay Calculation Pinhong Chen Desmond A. Kirkpatrick Kurt Keutzer Dept. of EECS Intel Corp. Dept. of EECS U. C. Berkeley icroprocessor Products Group U. C. Berkeley Berkeley, CA 947, USA Hillsboro, OR 974, USA Berkeley, CA 947, USA Abstract In coupling delay computation, a iller factor of more than X may be necessary to account for active coupling capacitance when modeling the delay of deep submicron circuitry in the presence of active coupling capacitance. We propose an efficient method to estimate this factor such that the delay response of a decoupling circuit model can emulate the original coupling circuit. Under the assumptions of zero initial voltage, equal charge transfer, and :5V DD as the switching threshold voltage, an upper bound of X for maximum delay and a lower bound of -X for minimum delay can be proven. Efficient Newton-Raphson iteration is also proposed as a technique for computing the iller factor or effective capacitance. This result is highly applicable to crosstalk coupling delay calculation in deep submicron gate-level static timing analysis. Detailed analysis and approximation are presented. SPICE simulations are demonstrated to show high correlation with these approximations. Introduction Using a iller factor is a very convenient method to reduce a highly coupled circuit to a simpler decoupling circuit approximation. If a coupling capacitance is connected between two nodes such as shown in Fig., the effective coupling capacitances are equal to (, k)c and (, =k)c grounded capacitances, respectively, where the two nodes have a voltage gain k. In digital designs, (, k) is conventionally estimated V kv (-k)c V kv Figure : iller Effect Circuit (-/k)c as for the opposite direction switching between two coupling nodes, and for the same direction switching. However, more than X factor has been observed and reported[, ]. In this paper, we present a detailed analysis for how the X iller factor is not an upper bound for coupling delay calculation, and provide a more accurate method to estimate the coupling effect by a decoupling approximation. The factor can be proved at most as large as X under reasonable assumptions. A simple iterative approach and Newton-Raphson iterations are proposed to find these factors or effective capacitances. HSPICE simulations are used to demonstrate the accuracy of these factors. oreover, because the overshoot or the undershoot waveform may also affect circuit delay, a correction method is proposed to approximate the effect of overshoot or undershoot. Our method is crucial for the underlying coupling model for delay calculation in deep submicron circuitry. The iller factor can be used to approximate a coupling capacitance by two grounded capacitances so that the conventional delay calculation mechanism remains unaltered. Due to the mutual dependency between switching windows and timing delays, the static timing analysis approach has to iterate in order to calculate full chip delays in presence of crosstalk[, 4,?]. An efficient and accurate estimation of the coupling effect is crucial for fast convergence. Fixed iller factors(x for the opposite direction switching, and for the same direction switching) are not accurate enough for calculating coupling delay such as shown in this paper. These factors provide neither a bound guarantee nor a good approximation of delay under coupling. In [], the authors show X factor is not an upper bound for crosstalk delay and slew rate, but they do not provide a more accurate factor or prove a new bound to answer this question. A detailed analysis is provided in [], but it does not deal with the case of multiple aggressors. In [5], the authors present an iterative algorithm based on [6] to calculate gate delay by approximating the gate response waveform and RC interconnect response. They address how to find an effective capacitance and nonlinear driver model. This can be very accurate for waveform approximation, which is computed based on a coupled RC network and a nonlinear driver modeling. In contrast with their approach, we address how to decouple the coupling capacitance in a circuit while maintaining delay accuracy. Note that our method is independent of the driver model used. any analytical models with a linear driver resistance have been proposed such as [7, 8, 9, ]. These models are useful to analyze the crosstalk delay and noise pulse for first level screening. However, as shown in Section, the linear model may not be accurate enough due to the driver s

2 significant nonlinearity. [, ] report algorithms to calculate the coupling interconnects. Also, [] provides an industrial example how the crosstalk delay and noise are estimated. Typically, complete waveform accuracy is not required for static timing analysis. What it needs is just the accuracy up to the switching threshold point to approximate delay accurately. Therefore, we use a decoupling approximation such as shown in Fig. to emulate and match the circuit response at the switching threshold point. In addition, the decoupling factor like iller factors is very easy to use and integrate into an existing timing analysis flow. This paper is organized as follows. First, we introduce the gate driving model used in this paper, and show why superposition and the single driver resistance model are not suitable for crosstalk coupling computation. Section will discuss how to derive a iller factor for the delay calculation matched at the switching threshold point. Efficient methods to calculate the effective capacitance and the convergence issue are presented as well. Due to the overshoot/undershoot waveform or noise glitch coupled from aggressors, the initial voltage can be quite different from zero, we propose a correction factor to fix this problem in Section 4. Experimental results from HSPICE simulations are shown in Section 5. Gate Driving and Coupling odel Suppose we have a coupling circuit shown in Fig., where i i Va i Figure : Coupling Circuit we lump all the interconnect resistance of the victim as R v,all the grounded interconnect capacitance of the victim net as C v, and all the coupling capacitance as C xi. Note that we refer to these two nets one for victim and the other for aggressor just for ease of reference. The victim is what we calculate the delay for, and the aggressor is its coupling net which contributes noise. For ease of explanation, we assume a rising waveform on the victim net through out this paper. It is symmetric for the case with a falling waveform.. Nonlinearity of Driver odel any previous works propose a linear driver model[9,, 8], in which the driver is connected with a series resistance and a voltage source, i.e. a Thevenin equivalent circuit such as shown in Fig.[6, 5]. It is useful to obtain an analytical formula for delay or noise peak analysis. However, it may not be accurate. In Fig.4, we show how the driver conductance on a victim net can be nonlinear during the signal transition. It is actually not fixed over time and can vary significantly. The conductance vs. output voltage is also nonlinear, which is shown in Fig.4. Figure : Linear Driver odel mho mho.9pf.6.7pf.6.9pf.5pf...7pf.pf.5pf.8.8.pf.4.pf.4.pf ns.5.5.5Volts Figure 4: Nonlinear conductance varies during signal transition over time for different loadings. Nonlinear conductance vs. output voltage during signal transition for different loadings The nonlinear driver resistance prevents correct superposition of waveforms. In Fig.5, we show how a coupling noise can vary with different arrival times of an aggressor. As the aggressor s arrival time is varied, we calculate the coupled noise on the victim net by subtracting the original victim s waveform from the victim s coupled response. If superposition worked in these cases, the noise peaks should be just the same shape with shifted positions. However, it shows from Fig.5 that the noise peaks can vary according to the arrival time of the aggressor. Therefore, the single resistance assumption for the driver or superposition for waveform estimation may not be accurate for crosstalk delay or noise calculation. - Volts Noise ns Figure 5: Original victim waveform and varying noise due to varying aggressor arrival times We model the driver resistance as a timing-varying and voltage-dependent current source to avoid the inaccuracy of using linear driver model. Actually, our method of estimation of the iller factor is independent of the driver model used.

3 . Driver odeling First, we model the time-varying voltage-dependent current source for a victim driver. For a COS transistor, the drain current is dependent on the drain-to-source voltage V ds and gate-to-source voltage V gs. It is can be written as I ds = f(v ds ;V gs ). Since that the gate-to-source voltage depends on the input waveform, and the drain-to-source voltage is dependent on the output, we model the driving current as I(V; t). Decoupling Approximation It is usually difficult to analyze a coupling circuit like Fig.. It is desirable to replace a coupling circuit with a decoupling circuit using iller factors to multiply the decoupling capacitances. Therefore, the objective of decoupling approximation is as follows. Objective of Decoupling Approximation The victim s transition interval from to is the target transition interval we intend to approximate, and the delay value measured at of transition point(starting from zero voltage) of the decoupling circuit shown in Fig.6 should approximate the response of the original coupling circuit(fig.)., β i in Fig.6 is called a iller factor. In some cases, the initial voltage may not be zero due to +(- βi) i Figure 6: Decoupling Approximation Circuit the early arrival aggressor signal, we will defer that discussion to Section 4.. Coupling odel Combining the driver model above, the circuit equation for Fig. can be written as I(V v ;t)=( C xi +C v ) dv v dv ai, C xi : () Integrating it over the period from the rising time of the victim, t s, to the switching threshold point, t th, for the delay computation. We have Q = Z t th t s It can be simplified as I(V v (t);t) Z Z V ai = ( C xi +C v )dv v, Q = ( C xi +C v ), C xi V ai V a i C xi dv ai : () = ( C xi (, V a i )+C v ) () = ( C xi (, V a i )+C v ) : (4) Eq. (4) implies a factor, V a i =, V a i to approximate the coupling capacitance C xi, assuming equal charge transfer at this period. That is to say, we can find an aggressors voltage difference in the period of the victim s transition from to (e.g. Fig.7) to calculate the iller factor. Vai = Va V DD t τ a = slope= τ a Figure 7: V ai used to calculate the iller factor for the coupling delay. V a vs.... Bounds Assuming equal charge transfer from zero voltage to on the victim net, we have a theorem for bounds of the iller factor for coupling delay calculation. Theorem Under the assumption of zero initial voltage and = :5V DD, the maximum iller factor of the opposite direction switching is for coupling delay calculation measured at the 5% transition. The minimum iller factor is - for the same direction switching at the 5% transition. (Proof:) From Eq. (4), the bounds are easily derived. If the aggressor and the victim switch in the opposite directions, we can have an upper bound, when V ai is equal to,v DD and = :5V DD. If the aggressor and the victim switch in the same direction, we can have as lower bound -, when V ai is equal to V DD and = :5V DD. Note that can be assumed different values to account for different switching threshold points, or the point where the timing is desired to be matched.. Approach V ai is actually unknown before the coupling delay is calculated, so the iller factor, V a i cannot be estimated accurately before the delay is calculated. A simple approach can iterate on V ai until it converges. For ease of notation, we drop the index i for the following discussion wherever there is no confusion. Consider a fixed ramp V a (t) waveform on an aggressor and the victim switches at the opposite direction. V a versus the victim s ramp time,, is shown in Fig.7, where τ a is the ramp time of the aggressor. Some notations are defined as β = V a = V a,

4 the effective capacitance C ef f,whichis C ef f =(, β)c x +C v ; (5) F τv (C ef f ) be the function of effective capacitance, which is the ramp time or slew rate response at the node that the coupling delay measured and matched, and G Va ( ) be the V a function of such as shown in Fig.7. So a composite function H β (C ef f ) can be defined to compute anewβ given C ef f β = H β (C ef f ) = V a = V a = G Va ( ) = G Va (F τv (C ef f )): (6) Simple iterative approach just combines Eq. (5) and Eq. (6), i.e. Cef f =(, H β (C ef f ))C x +C v (7) to iterate until it converges. We note that the convergence rate of this approach is linear... Convergence of Approach To see how this algorithm converges, we can draw the curves for the iller factor versus the effective capacitance C ef f. Four possible curves are shown in Fig.8. The dashed line is the mapping from the iller factor calculated by Eq. (6), and the solid line is the iller factor by Eq. (5). Starting from the the solid line by Eq. (5), and then computing a new iller factor by Eq. (6) along the dashed line. This process repeats until it converges to point. In (d), there may be points the algorithm may converge to, depending on the initial point. The conservative approach is to take the initial value as to converge to the upper point. Physically, this condition corresponds to a very weak victim driver and a very sharp aggressor transition. ost of the cases result in a spike, which is not easy to approximate by this method.. Newton-Raphson Iteration for The convergence rate can be improved by using Newton- Raphson iteration. The key is to compute the derivative of β. By using Eq. (7), Newton-Raphson iteration is set to find the root of f(c ef f )=(, H β (C ef f ))C x +C v,c ef f = : The derivative of H β (C ef f ) is H β(c ef f ) = G V a ( )F (C ef f ) (8) = d V a d ; (9) d dc ef f where F (C ef f ) can be found by a simple table lookup from conventional cell characterization data. The Newton-Raphson iteration can be therefore written as C ef f = C ef f, (, H β(c ef f ))C x +C v,c ef f,c x H β (C ef f), : () Note that if Hβ (β) is equal to, simplifying Eq. (), we have C ef f =(, H β (C ef f ))C x +C v : + + (c) (d) + + Figure 8: iller factor vs. effective capacitance, assuming = = :5V DD iller factor equal to, Fig.8, and (c) can converge to point. The algorithm is equivalent to starting from an initial iller factor, mapping it to an effective capacitance along This is equivalent to the simple iterative approach from Eq. (7). The strength of this approach is the quadratic convergence rate and the convergent initial value is easy to find since the value of β is between - to if = :5V DD, and hence the value of C ef f is between,c x +C v and C x +C v. Note that strictly, G Va does not only depend on but also depends on the relative delay between the aggressor and the victim, which is in turn dependent on C ef f. There is no explicit analytic formula available to accurately describe the relationship. Conventionally, F τv (C ef f ) is described by a two dimensional table pre-characterized for the driving cells. However, the derivative can be relaxed by finite difference approximation. Empirically, the derivative function, H β (C ef f) can be well approximated by the finite difference since the original function H β (C ef f ) is very close to a linear function. The number of iterations vs. the ratio of the coupling capacitance to the grounded capacitance for two approaches are compared and shown in Fig.9, where the convergence criterion is such that the relative error is less than,4. The peak in Fig.9 is a case for which simple iterative approach takes 4

5 45 #iterations Newton-Raphson Figure 9: Comparison of the number of iterations of Simple Iterative Approach and Newton-Raphson iteration iterations to converge. The trace for both approaches for this special case is shown in Fig.. It shows that the simple iterative approach has to iterate more steps around the convergent point, while Newton-Raphson takes fewer steps to converge Newton-Raphson =(- )+ β pf Figure : A case for Approach to take 4 iterations to converge..4 ultiple s for ultiple Coupling Nets For multiple nets coupling together, simple iterative approach becomes C i ef f = k (, H i β k (C ef f ))C i x k +C i v : () However, multiple C ef f values can be found in a single Newton-Raphson run. There is one C ef f for each coupling net. Once C ef f is known, V ai can be computed, and hence the iller factors. Compared with the approach in [5], our formulation needs just one equation per node. The matrix used is simpler and the initial vector is easier to find, i.e. C ef f is between,c x +C v to C x +C v if = :5V DD. We address how to use a decoupling circuit to emulate the original one, while [5] address how to find C ef f and the gate delay. Our model is independent of the driver model used. In reality, the gate driver model and RC interconnect delay are encapsulated in the function F τv (C ef f ),wherec ef f and are the effective capacitance and ramp time, respectively, at the node where the coupling delay should be matched. For completeness of this paper, we derive the Newton- Raphson iteration equations in the following. Suppose we have f i (C ef f )= (, Hβ i k (C ef f )) i k + i,ci ef f = k set to find the roots, where the superscript i denotes the related variable at net i, and net i has net k as a coupling net with coupling capacitance i k. The partial derivative of f i (C ef f ) is f i (C ef f ) where 8 >< = >: H i β k (C ef f ),, k C i x k H i β k (C eff ) C i eff, k C i x k H i β k (C eff ) C j eff = V i a k if i = j =,C i x j H i β j (C eff ) C j eff if i 6= j = G V i (τ i a v ;τk k v) ; which is nonzero only when i = j or j = k. We test this algorithm on a case of two coupling nets with a rising ramp on both nets. The result is shown in Fig., where C v is equal to.5pf. Note that the difference between this and the previous section is that neither one of the nets has a fixed output waveform here. The simple iterative approach fails to converge within steps below the capacitance ratio.75. We also test a case with four coupling nets with a rising ramp #iterations Newton Raphson Figure : Comparison of the number of iterations for Simple Iterative Approach and Newton-Raphson Iterations with coupling nets. on each net. The result is shown in Fig...5 Slew Rate(Ramp Time) Calculation Slew rate(ramp time) is another factor that affects the delay calculation. However, if the iller factors are used to approximate the slew rate, we have to match up to the upper point of transition(typically 9% or 8% of transition) or down to the lower point of transition(typically % or % of transition). It may need more than one iller factor to calculate. The difference is just to make = :9V DD in Eq. (4) for the upper point of transition at 9% of V DD,or = :V DD for the lower point of transition at % of V DD.

6 #iterations Newton-Raphson Figure : Comparison of the number of iterations for Simple Iterative Approach and Newton-Raphson Iterations with 4 coupling nets. 4 Nonzero Initial Voltage Correction Some waveforms may not start from zero voltage. This leads another source of errors for decoupling approximation. We show how to correct this problem in this section. 4. Glitch Waveform Approximation We first consider a case when an aggressor is making transition before a victim is such that an undershoot waveform occurs on the victim net such as shown in Fig.. The vic- R Figure : Undershoot Waveform Undershoot Circuit tim s initial voltage being zero is not exactly accurate due to the glitch coupled from the aggressor. Consider a falling aggressor with a ramp waveform. A simplified model is used as shown in Fig.. We have V v d +C R + x R v (V dv v v,v a )+C v = : by averaging ap- Assume V a =(, t=τ a )V DD and dv v proximation. It can be rewritten as V v = = V v t V v +C R + x ( V v + V DD V v )+C v = R v t τ a t Va, C x τ a V DD t t=(r + R v )+C x +C v ; t τ a : () If multiple aggressors are present, and the initial voltage of V v is nonzero V v, we can extend it as V v = δii,t τ ai V DD +( C xi +C v ) () t=(r + R v )+ C xi +C v where δ i is if the aggressor is falling, or - if the aggressor is rising, and zero, otherwise. This equation also applies when multiple aggressors join in different time points. It also applies when all aggressors become quiet. This modeling is verified with HSPICE simulations. One example is shown in Fig.4. The victim s driver resistance is 856ohm, the aggressor has a perfect falling slope of.5ns, is.pf, is.pf, and V DD is.v. It shows that at the corners of the curve this model has some small errors. Volts SPICE Simulation Under Shoot Waveform Approximation ns Figure 4: Experiment for Undershoot odeling 5 Experimental Results We verify the estimated iller factors or decoupling approximation by HSPICE simulation on a simple circuit consisting of a fixed ramp input on an aggressor net, and a pure capacitive loading on the victim net along with some coupling capacitance. In Fig.5, we vary the aggressor s arrival time to see the effect of delay variation on the victim net. The estimated iller factor is calculated using decoupling approximation described in Section and the undershoot correction is also computed. Using this factor HSPICE simulation is performed on the decoupling circuit again to measured the delay. The same procedure is repeated for X iller factor. Our method(marked as decoupling approximation) closely follows the original coupling circuit, while the X iller factor can be far off. Also, it shows that X is not an upper bound. In Delay(ns) X iller Decoupling Coupling Decoupling Approximation Arrival Time(ns) Figure 5: delay vs. aggressor s arrival time

7 Fig.6, we vary the aggressor s ramp time to see the effect of delay variation on the victim net. Our method (marked as decoupling approximation) closely follows the original coupling circuit, while the X iller factor can be far off. Typical Delay X iller Decoupling Coupling Decoupling Approximation Ramp Time(ns) Figure 6: s delay vs. aggressor s ramp time waveform response is shown in Fig.7. volts X Coupling Output Decoupling Approximation ns Figure 7: Example of waveform response 6 Conclusion We propose a simple and accurate method to estimate the iller factor for approximating a coupling circuit by a decoupling circuit. It is well-suited for coupling delay calculation in very deep submicron designs. An efficient Newton-Raphson method is proposed to find the iller factors or effective capacitance. Besides, we prove an upper bound of X for opposite direction switching, and a lower bound of -X for same direction switching. The conventional X factor is shown as clearly not a bound and can be very inaccurate for coupling delay calculation. References [] G. Yee, R. Chandra, V. Ganesan, and C. Sechen. Wire Delay in the Presence of Crosstalk. In IEEE/AC International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pages 7 75, 997. [] A. B. Kahng, S. uddu, and E. Sarto. On Switch Factor Based Analysis of Coupled RC Interconnects. In Design Automation Conference, pages 79 84,. [] B. Franzini, C. Forzan, D. Pandini, P. Scandolara, and A. D. Fabbro. Crosstalk Aware Static Timing Analysis:a Two Step Approach. In IEEE of st International Symposium on Quality Electronic Design, pages 499 5, ar.. [4] P. F. Tehrani, S. W. Chyou, and U. Ekambaram. Deep Sub-icron Static Timing Analysis in Presence of Crosstalk. In IEEE of st International Symposium on Quality Electronic Design, pages 55 5, ar.. [5] F. Dartu and L. T. Pileggi. Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. In Proc. of 4th AC/IEEE Design Automation Conference, Jun [6] F. Dartu, N. enezes, and L. T. Pileggi. Performance computation for precharacterized COS gates with RCloads. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 5:544 55, ay 996. [7] A. B. Kahng, S. uddu, and D. Vidhani. Noise and Delay Estimation for Coupled RC Interconnects. In IEEE AISC/SoC, ar [8]. Becer and I. N. Hajj. An Analytical odel for Delay and Crosstalk Estimation with Application to Decoupling. In IEEE of st International Symposium on Quality Electronic Design, pages 5 57, ar.. [9] W. Chen, S. K. Gupta, and. A. Breuer. Analytic odels for Crosstalk Delay and Pulse Analysis Under Non- Ideal Inputs. In International Test Conference, pages 89 88, Nov [] T. Xiao and. arek-sadowska. Efficient Delay Calculation in Presence of Crosstalk. In IEEE of st International Symposium on Quality Electronic Design, pages , ar.. [] K. L. Shepard, V. Narayanan, P.C. Elmendor, and Gutuan Zheng. Global Harmony: Coupled Noise Analysis for Full-Chip RC Interconnect Network. In Proc. of International Conference on Computer Aided Design, pages 9 46, 997. [] A. Devgan. Efficient Coupled Noise Estimation for On- Chip Interconnects. In Proc. of International Conference on Computer Aided Design, pages 47 5, 997. [] K. Aringaran, F. Klass, C.. Kim, C. Amir, J. itra, E. You, J. ohd, and S. K. Dong. Coupling Noise Analysis for VLSI and ULSI Circuits. In IEEE of st International Symposium on Quality Electronic Design, pages , ar..