X9258. Low Noise/Low Power/2-Wire Bus/256 Taps. Features. Quad Digital Controlled Potentiometers (XDCP ) Block Diagram

Transcription

1 Low Noise/Low ower/2-wire Bus/256 aps Data heet FN Quad Digital ontrolled otentiometers (XD ) he X9258 integrates 4 digitally controlled potentiometers (XD ) on a monolithic M integrated circuit. he digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. he position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper ounter egister (W) and 4 non-volatile Data egisters (D0:D3) that can be directly written to and read by the user. he contents of the W controls the position of the wiper on the resistor array though the switches. ower-up recalls the contents of D0 to the W. he XD can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features Four potentiometers in one package 256 resistor taps/potentiometer % resolution 2-wire serial interface Wiper resistance, 40Ω V+ = 5V, V- = -5V Four nonvolatile data registers for each potentiometer Nonvolatile storage of wiper position tandby current <5µ max (total package) ower supplies - V = 2.7V to 5.5V - V+ = 2.7V to 5.5V - V- = -2.7V to -5.5V 100kΩ, 50kΩ total potentiometer resistance High reliability - Endurance: 100,000 data changes per bit per register - egister data retention years 24 Ld I, 24 Ld Dual supply version of X9259 b-free (oh compliant) Block Diagram V 0 V V+ V- W WIE UNE EGIE (W) V H0 / H0 V L0 / L WIE UNE EGIE (W) EI Y 2 V H2 / H2 V L2 / L2 L D INEFE ND NL IUIY 8 V W0 / W0 V W2 / W2 3 D V W1 / W1 V W3 / W WIE UNE EGIE (W) EI Y 1 V H1 / H1 V L1 / L WIE UNE EGIE (W) EI Y 3 V H3 / H3 V L3 / L3 1 UIN: hese devices are sensitive to electrostatic discharge; follow proper I Handling rocedures INEIL or opyright Intersil mericas Inc. 2005, 2006, ll ights eserved Intersil (and design) and XD are trademarks owned by Intersil orporation or one of its subsidiaries. ll other trademarks mentioned are the property of their respective owners.

2 rdering Information NUMBE (Note 2) MING V LIMI (V) ENIMEE GNIZIN (kω) EMEUE NGE ( ) GE (b-free) G. DWG. # X9258U24Z (Note 1) X9258U Z 5 ± to Ld I (300 mil) M24.3 X9258U24IZ (Note 1) X9258U ZI -40 to Ld I (300 mil) M24.3 X9258UV24IZ X9258UV ZI -40 to Ld (4.4mm) MD0044 X925824Z X9258 Z to Ld I (300 mil) M24.3 X925824IZ (Note 1) X9258 ZI -40 to Ld I (300 mil) M24.3 X9258U24Z-2.7 (Note 1) X9258U ZF 2.7 to to Ld I (300 mil) M24.3 X9258U24IZ-2.7 (Note 1) X9258U ZG -40 to Ld I (300 mil) M24.3 X9258UV24IZ-2.7 X9258UV ZG -40 to Ld (4.4mm) MD0044 X925824Z-2.7 (Note 1) X9258 ZF to Ld I (300 mil) M24.3 X925824IZ-2.7 (Note 1) X9258 ZG -40 to Ld I (300 mil) M24.3 X9258V24IZ-2.7 X9258V ZG -40 to Ld (4.4mm) MD0044 X9258V24Z-2.7 X9258V ZF 0 to Ld (4.4mm) MD0044 NE: 1. dd * suffix for tape and reel. lease refer to B347 for details on reel specifications. 2. hese Intersil b-free plastic packaged products employ special b-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal (e3 termination finish, which is oh compliant and compatible with both nb and b-free soldering operations). Intersil b-free products are ML classified at b-free peak reflow temperatures that meet or exceed the b-free requirements of I/JEDE J D For Moisture ensitivity Level (ML), please see device information page for X9258. For more information on ML please see tech brief B FN8168.6

3 inout X9258 (24 LD I, ) VIEW N L V W3 / W V L2 / L2 V H3 / H V H2 / H2 V L3 / L V W2 / W2 V+ V 6 7 X V V V L0 / L V W1 / W1 V H0 / H V H1 / H1 V W0 / W V L1 / L W D in Descriptions Host Interface ins in Names YMBL DEIIN EIL L (L) he L input is used to clock data into and out of the X9258. EIL D (D) D is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ed with any number of open drain or open collector outputs. n open drain output requires the use of a pull-up resistor. For selecting typical values, refer to Guidelines for alculating ypical Values of Bus ull-up esistors on page 10. DEVIE DDE ( 0-3 ) he ddress inputs are used to set the least significant 4 bits of the 8-bit slave address. match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9258. maximum of 16 devices may occupy the 2-wire serial bus. otentiometer ins V H / H (V H0 / H0 - V H3 / H3 ), V L / L (V L0 / L0 - V L3 / L3 ) he V H / H and V L / L inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. V W / W (V W0 / W0 - V W3 / W3 ) he wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write rotect Input (W) he W pin when low prevents nonvolatile writes to the Data egisters. nalog upplies V+, V- he nalog upplies V+, V- are the supply voltages for the D analog section. L D 0 thru 3 V H0 / H0 thru V H3 / H3, V L0 / L0 thru V L3 / L3 V W0 / W0 thru V W3 / W3 W V+, V- V V N erial lock erial Data rinciples f peration Device ddress otentiometer ins (terminal equivalent) otentiometers ins (wiper equivalent) Hardware Write rotection nalog upplies ystem upply Voltage ystem Ground No onnection (llowed) he X9258 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the D potentiometers. erial Interface (2-Wire) he X9258 supports a bidirectional bus oriented protocol. he protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. he device controlling the transfer is a master and the device being controlled is the slave. he master will always initiate data transfers and provide the clock for both transmit and receive operations. herefore, the X9258 will be considered a slave device in all applications. 3 FN8168.6

4 lock and Data onventions Data states on the D line can change only during L LW periods (t LW ). D state changes during L HIGH are reserved for indicating start and stop conditions. tart ondition ll commands to the X9258 are preceded by the start condition, which is a HIGH to LW transition of D while L is HIGH (t HIGH ). he X9258 continuously monitors the D and L lines for the start condition and will not respond to any command until this condition is met. top ondition ll communications must be terminated by a stop condition, which is a LW to HIGH transition of D while L is HIGH. cknowledge cknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. he transmitting device, either the master or the slave, will release the D bus after transmitting 8 bits. he master generates a ninth clock cycle and during this period the receiver pulls the D line LW to acknowledge that it successfully received the 8 bits of data. he X9258 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte, the X9258 will respond with a final acknowledge. rray Description he X9258 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. he physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (V H / H and V L / L inputs). Device ddressing Following a start condition the master must output the address of the slave it is accessing. he most significant 4 bits of the slave address are the device type identifier (refer to Figure 1). For the X9258 this is fixed as 0101[B]. DEVIE YE IDENIFIE DEVIE DDE FIGUE 1. LVE DDE he next 4 bits of the slave address are the device address. he physical device address is defined by the state of the 0 thru 3 inputs. he X9258 compares the serial data stream with the address input state; a successful compare of all 4 address bits is required for the X9258 to respond with an acknowledge. he 0 thru 3 inputs can be actively driven by M input signals or tied to V or V. cknowledge olling he disabling of the inputs (during the internal nonvolatile write operation), can be used to take advantage of the typical 5ms nonvolatile write cycle time. nce the stop condition is issued to indicate the end of the nonvolatile write command, the X9258 initiates the internal write cycle. polling can be initiated immediately. his involves issuing the start condition followed by the device slave address. If the X9258 is still busy with the write operation, no will be returned. If the X9258 has completed the write operation an will be returned and the master can then proceed with the next operation. t both ends of each array and between each resistor segment is a M switch connected to the wiper (V W ) output. Within each individual array only one switch may be turned on at a time. hese switches are controlled by the Wiper ounter egister (W). he 8 bits of the W are decoded to select, and enable, one of 256 switches. he W may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the W. hese data registers and the W can be read and written by the host system. 4 FN8168.6

5 olling equence. EGIE ELE NNVLILE WIE MMND MLEED ENE LLING I3 I2 I1 I IUE INUIN WIE UNE EGIE ELE FIGUE 2. INUIN BYE FM IUE LVE DDE EUNED? YE FUHE EIN? YE IUE INUIN EED N N IUE IUE EED he four high order bits define the instruction. he next 2 bits (1 and 0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. he last bits (1, 0) select which one of the four potentiometers is to be affected by the instruction. Four of the nine instructions end with the transmission of the instruction byte. he basic sequence is illustrated in Figure 3. hese two-byte instructions exchange data between the Wiper ounter egister and one of the data registers. transfer from a Data egister to a Wiper ounter egister is essentially a write to a static M. he response of the wiper to this action will be delayed t WL. transfer from the Wiper ounter egister (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t W to complete. he transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, wherein the transfer occurs between all of the potentiometers and one of their associated registers. Instruction tructure he next byte sent to the X9258 contains the instruction and register pointer information. he four most significant bits are the instruction. he next four bits point to one of the two potentiometers and when applicable they point to one of four associated registers. he format is shown in Figure 2. Four instructions require a three-byte sequence to complete. hese instructions transfer data between the host and the X9258; either between the host and one of the data registers or directly between the host and the Wiper ounter egister. hese instructions are: ead Wiper ounter egister (read the current wiper position of the selected potentiometer), Write Wiper ounter egister (change current wiper position of the selected potentiometer), ead Data egister (read the contents of the selected nonvolatile register) and Write Data egister (write a new value to the selected data register). he sequence of operations is shown in Figure 4. L D I3 I2 I1 I FIGUE 3. W-BYE INUIN EQUENE 5 FN8168.6

6 he Increment/Decrement command is different from the other commands. nce the command is issued and the X9258 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each L clock pulse (t HIGH ) while D is HIGH, the selected wiper will move one resistor segment towards the V H terminal. imilarly, for each L clock pulse while D is LW, the selected wiper will move one resistor segment towards the V L / L terminal. detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. INUIN BLE 1. INUIN E INUIN E I 3 I 2 I 1 I EIN ead Wiper ounter egister /0 1/0 ead the contents of the Wiper ounter egister pointed to by 1-0 Write Wiper ounter egister /0 1/0 Write new value to the Wiper ounter egister pointed to by 1-0 ead Data egister /0 1/0 1/0 1/0 ead the contents of the Data egister pointed to by 1-0 and 1-0 Write Data egister /0 1/0 1/0 1/0 Write new value to the Data egister pointed to by 1-0 and 1-0 XF Data egister to Wiper ounter egister XF Wiper ounter egister to Data egister Global XF Data egisters to Wiper ounter egisters Global XF Wiper ounter egisters to Data egister Increment/Decrement Wiper ounter egister /0 1/0 1/0 1/0 ransfer the contents of the Data egister pointed to by 1-0 and 1-0 to its associated Wiper ounter egister /0 1/0 1/0 1/0 ransfer the contents of the Wiper ounter egister pointed to by 1-0 to the Data egister pointed to by /0 1/0 0 0 ransfer the contents of the Data egisters pointed to by 1-0 of all four potentiometers to their respective Wiper ounter egisters /0 1/0 0 0 ransfer the contents of both Wiper ounter egisters to their respective data egisters pointed to by 1-0 of all four potentiometers /0 1/0 Enable Increment/decrement of the ontrol Latch pointed to by 1-0 NE: 4. 1/0 = data is one or zero. 6 FN8168.6

7 L D I3 I2 I1 I D7 D6 D5 D4 D3 D2 D1 D0 FIGUE 4. HEE-BYE INUIN EQUENE I L D I3 I2 I1 I FIGUE 5. INEMEN/DEEMEN INUIN EQUENE I N 1 I N 2 I N n D E 1 D E n F I IN/DE MD IUED t WID L D V W / W VLGE U FIGUE 6. INEMEN/DEEMEN IMING LIMI L FM ME D UU FM NMIE D UU FM EEIVE FIGUE 7. NWLEDGE ENE FM EEIVE NWLEDGE 7 FN8168.6

8 EIL D H FM INEFE IUIY EIL BU INU V H / H EGIE 0 EGIE EGIE 2 EGIE 3 LLEL BU INU WIE UNE EGIE (W) UNE DEDE If W = 00[H] then V W / W = V L / L If W = FF[H] then V W / W = V H / H U/DN MDIFIED L IN/DE LGI U/DN L V L / L FIGUE 8. DEILED ENIMEE BL DIGM DEILED EIN V W / W ll D potentiometers share the serial interface and share a common architecture. Each potentiometer has a Wiper ounter egister and four Data egisters. detailed discussion of the register organization and array operation follows. Wiper ounter egister he X9258 contains four Wiper ounter egisters, one for each D potentiometer. he Wiper ounter egister can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. he contents of the W can be altered in four ways: 1. Written directly by the host via the Write Wiper ounter egister instruction (serial load) 2. Written indirectly by transferring the contents of one of four associated Data egisters via the XF Data egister instruction (parallel load) 3. an be modified one step at a time by the Increment/Decrement instruction. 4. Loaded with the contents of its data register zero (0) upon power-up. he W is a volatile register; that is, its contents are lost when the X9258 is powered-down. lthough the register is automatically loaded with the value in 0 upon power-up, it should be noted this may be different from the value present at power-down. Data egisters Each potentiometer has four nonvolatile Data egisters. hese can be read or written directly by the host and data can be transferred between any of the four Data egisters and the W. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. egister Descriptions Data egisters, (8-bit), Nonvolatile W7 W6 W5 W4 W3 W2 W1 W0 NV NV NV NV NV NV NV NV (MB) Four 8-bit Data egisters for each D (sixteen 8-bit registers in total). (LB) {D7~D0}: hese bits are for general purpose not volatile data storage or for storage of up to four different wiper values. he contents of Data egister 0 are automatically moved to the wiper counter register on power-up. 8 FN8168.6

9 Wiper ounter egister, (8-bit), Volatile W7 W6 W5 W4 W3 W2 W1 W0 V V V V V V V V (MB) (LB) ne 8-bit Wiper ounter egister for each D (four 8-bit registers in total.) {D7~D0}: hese bits specify the wiper position of the respective D. he Wiper ounter egister is loaded on power-up by the value in Data egister 0. he contents of the W can be loaded from any of the other Data egister or directly. he contents of the W can be saved in a D. Instruction Format NE: 5. M / : stands for the acknowledge sent by the master/slave ~ 0 : stands for the device addresses sent by the master. 7. X : indicates that it is a 0 for testing purpose but physically it is a don t care condition. 8. I : stands for the increment operation, D held high during active L phase (high). 9. D : stands for the decrement operation, D held low during active L phase (high). ead Wiper ounter egister (W) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE W DDEE WIE IIN (EN BY LVE N D) W7 W6 W5 W4 W3 W2 W1 W0 M Write Wiper ounter egister (W) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE W DDEE D BYE (EN BY ME N D) W7 W6 W5 W4 W3 W2 W1 W0 ead Data egister (D) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D ND W DDEE D BYE (EN BY LVE N D) W7 W6 W5 W4 W3 W2 W1 W0 M Write Data egister (W) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D ND W DDEE D BYE (EN BY ME N D) W7 W6 W5 W4 W3 W2 W1 W0 HIGH-VLGE WIE YLE 9 FN8168.6

10 XF Data egister (D) to Wiper ounter egister (W) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D ND W DDEE XF Wiper ounter egister (W) to Data egister (D) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D ND W DDEE HIGH-VLGE WIE YLE Increment/Decrement Wiper ounter egister (W) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE W DDEE INEMEN/DEEMEN (EN BY ME N D) I/D I/D.... I/D I/D Global XF Data egister (D) to Wiper ounter egister (W) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D DDEE Global XF Wiper ounter egister (W) to Data egister (D) DEVIE YE IDENIFIE DEVIE DDEE INUIN DE D DDEE HIGH-VLGE WIE YLE ymbol able WVEFM INU UU Must be steady May change from Low to High May change from High to Low Don t are: hanges llowed N/ Will be steady Will change from Low to High Will change from High to Low hanging: tate Not nown enter Line is High Impedance Guidelines for alculating ypical Values of Bus ull-up esistors EINE (k) V MX MIN = =1.8kΩ IL MIN MX = MINIMUM EINE t BU MXIMUM EINE BU INE (pf) 10 FN8168.6

11 bsolute Maximum atings Voltage on D, L or any ddress Input with espect to V V to +7V Voltage on V+ (referenced to V ) V Voltage on V- (referenced to V ) V (V+) - (V-) V ny V H / H V+ ny V L / L V- I W (10s) ±15m hermal Information hermal esistance (ypical) θ J ( /W) θ J ( /W) 24 Lead I (Notes 10, 11) Lead (Notes 10, 11) emperature Under Bias to +135 torage emperature to +150 b-free eflow rofile see link below perating onditions emperature ange to +85 upply Voltage ange (ypical) X V ±10% X V to 5.5V UIN: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NE: 10. θ J is measured with the component mounted on a high effective thermal conductivity test board in free air. ee ech Brief B379 for details. 11. For θ J, the case temp location is taken at the package top center. nalog pecifications ver recommended operating conditions, unless otherwise specified. YMBL MEE E NDIIN MIN Y MX UNI End-to-end esistance olerance ±20 % ower ating +25, each potentiometer 50 mw I W Wiper urrent Wiper current = ±1m ±7.5 m W Wiper esistance I W = ± V+ = 3V, V- = -3V Ω W Wiper esistance I W = ± V+ = 5V, V- = -5V Ω V+ Voltage on V+ in X V X V V- Voltage on V- in X V X V V EM Voltage on any V H / H or V L / L in V- V+ V Noise ef: 1kHz -120 dbv esolution (Note 16) 0.6 % bsolute Linearity (Note 13) V w(n)(actual) - V w(n)(expected) ±1 MI (Note 15) elative Linearity (Note 14) V w(n + 1) - [V w(n) + MI ] ±0.6 MI (Note 15) emperature oefficient of L ±300 ppm/ atiometric emperature oefficient ±20 ppm/ H / L / W otentiometer apacitance ee est ircuit #3 IE Macro Model on page 13 10/10/25 pf 11 FN8168.6

12 D perating haracteristics ver recommended operating conditions, unless otherwise specified. YMBL MEE E NDIIN MIN Y MX UNI I 1 I 2 V upply urrent (Nonvolatile Write) V upply urrent (Move Wiper, Write, ead) f L = 400kHz, D = pen, 1 m ther Inputs = V f L = 400kHz, D = pen, 100 µ ther Inputs = V I B V urrent (tandby) L = D = V, ddr. = V 5 µ I LI Input Leakage urrent V IN = V to V 10 µ I L utput Leakage urrent V U = V to V 10 µ V IH Input HIGH Voltage V x 0.7 V V V IL Input LW Voltage -0.5 V x 0.3 V V L utput LW Voltage I L = 3m 0.4 V NE: 12. arameters with MIN and/or MX limits are 100% tested at +25, unless otherwise specified. emperature limits established by characterization and are not production tested. 13. bsolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 14. elative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 15. MI = /255 or (V H / H V L / L )/255, single potentiometer. 16. Max = all four arrays cascaded together; typical = individual array resolutions. Endurance and Data etention MEE MIN UNI Minimum Endurance 100,000 Data changes per bit per register Data etention 100 years apacitance YMBL MEE E NDIIN MX UNI I/ (Note 17) Input/utput apacitance (D) V I/ = 0V 8 pf IN (Note 17) Input apacitance (0, 1, 2, 3, and L) V IN = 0V 6 pf ower-up iming YMBL MEE MIN MX UNI t U (Note 18) ower-up to Initiation of ead peration 1 ms t UW (Note 18) ower-up to Initiation of Write peration 5 ms t V (Note 19) V ower-up amp V/ms NE: 17. his parameter is periodically sampled and not 100% tested. 18. t U and t UW are the delays required from the time the third (last) power supply (V, V+ or V-) is stable until the specific instruction can be issued. hese parameters are periodically sampled and not 100% tested. 19. ample tested only. 12 FN8168.6

13 ower-up and ower-down equirement he are no restrictions on the sequencing of the bias supplies V, V+, and V- provided that all three supplies reach their final values within 1ms of each other. t all times, the voltages on the potentiometer pins must be less than V+ and more than V-. he recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their final value. he V ramp rate specification is always in effect. est onditions Input ulse Levels V x 0.1 to V x 0.9 Input ise and Fall imes 10ns Input and utput iming Level V x 0.5 Equivalent Load ircuit 5V 1533Ω D UU 100pF est ircuit #3 IE Macro Model M MDEL 2.7V 100pF L H H W L 10pF L 10pF 25pF W iming ver recommended operating conditions, unless otherwise specified. YMBL MEE MIN MX UNI f L lock Frequency 400 khz t Y lock ycle ime 2500 ns t HIGH lock High ime 600 ns t LW lock Low ime 1300 ns t U: tart etup ime 600 ns t HD: tart Hold ime 600 ns t U: top etup ime 600 ns t U:D D Data Input etup ime 100 ns t HD:D D Data Input Hold ime 30 ns t L and D ise ime (Note 20) 300 ns t F L and D Fall ime (Note 20) 300 ns t L Low to D Data utput Valid ime 900 ns t DH D Data utput Hold ime 50 ns I Noise uppression ime onstant at L and D Inputs 50 ns t BUF Bus Free ime (rior to any ransmission) 1300 ns t U:W W, 0, 1, 2 and 3 etup ime 0 ns t HD:W W, 0, 1, 2 and 3 Hold ime 0 ns NE: 20. device must internally provide a hold time of at least 300ns for the D signal in order to bridge the undefined region of the falling edge of L. 13 FN8168.6

14 High-Voltage Write ycle iming YMBL MEE Y MX UNI t W High-Voltage Write ycle ime (tore Instructions) 5 10 ms D iming YMBL MEE MIN MX UNI t W Wiper esponse ime fter the hird (Last) ower upply is table 10 µs t WL Wiper esponse ime fter Instruction Issued (ll Load Instructions) 10 µs t WID Wiper esponse ime from an ctive L/ Edge (Increment/Decrement Instruction) 10 µs iming Diagrams 2-Wire Interface tart and top iming () () t t F L t U: t HD: t U: t t F D Input iming t Y t HIGH L t LW D t U:D t HD:D t BUF utput iming L D t t DH 14 FN8168.6

15 D iming (for ll Load Instructions) () L D LB t WL VWx D iming (for Increment/Decrement Instruction) L D WIE EGIE DDE INEMEN/DEEMEN INEMEN/DEEMEN t WID VWx Write rotect and Device ddress ins iming () () L D... (NY INUIN) t U:W t HD:W W 0, 1 2, 3 15 FN8168.6

16 pplications information Basic onfigurations of Electronic otentiometers X9258 V +V V W / W I FIGUE 9. HEE EMINL ENIMEE; VIBLE VLGE DIVIDE FIGUE 10. W-EMINL VIBLE EI; VIBLE UEN pplication ircuits V + V V IN 317 V (EG) 1 2 I DJ 1 2 V = (1+ 2 / 1 ) V FIGUE 11. NN-INVEING MLIFIE V (EG) = 1.25V (1+ 2 / 1 )+ I DJ 2 FIGUE 12. VLGE EGUL V kΩ + V V + V L072 10kΩ } } 10kΩ 10kΩ +12V -12V FIGUE 13. FFE VLGE DJUMEN 1 2 V UL = { 1 /( )} V (MX) V LL = { 1 /( )} V (MIN) FIGUE 14. M WIH HYEEI 16 FN8168.6

17 pplication ircuits (ontinued) V + V V V 3 4 ll = 10kΩ 1 2 V = G V -1/2 G +1/2 FIGUE 15. ENU G = / 1 fc = 1/(2π) FIGUE 16. FILE V + V } } + V Z IN 1 3 V = G V G = - 2 / 1 FIGUE 17. INVEING MLIFIE Z IN = 2 + s 2 ( ) 1 = 2 + s Leq ( ) >> 2 FIGUE 18. EQUIVLEN L- IUI + } } B FEQUENY 1, 2, MLIUDE, B FIGUE 19. FUNIN GENE 17 FN8168.6

18 hin hrink mall utline ackage Family () E 0.25 M B E1 B EING LNE 0.10 N LED e N 1 D VIEW b IDE VIEW EE DEIL X (N/2)+1 (N/2) IN #1 I.D B 2X N/2 LED I M B H MD0044 HIN HIN MLL ULINE GE FMILY MILLIMEE YMBL 14 LD 16 LD 20 LD 24 LD 28 LD LENE Max ± ±0.05 b /-0.06 c /-0.06 D ±0.10 E Basic E ±0.10 e Basic L ±0.15 L eference ev. F 2/07 NE: 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension E1 does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. 3. Dimensions D and E1 are measured at dtum lane H. 4. Dimensioning and tolerancing per ME Y14.5M c END VIEW L1 2 1 DEIL X L 0-8 GUGE LNE 0.25 ll Intersil U.. products are manufactured, assembled and tested utilizing I9000 quality systems. Intersil orporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil orporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. ccordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see 18 FN8168.6

19 ackage utline Drawing M LED WIDE BDY MLL ULINE LI GE (I) ev 2, 3/11 24 INDEX E 7.60 (0.299) 7.40 (0.291) (0.419) (0.394) DEIL "" VIEW EING LNE 1.27 (0.050) 0.40 (0.016) (0.614) (0.598) 2.65 (0.104) 2.35 (0.093) 0.75 (0.029) 0.25 (0.010) x (0.050) IDE VIEW 0.30 (0.012) 0.10 (0.004) 0.51 (0.020) 0.33 (0.013) 0.32 (0.012) 0.23 (0.009) 8 0 IDE VIEW B (0.078) (0.369) NE: 1. Dimensioning and tolerancing per NI Y14.5M ackage length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. ackage width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. he chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. erminal numbers are shown for reference only. 6. he lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. ontrolling dimension: MILLIMEE. onverted inch dimensions in ( ) are not necessarily exact. 8. his outline conforms to JEDE publication M-013-D IUE (0.050) (0.021) YIL EMMENDED LND EN 19 FN8168.6