DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, DIGITAL, DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR, MONOLITHIC SILICON REVISIONS
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1 REVISIONS LTR DESCRIPTION DTE PPROVED Update boilerplate to current MIL-PRF requirements. - PHN Thomas M. Hess CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE PMIC N/ PREPRED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen PPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITL, DUL RETRIGGERBLE MONOSTBLE MULTIVIBRTOR, MONOLITHIC SILICON CODE IDENT. NO. REV PGE 1 OF 11 MSC N/ 5962-V079-14
2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual retriggerable mono stable multi vibrator microcircuit, with an operating temperature range of -55 C to +125 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacturer s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s) X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device type Generic Circuit function 01 SN74HC123-EP Dual retriggerable mono stable multi vibrator Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MS-012 Plastic small outline Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other REV PGE 2
3 1.3 bsolute maximum ratings. 1/ Supply voltage range ( V CC ) V to +7.0 V 2/ Input voltage range ( V I ) V to +7.0 V 3/ Output voltage range in high or low state ( V O ) V to V CC V 2/ Output voltage range in power off state ( V O ) V to +7.0 V 2/ Input clamp current ( I IK ) ( V I < 0 ) m Output clamp current ( I OK ) ( V O < 0 V or V O < V CC )... ±20 m Continuous output current ( I O ) (V O = 0 V to V CC)... ±25 m Continuous current through V CC or GND... ±50 m Package thermal impedance ( θ J ) C/W 4/ Storage temperature range (T STG ) C to 150 C 1.4 Recommended operating conditions. 5/ Supply voltage (V CC ) V to +5.5 V Minimum high level input voltage ( V IH): V CC = 2.0 V V V CC = 3.0 V V V CC = 5.5 V V Maximum low level input voltage (V IL): V CC = 2.0 V V V CC = 3.0 V V V CC = 5.5 V V Input voltage (V I)... 0 V to 5.5 V Output voltage (V O)... 0 to V CC Maximum high level output current ( I OH ): V CC = 2.0 V μ V CC = 3.3 V ±0.3 V m V CC = 5 V ±0.5 V m Maximum low level output current ( I OL ): V CC = 2.0 V μ V CC = 3.3 V ±0.3 V... 4 m V CC = 5 V ±0.5 V... 8 m Minimum external timing resistance: V CC = 2.0 V... 5 kω V CC > 3.0 V... 1 kω V Minimum power up ramp rate (Δt/ΔV CC)... 1 ms/v Operating free-air temperature range ( T ) C to +125 C 1/ Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Voltage values are with respect to the network ground terminal. 3/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4/ The package thermal impedance is calculated in accordance with JESD / Unused Rext/Cext terminals should be left unconnected. ll remaining unused inputs of the device must be held at VCC or GND to ensure proper device operation. REV PGE 3
4 2. PPLICBLE DOCUMENTS JEDEC SOLID STTE TECHNOLOGY SSOCITION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at or from JEDEC Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outline. The case outline shall be as shown in and figure Terminal connections. The terminal connections shall be as shown in figure Function table. The Function table shall be as shown in figure Logic diagram. The logic diagram shall be as shown in figure Input/Output timing diagram. The input/output timing diagram shall be as shown in figure Load circuit and timing waveforms. The load circuit and timing waveforms shall be as shown in figure 6. REV PGE 4
5 Test Symbol Conditions TBLE I. Electrical performance characteristics. 1/ unless otherwise specified V CC Limits Unit T = 25 C -55 C T 125 C Min Max Min Max 2 V V I OH = -50 µ 3 V High level output voltage V OH 4.5 V I OH = -4 m 3 V I OH = -8 m 4.5 V V V I OL = 50 µ 3 V Low level output voltage V OL 4.5 V I OL = 4 m 3 V I OL = 8 m 4.5 V Input R ext/c ext 2/ I I V I = V CC or GND 5.5 V ±0.25 ±2.5 μ current, B, and CLR V I = V CC or GND 0 V to 5.5 V ±0.1 ±1 3/ Quiescent supply current I CC V I = V CC or GND, I O = V 4 40 μ V I = V CC or GND, 3 V μ ctive state (per circuit) I CC R ext/c ext = 0.5 V CC 4.5 V V Input capacitance C i V I = V CC or GND 5 V pf Pulse duration Pulse retrigger time CLR 3.3 V ±0.3 V 5 5 ns t w 5 V ±0.5 V 5 5 or B trigger 3.3 V ±0.3 V V ±0.5 V 5 5 R ext = 1 kω, C ext = 100 pf 3.3 V ±0.3 V 4/ 76 Typ 4/ ns t rr R ext = 1 kω, C ext = 0.01 μf 4/ 1.8 Typ 4/ R ext = 1 kω, C ext = 100 pf 5 V ±0.5 V 4/ 59 Typ 4/ μs R ext = 1 kω, C ext = 0.01 μf 4/ 1.5 Typ 4/ Switching characteristics From input or B See footnotes at end of table. t PLH C L = 15 pf 3.3 V ±0.3 V / 5 V ±0.5 V 12 5/ t PHL 3.3 V ±0.3 V / 5 V ±0.5 V 12 5/ 24 5/ ns 14 5/ 24 5/ 14 5/ REV PGE 5
6 Pulse duration at Q or Q TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions t w unless otherwise specified C L = 50 pf, C ext = 28 μf, R ext = 2 kω C L = 50 pf, C ext = 0.01 μf, R ext = 10 kω C L = 50 pf, C ext = 0.1 μf, R ext = 10 kω V CC Limits Unit T = 25 C -55 C T 125 C Min Max Min Max Switching characteristics - continued From input CLR t PLH C L = 15 pf 3.3 V ±0.3 V / / ns 5 V ±0.5 V 9.4 5/ 11 5/ t PHL 3.3 V ±0.3 V / / 5 V ±0.5 V 9.4 5/ 11 5/ From input CLR trigger t PLH 3.3 V ±0.3 V / 26 5/ 5 V ±0.5 V / 15 5/ t PHL 3.3 V ±0.3 V / 26 5/ 5 V ±0.5 V / 15 5/ From input or B t PLH C L = 50 pf 3.3 V ±0.3 V V ±0.5 V t PHL 3.3 V ±0.3 V V ±0.5 V From input CLR t PLH 3.3 V ±0.3 V V ±0.5 V t PHL 3.3 V ±0.3 V V ±0.5 V From input CLR trigger t PLH 3.3 V ±0.3 V V ±0.5 V t PHL 3.3 V ±0.3 V V ±0.5 V V ±0.3 V ns 5 V ±0.5 V Output pulse duration variation (Q or Q ) between circuits in same package Operating Characteristics Power dissipation capacitance 3.3 V ±0.3 V μs 5 V ±0.5 V V ±0.3 V ms 5 V ±0.5 V V ±0.3 V ±1% Typ 5 V ±0.5 V ±1% Typ 5 V 29 Typ pf 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This test is performed with the terminal in the off state condition. 3/ On products compliant to MIL-PRF-38535, this parameter in not production tested at V CC = 0 V. 4/ See retriggering in the manufacturer data. 5/ On products compliant to MIL-PRF-38535, this parameter in not production tested. REV PGE 6
7 Case X Dimension Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max E E b e.050 BSC 1.27 BSC c L D NOTES: 1. ll linear dimensions are in inches (millimeters). 2. This drawing is subject to change without notice. 3. Body length does not include mold flash, protrusions, or gat burrs. Mold flash, protrusions, or gat burs shall not exceed.006 inches (0.15 mm) per end. 4. Body width does not include interlead flash. Interlead flash shall not exceed.017 inches (0.43 mm) per side. 5. Falls within JEDEC MS-012 variation C FIGURE 1. Case outline. REV PGE 7
8 Case X Terminal number Terminal symbol Terminal number Terminal symbol B 10 2B 3 1 CLR 11 2 CLR 4 1 Q 12 2 Q 5 2Q 13 1Q 6 2C ext 14 1C ext 7 2R ext/c ext 15 1R ext/c ext 8 GND 16 V CC FIGURE 2. Terminal connections. Note: These outputs are based on the assumption that the indicated steady-state condition at the and B inputs have been set up long enough to complete any pulse started before the setup. FIGURE 3. Function table. REV PGE 8
9 FIGURE 4. Logic diagram. FIGURE 5. Input/output timing diagram REV PGE 9
10 NOTES: 1. C L includes probe and jig capacitance. 2. ll input pulses are supplied by generators having the following characteristics: Z O = 50 Ω, t r = 3 ns, t f = 3 ns.. 3. The outputs are measured one at a time with one input transition per measurement. FIGURE 5. Load circuit and timing waveforms. REV PGE 10
11 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL Land and Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ Device manufacturer CGE code Vendor part number Top side marking -01XE SN74HC123MDREP HC123-EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box Dallas, TX Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX REV PGE 11
DLA LAND AND MARITIME COLUMBUS, OHIO TITLE MICROCIRCUIT, LINEAR, CMOS SPDT SWITCH, MONOLITHIC SILICON REVISIONS
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