74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.
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1 Rev November 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state bus compatible outputs. The 3-state outputs are controlled by the output enable inputs OE0 and OE1. HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Balanced propagation delays ll inputs have a Schmitt-trigger action Inputs accepts voltages higher than V CC For 74HC541 only: operates with CMOS input levels For 74HCT541 only: operates with TTL input levels ESD protection: HBM JESD22-114E exceeds 2000 V MM JESD exceeds 200 V CDM JESD22-C101C exceeds 1000 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC541D 40 C to +125 C SO20 plastic small outline package; 20 leads; SOT HCT541D 74HC541PW 40 C to +125 C TSSOP20 body width 7.5 mm plastic thin shrink small outline package; 20 leads; SOT HCT541PW 74HC541BQ 40 C to +125 C DHVQFN20 body width 4.4 mm plastic dual-in-line compatible thermal enhanced SOT HCT541BQ very thin quad flat package; no leads; 20 terminals; body mm
2 4. Functional diagram 2 0 Y Y Y Y Y & EN 7 5 Y Y Y OE0 OE1 mna mna180 Fig 1. Logic symbol Fig 2. IEC logic symbol Product data sheet Rev November of 16
3 5. Pinning information 5.1 Pinning 74HC541 74HCT541 terminal 1 index area OE0 VCC 74HC541 74HCT OE1 OE V CC OE1 Y Y0 Y1 Y Y Y GND Y2 Y3 Y4 Y5 Y6 Y GND (1) GND 11 Y7 Y4 Y5 Y6 001aah aah038 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 3. Pin configuration SO20, TSSOP20 Fig 4. Pin configuration DHVQFN Pin description Table 2. Pin description Symbol Pin Description OE0 1 output enable input (active LOW) [0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) Y[0:7] 18, 17, 16, 15, 14, 13, 12, 11 data output OE1 19 output enable input (active LOW) V CC 20 supply voltage Product data sheet Rev November of 16
4 6. Functional description Table 3. Functional table [1] Control Input Output OE0 OE1 n Yn L L L L L L H H X H X Z H X X Z [1] H = HIGH voltage level; L = LOW voltage level; X = don t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V V I input voltage V I IK input clamping current V I < 0.5 V [1] 20 - m I OK output clamping current V O < 0.5 V or V O >V CC V [1] - ±20 m I O output current V O = 0.5 V to (V CC V) - ±25 m I CC supply current - 75 m I GND ground current 75 - m T stg storage temperature C P tot total power dissipation T amb = 40 C to +125 C SO20 package [2] mw TSSOP20 package [3] mw DHVQFN20 package [4] mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] P tot derates linearly with 8 mw/k above 70 C. [3] P tot derates linearly with 5.5 mw/k above 60 C. [4] P tot derates linearly with 4.5 mw/k above 60 C. Product data sheet Rev November of 16
5 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC541 74HCT541 Unit 9. Static characteristics Min Typ Max Min Typ Max V CC supply voltage V V I input voltage V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature C t/ V input transition rise and fall rate V CC = 3.3 V ± 0.3 V ns/v V CC = 5.0 V ± 0.5 V ns/v Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit For type 74HC541 V IH HIGH-level input voltage V IL V OH V OL I OZ I I LOW-level input voltage HIGH-level output voltage LOW-level output voltage OFF-state output current input leakage current Min Typ Max Min Max Min Max V CC = 2.0 V V V CC = 3.0 V V V CC = 5.5 V V V CC = 2.0 V V V CC = 3.0 V V V CC = 5.5 V V V I = V IH or V IL I O = 50 µ; V CC = 2.0 V V I O = 50 µ; V CC = 3.0 V V I O = 50 µ; V CC = 4.5 V V I O = 4.0 m; V CC = 3.0 V V I O = 8.0 m; V CC = 4.5 V V V I = V IH or V IL I O = 50 µ; V CC = 2.0 V V I O = 50 µ; V CC = 3.0 V V I O = 50 µ; V CC = 4.5 V V I O = 4.0 m; V CC = 3.0 V V I O = 8.0 m; V CC = 4.5 V V V I =V IH or V IL ; - - ± ±2.5 - ±10.0 µ V O =V CC or GND; V CC = 5.5 V V I =V CC or GND; V CC = 0 V to 5.5 V I CC supply current V I =V CC or GND; I O = 0 ; V CC = 5.5 V µ µ Product data sheet Rev November of 16
6 Table 6. Static characteristics continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max C I input pf capacitance C O output capacitance pf For type 74HCT541 V IH HIGH-level V CC = 4.5 V to 5.5 V V input voltage V IL LOW-level V CC = 4.5 V to 5.5 V V input voltage V OH HIGH-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 50 µ V I O = 8.0 m V V OL LOW-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 50 µ V I O = 8.0 m V I OZ OFF-state output current per input pin; V I =V IH or V IL ; V CC = 5.5 V; I O = 0 ; V O =V CC or GND; other pins at V CC or GND - - ± ±2.5 - ±10.0 µ I I input leakage current V I =V CC or GND; V CC = 0 V to 5.5 V I CC supply current V I =V CC or GND; I O = 0 ; V CC = 5.5 V I CC C I C O additional supply current input capacitance output capacitance per input pin; V I =V CC 2.1 V; I O = 0 ; other pins at V CC or GND; V CC = 4.5 V to 5.5 V µ µ m pf pf Product data sheet Rev November of 16
7 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V. For test circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max Min Max For type 74HC541 t pd propagation n to Yn; see Figure 5 [2] delay V CC = 3.0 V to 3.6 V C L = 15 pf ns C L = 50 pf ns V CC = 4.5 V to 5.5 V C L = 15 pf ns C L = 50 pf ns t en enable time OEn to Yn; see Figure 6 [2] V CC = 3.0 V to 3.6 V C L = 15 pf ns C L = 50 pf ns V CC = 4.5 V to 5.5 V C L = 15 pf ns C L = 50 pf ns t dis disable time OEn to Yn; see Figure 6 [2] C PD power dissipation capacitance V CC = 3.0 V to 3.6 V C L = 15 pf ns C L = 50 pf ns V CC = 4.5 V to 5.5 V C L = 15 pf ns C L = 50 pf ns C L = 50 pf; f i = 1 MHz; [3] pf V I = GND to V CC Product data sheet Rev November of 16
8 Table 7. Dynamic characteristics continued GND = 0 V. For test circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max Min Max For type 74HCT541 t pd propagation n to Yn; see Figure 5 [2] delay V CC = 4.5 V to 5.5 V C L = 15 pf ns C L = 50 pf ns t en enable time OEn to Yn; see Figure 6 V CC = 4.5 V to 5.5 V C L = 15 pf ns C L = 50 pf ns t dis disable time OEn to Yn; see Figure 6 [2] C PD power dissipation capacitance [1] Typical values are measured at nominal supply voltage (V CC = 3.3 V and V CC = 5.0 V). [2] t pd is the same as t PLH and t PHL. t en is the same as t PZL and t PZH. t dis is the same as t PLZ and t PHZ. [3] C PD is used to determine the dynamic power dissipation P D (µw). P D =C PD V CC 2 f i + (C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in Volts. V CC = 4.5 V to 5.5 V C L = 15 pf ns C L = 50 pf ns per buffer; [3] pf C L =50pF;f=1 MHz; V I = GND to V CC Product data sheet Rev November of 16
9 11. Waveforms V I n input GND t PHL t PLH V OH Yn output V OL mna901 Fig 5. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Propagation delay input (n) to output (Yn) V I OEn input GND t PLZ t PZL output LOW-to-OFF OFF-to-LOW V CC V OL V X t PHZ t PZH V OH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled V Y outputs disabled outputs enabled mna902 Fig 6. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Enable and disable times Table 8. Measurement points Type Input Output V X V Y 74HC V CC 0.5V CC V OL V V OH 0.3 V 74HCT V 0.5V CC V OL V V OH 0.3 V Product data sheet Rev November of 16
10 V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC PULSE GENERTOR VI DUT VO RL S1 open RT CL 001aad983 Fig 7. Test data is given in Table 9. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator C L = Load capacitance including jig and probe capacitance R L = Load resistor S1 = Test selection switch Load circuitry for switching times Table 9. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC541 V CC 3.0 ns 15 pf, 50 pf 1 kω open GND V CC 74HCT V 3.0 ns 15 pf, 50 pf 1 kω open GND V CC Product data sheet Rev November of 16
11 12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E X c y H E v M Z Q 2 1 ( ) 3 pin 1 index L p L θ 1 e b p 10 w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E04 MS Fig 8. Package outline SOT163-1 (SO20) Product data sheet Rev November of 16
12 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E X c y H E v M Z Q pin 1 index 2 1 ( ) 3 θ 1 10 w M e b p detail X L p L mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT360-1 MO-153 EUROPEN PROJECTION ISSUE DTE Fig 9. Package outline SOT360-1 (TSSOP20) Product data sheet Rev November of 16
13 DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm SOT764-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 9 v M w M C C B y 1 C C y L 1 10 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) E h e e 1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 10. Package outline SOT764-1 (DHVQFN20) Product data sheet Rev November of 16
14 13. bbreviations Table 10. cronym CDM CMOS DUT ESD HBM MM TTL bbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes Product data sheet 74HC_HCT541_2 Modifications: 74HC_HCT541_2 ( ) 74HC_HCT541_1 ( ) The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN20 package added. Section 8: derating values added for DHVQFN20 package. Section 12: outline drawing added for DHVQFN20 package Product specification 74HC_HCT541_ Product specification - Product data sheet Rev November of 16
15 15. Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail Disclaimers General Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia accepts no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Nexperia. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: For sales office addresses, send an to: salesaddresses@nexperia.com Product data sheet Rev November of 16
16 17. Contents 1 General description Features Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Date of release: 12 November 2007
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Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
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More information74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting
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Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance
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Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 7 pril 203 Product data sheet. General description The consists of four non-inverting buffers/line drivers with 3-state outputs (ny) that are controlled by the output enable input (noe). HIGH at noe
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Rev. 1 18 November 2013 Product data sheet 1. General description The provides the single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
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Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible
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Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
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