Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.
|
|
- Lenard Sutton
- 5 years ago
- Views:
Transcription
1 Rev November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance with JEDEC standard no. 7. The is a quad bus transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The is designed for 4-line asynchronous 2-way data communications between data buses. The output enable inputs (OE and OEB) can be used to isolate the buses. The is similar to the 74HC242 but has non-inverting (true) outputs. Non-inverting 3-state outputs 2-way asynchronous data bus communication Low-power dissipation Complies with JEDEC standard no. 7 ESD protection: HBM EI/JESD B exceeds 2000 V MM EI/JESD exceeds 200 V. Multiple package options Specified from 40 C to+80 C and from 40 C to +125 C.
2 3. Quick reference data 4. Ordering information Table 1: Quick reference data GND = 0 V; T amb =25 C; t r =t f = 6 ns. Symbol Parameter Conditions Min Typ Max Unit t PHL, t PLH propagation delay n to Bn; C L = 15 pf; V CC = 5 V ns Bn to n C I input capacitance pf C I/O input/output capacitance pf C PD power dissipation capacitance per transceiver V I = GND to V CC [1] pf [1] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Table 2: Type number Ordering information Package Temperature range Name Description Version N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 D 40 C to +125 C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 Product data sheet Rev November of 17
3 5. Functional diagram 13 1 OEB OE ENBLE EXITING 3 0 B B B B aab953 Fig 1. Functional diagram OEB 13 OE 1 ENBLE EXITING 13 1 EN1 EN2 0 3 B B aab aab951 Fig 2. Logic symbol Fig 3. IEC logic symbol Product data sheet Rev November of 17
4 6. Pinning information 6.1 Pinning OE 1 14 V CC n.c OEB n.c B B B2 GND aab948 B3 Fig 4. Pin configuration 6.2 Pin description Table 3: Pin description Symbol Pin Description OE 1 output enable input (active LOW) n.c. 2 not connected 0 3 data input or output 1 4 data input or output 2 5 data input or output 3 6 data input or output GND 7 ground (0 V) B3 8 data output or input B2 9 data output or input B1 10 data output or input B0 11 data output or input n.c. 12 not connected OEB 13 output enable input V CC 14 positive supply voltage Product data sheet Rev November of 17
5 7. Functional description 8. Limiting values 7.1 Function table Table 4: Function table [1] Control [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. Input or output OE OEB n Bn L L input B = H L Z Z L H Z Z H H = B input Table 5: Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input diode current V I < 0.5 V or V I >V CC V - ±20 m I OK output diode current V O < 0.5 V or - ±20 m V O >V CC V I O output source or sink V O = 0.5 V to V CC V - ±35 m current I CC, I GND V CC or GND current - ±70 m T stg storage temperature C P tot power dissipation DIP14 package [1] mw SO14 and SSOP16 packages [2] mw [1] bove 70 C: P tot derates linearly with 12 mw/k. [2] bove 70 C: P tot derates linearly with 8 mw/k. Product data sheet Rev November of 17
6 9. Recommended operating conditions Table 6: 10. Static characteristics Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V t r, t f input rise and fall V CC = 2.0 V ns times V CC = 4.5 V ns V CC = 6.0 V ns T amb ambient temperature C Table 7: Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb =25 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±0.1 µ I OZ 3-state OFF-state current V I =V IH or V IL ; V CC = 6.0 V; - - ±0.5 µ V O =V CC or GND I CC quiescent supply current V I =V CC or GND; I O =0; µ V CC = 6.0 V C I input capacitance pf C I/O input/output capacitance pf Product data sheet Rev November of 17
7 Table 7: Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±1.0 µ I OZ 3-state OFF-state current V I =V IH or V IL ; V CC = 6.0 V; - - ±5.0 µ V O =V CC or GND I CC quiescent supply current V I =V CC or GND; I O =0; V CC = 6.0 V µ T amb = 40 C to +125 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL - I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V Product data sheet Rev November of 17
8 Table 7: Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V OL LOW-level output voltage V I =V IH or V IL - I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V I LI input leakage current V I =V CC or GND; V CC = 6.0 V - - ±1.0 µ I OZ 3-state OFF-state current V I =V IH or V IL ; V CC = 6.0 V; - - ±10.0 µ V O =V CC or GND I CC quiescent supply current V I =V CC or GND; I O =0; V CC = 6.0 V µ 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; t r =t f = 6 ns; C L = 50 pf; R L = 1000 Ω; see Figure 8. Symbol Parameter Conditions Min Typ Max Unit T amb = 25 C t PHL, t PLH propagation delay n to Bn; Bn to n see Figure 5 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 5.0 V; C L =15pF ns t PZH, t PZL 3-state output enable time OE to n or Bn; OEB to n or Bn see Figure 6 and 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PHZ, t PLZ 3-state output disable time OE to n or Bn; OEB to n or Bn see Figure 6 and 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 5 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns C PD power dissipation capacitance per transceiver V I = GND to V CC [1] pf T amb = 40 C to +85 C t PHL, t PLH propagation delay n to Bn; Bn to n see Figure 5 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev November of 17
9 Table 8: Dynamic characteristics continued GND = 0 V; t r =t f = 6 ns; C L = 50 pf; R L = 1000 Ω; see Figure 8. Symbol Parameter Conditions Min Typ Max Unit t PZH, t PZL 3-state output enable time OE to n or Bn; OEB to n or Bn [1] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. see Figure 6 and 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PHZ, t PLZ 3-state output disable time OE to n or Bn; see Figure 6 and 7 OEB to n or Bn V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 5 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns T amb = 40 C to +125 C t PHL, t PLH propagation delay n to Bn; Bn to n see Figure 5 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PZH, t PZL 3-state output enable time OE to n or Bn; see Figure 6 and 7 OEB to n or Bn V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PHZ, t PLZ 3-state output disable time OE to n or Bn; see Figure 6 and 7 OEB to n or Bn V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 5 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev November of 17
10 12. Waveforms n, Bn input V M t PHL t PLH Bn, n output V M t THL t TLH 001aab955 V M = 0.5 V I. Fig 5. Waveforms showing the input (n and Bn) to output (Bn and n) propagation delays and the output transition times t r t f OE input 10 % 90 % V M t PLZ t PZL output LOW to OFF OFF to LOW 10 % V M output HIGH to OFF OFF to HIGH t PHZ 90 % t PZH V M outputs enabled outputs disabled outputs enabled 001aab959 V M = 0.5 V I. Fig 6. Waveforms showing the 3-state enable and disable times for input OE Product data sheet Rev November of 17
11 t r t f OEB input 90 % V M 10 % t PLZ t PZL output LOW to OFF OFF to LOW 10 % V M output HIGH to OFF OFF to HIGH t PHZ 90 % t PZH V M outputs enabled outputs disabled outputs enabled 001aab956 Fig 7. V M = 0.5 V I. Waveforms showing the 3-state enable and disable times for input OEB PULSE GENERTOR V I V CC D.U.T. V O S 1 RL = 1000 Ω V CC open GND RT C L mna232 Fig 8. Test data is given in Table 9. Definitions for test circuit: R L = Load resistor. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Z o of the pulse generator. Load circuitry for switching times Table 9: Test data Supply Input Load S 1 V CC V I t r = t f C L R L t PZL, t PLZ t PZH, t PHZ t PHL, t PLH 2.0 V V CC 6 ns 50 pf 1 kω V CC GND open 4.5 V V CC 6 ns 50 pf 1 kω V CC GND open 6.0 V V CC 6 ns 50 pf 1 kω V CC GND open 5.0 V V CC 6 ns 15 pf 1 kω V CC GND open Product data sheet Rev November of 17
12 13. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D M E seating plane 2 L 1 Z 14 e b b 1 8 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT G04 MO-001 SC Fig 9. Package outline SOT27-1 (DIP14) Product data sheet Rev November of 17
13 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E X c y H E v M Z 14 8 Q pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E06 MS Fig 10. Package outline SOT108-1 (SO14) Product data sheet Rev November of 17
14 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E X c y H E v M Z 14 8 Q 2 1 ( ) 3 pin 1 index 1 7 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p Q v w y Z(1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT337-1 MO Fig 11. Package outline SOT337-1 (SSOP14) Product data sheet Rev November of 17
15 14. Revision history Table 10: Revision history Document ID Release Data sheet status Change notice Doc. number Supersedes date _ Product data sheet HC_HCT243_CNV_2 Modifications: The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. Removed type number 74HCT243. Inserted family specification. 74HC_HCT243_CNV_ Product specification HC_HCT243_1 74HC_HCT243_ Product specification Product data sheet Rev November of 17
16 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions 17. Disclaimers Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ Product data sheet Rev November of 17
17 19. Contents 1 General description Features Quick reference data Ordering information Functional diagram Pinning information Pinning Pin description Functional description Function table Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline Revision history Data sheet status Definitions Disclaimers Contact information Koninklijke Philips Electronics N.V ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 November 2004 Document number: Published in The Netherlands
18 Mouser Electronics uthorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: D,112 DB,112 DB,118 D,118 N,652
The 74HC21 provide the 4-input AND function.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
More information74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting
3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible
More information74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.
Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).
More information74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance
More information74HC1G125; 74HCT1G125
Rev. 05 23 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed, Si-gate CMOS device. The provides one non-inverting buffer/line driver with 3-state
More information74HC244; 74HCT244. Octal buffer/line driver; 3-state
Rev. 03 22 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
More information8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground).
Rev. 04 12 January 2005 Product data sheet 1. General description 2. Features The is an with three address inputs (0 to 2), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and
More informationHex inverting Schmitt trigger with 5 V tolerant input
Rev. 04 15 February 2005 Product data sheet 1. General description 2. Features 3. pplications The is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible
More information8-bit binary counter with output register; 3-state
Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It
More informationINTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23
INTEGRTED CIRCUITS DT SHEET Supersedes data of 993 Sep 0 2003 Jul 23 FETURES Complies with JEDEC standard no. 8- ESD protection: HBM EI/JESD22-4- exceeds 2000 V MM EI/JESD22-5- exceeds 200 V. Specified
More information74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger
Rev. 03 24 January 2006 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
More information74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.
16-bit dual supply translating transciever; 3-state Rev. 02 1 June 2004 Product data sheet 1. General description 2. Features The is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior
More information8-bit serial-in/parallel-out shift register
Rev. 03 4 February 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164.
More informationINTEGRATED CIRCUITS DATA SHEET. 74HC00; 74HCT00 Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 26.
INTEGRTED CIRCUITS DT SHEET Quad 2-input NND gate Supersedes data of 1997 ug 26 2003 Jun 30 Quad 2-input NND gate FETURES Complies with JEDEC standard no. 8-1 ESD protection: HBM EI/JESD22-114- exceeds
More information74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop.
Rev. 03 14 September 2005 Product data sheet 1. General description 2. Features 3. pplications 4. uick reference data he are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series.
More information74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state
Rev. 03 20 January 2006 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. INTEGRTED CIRCUITS DT SHEET Supersedes data of 1990 Dec 01 2003 Jul 25 FETURES
More information74HC393; 74HCT393. Dual 4-bit binary ripple counter
Rev. 03 6 September 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
More information14-stage binary ripple counter
Rev. 01 29 November 2005 Product data sheet 1. General description 2. Features 3. pplications he is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HC4020.
More information2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.
74HC1G09 Rev. 02 18 December 2007 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC1G09 is a high-speed Si-gate CMOS device. The 74HC1G09 provides the 2-input ND function
More information74HC164; 74HCT bit serial-in, parallel-out shift register
Rev. 03 4 pril 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They
More informationThe 74LV08 provides a quad 2-input AND function.
Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0
More informationINTEGRATED CIRCUITS. PCK2002P 533 MHz PCI-X clock buffer. Product data Supersedes data of 2001 May Dec 13. Philips Semiconductors
INTEGRATED CIRCUITS Supersedes data of 2001 May 09 2002 Dec 13 Philips Semiconductors FEATURES General purpose and PCI-X 1:4 clock buffer 8-pin TSSOP package See PCK2001 for 48-pin 1:18 buffer part See
More information74AHC1G00; 74AHCT1G00
74HC1G00; 74HCT1G00 Rev. 06 30 May 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G00 and 74HCT1G00 are high-speed Si-gate CMOS devices. They provide a 2-input
More informationThe 74LV32 provides a quad 2-input OR function.
Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.
More information74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.
Rev. 02 5 November 2007 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
More informationDATA SHEET. 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET 16-bit D-type transparent latch with 5 V Supersedes data of 2002 Oct 02 2003 Dec 08 FEATURES 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage
More information74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter
Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output
More information74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.
Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.
More informationOctal bus transceiver; 3-state
Rev. 02 7 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive
More information74HC154; 74HCT to-16 line decoder/demultiplexer
Rev. 06 2 February 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The
More information74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
More informationTemperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.
Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance
More information74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.
Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
More information74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.
Rev. 03 12 November 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state
More information2-input EXCLUSIVE-OR gate
Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output
More information74AHC125; 74AHCT125. Quad buffer/line driver; 3-state
Rev. 04 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They
More information74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.
Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
More informationDATA SHEET. 74LVC16374A; 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS
INTEGRATED CIRCUITS DATA SHEET 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state Supersedes data of 1998 Mar 17 2003 Dec 12 FEATURES 5 V tolerant inputs/outputs for interfacing
More information74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.
Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible
More information74HC238; 74HCT to-8 line decoder/demultiplexer
Rev. 03 16 July 2007 Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238
More informationThe 74LVC1G02 provides the single 2-input NOR function.
Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. INTEGRTED CIRCUITS DT SHEET Supersedes data of 1997 ug 26 2003 Oct 30 FETURES
More information74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.
Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state
More informationXC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger
Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This
More information74AHC2G126; 74AHCT2G126
Rev. 04 27 pril 2009 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC2G126 and 74HCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line
More information74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.
Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
More informationThe 74LVC1G11 provides a single 3-input AND gate.
Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input
More information3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state
with 30 Ω termination resistors; 3-state Rev. 03 17 January 2005 Product data sheet 1. General description 2. Features The is a high performance BiCMOS product designed for V CC operation at 3.3 V. The
More information74AHC14; 74AHCT14. Hex inverting Schmitt trigger
Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
More informationINTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1998 Apr 13 IC24 Data Handbook 1998 Apr 20 FEATURES Wide operating voltage: 1.0 to 5.5 V Optimized for low voltage applications: 1.0 to 3.6 V Accepts TTL input levels
More information74HC257; 74HCT257. Quad 2-input multiplexer; 3-state
Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has four identical 2-input multiplexers with
More informationINTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook
INTEGRATED CIRCUITS Octal D-type flip-flop with reset; positive-edge trigger 1997 Apr 07 IC24 Data Handbook FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V
More information74LV General description. 2. Features. 3. Applications. 8-bit serial-in/serial-out or parallel-out shift register; 3-state
Rev. 03 21 pril 2009 Product data sheet 1. General description 2. Features 3. pplications The is an 8 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage
More information74LV393 Dual 4-bit binary ripple counter
INTEGRATED CIRCUITS Supersedes data of 1997 Mar 04 IC24 Data Handbook 1997 Jun 10 FEATURES Optimized for Low Voltage applications: 1.0 to.6v Accepts TTL input levels between V CC = 2.7V and V CC =.6V Typical
More information74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting
Rev. 3 21 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit inverting buffer/line driver with 3-state outputs. The device features
More information74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state
Rev. 06 6 March 2006 Product data sheet. General description 2. Features 3. Quick reference data The is a high-performance BiCMOS product designed for V CC operation at 3.3 V. This device combines low
More informationINTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook
INTEGRATED CIRCUITS 1998 Jun 23 IC24 Data Handbook FEATURES Optimized for Low Voltage applications: 1.0 to 5.5V Accepts TTL input levels between V CC = 2.7V and V CC = 3.6V Typical V OLP (output ground
More information74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:
Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate
More information74LVU General description. 2. Features. 3. Applications. Hex inverter
Rev. 06 20 December 2007 Product data sheet. General description 2. Features 3. pplications The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HCU04. The is a general purpose
More information8-bit binary counter with output register; 3-state
Rev. 02 28 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is
More informationINTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Jun 23 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for low voltage applications: 1.0V to 3.6V Accepts TTL input levels
More informationINTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28
INTEGRATED CIRCUITS -to-8 line decoder/demultiplexer; inverting 998 Apr 8 FEATURES Wide supply voltage range of. to. V In accordance with JEDEC standard no. 8-A Inputs accept voltages up to. V CMOS lower
More informationDual 2-to-4 line decoder/demultiplexer
74LV9 Rev. 04 December 007 Product data sheet. General description. Features. Ordering information The 74LV9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC9 and 74HCT9.
More information74LV General description. 2. Features. 8-bit addressable latch
Rev. 03 2 January 2008 Product data sheet. General description 2. Features The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The is a high-speed designed
More information74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset
Rev. 04 16 June 2006 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
More information2N7002T. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.
Rev. 1 17 November 25 Product data sheet 1. Product profile 1.1 General description N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features
More information74LV374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS
INTEGRATE CIRCUITS Octal -type flip-flop; positive edge-trigger (3-State) Supersedes data of 1996 Feb IC24 ata Handbook 1997 Mar 20 FEATURES Wide operating voltage: 1.0 to 5.5 Optimized for Low oltage
More information74HC594; 74HCT bit shift register with output register
Rev. 03 20 December 2006 Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The is
More informationHEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder
Rev. 06 25 November 2009 Product data sheet 1. General description 2. Features 3. Applications The is a 4-bit, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer.
More informationPMWD16UN. 1. Product profile. 2. Pinning information. Dual N-channel µtrenchmos ultra low level FET. 1.1 General description. 1.
Rev. 2 24 March 25 Product data sheet 1. Product profile 1.1 General description Dual N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2 Features
More informationDual JK flip-flop with reset; negative-edge trigger
Rev. 04 19 March 2008 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate MOS device that complies with JEDE standard no. 7. It is pin compatible with
More information74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state
Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device
More informationDATA SHEET. BSS192 P-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 20
DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D19 Supersedes data of 1997 Jun 2 22 May 22 FEATURES Direct interface to C-MOS, TTL, etc. High-speed switching No secondary breakdown. APPLICATIONS Line
More information74HC4017; 74HCT4017. Johnson decade counter with 10 decoded outputs
Rev. 03 8 January 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4017. The is a 5-stage Johnson decade counter with
More information74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate
8-input NND gate Rev. 6 27 December 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-input NND gate. Inputs include clamp diodes. This enables
More information74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting. Product data sheet
3-to-8 line decoder, demultiplexer with address latches; inverting Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky
More information74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:
Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate
More information74AHC1G14; 74AHCT1G14
Rev. 6 18 May 29 Product data sheet 1. General description 2. Features 3. pplications 74HC1G14 and 74HCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt
More information74HC238; 74HCT to-8 line decoder/demultiplexer
Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders
More informationDual 3-channel analog multiplexer/demultiplexer with supplementary switches
with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer
More information74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.
Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
More information74HC08; 74HCT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate
Quad 2-input ND gate Rev. 4 6 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input ND gate. Inputs include clamp diodes. This
More information74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate
Rev. 4 17 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use
More information74HC126; 74HCT126. Quad buffer/line driver; 3-state
Rev. 3 22 September 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad buffer/line driver with 3-state outputs controlled by the output enable
More information2N7002F. 1. Product profile. 2. Pinning information. N-channel TrenchMOS FET. 1.1 General description. 1.2 Features. 1.
Rev. 3 28 April 26 Product data sheet. Product profile. General description N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology..2 Features Logic level
More information74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.
Quad 2-input NND gate Rev. 5 25 November 200 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard
More information74HC138; 74HCT to-8 line decoder/demultiplexer; inverting
Rev. 4 27 June 2012 Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The decoder accepts three binary weighted
More informationDATA SHEET. PH2369 NPN switching transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr Oct 11.
DISCRETE SEMICONDUCTORS DATA SHEET book, halfpage M3D186 Supersedes data of 1999 Apr 27 2004 Oct 11 FEATURES Low current (max. 200 ma) Low voltage (max. 15 V). APPLICATIONS High-speed switching. PINNING
More information74HC04; 74HCT General description. 2. Features and benefits. 3. Ordering information. Hex inverter
Rev. 4 3 ugust 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The is a hex inverter. The inputs include clamp diodes that enable the use of current limiting
More informationPMV65XP. 1. Product profile. 2. Pinning information. P-channel TrenchMOS extremely low level FET. 1.1 General description. 1.
Rev. 1 28 September 24 Product data sheet 1. Product profile 1.1 General description P-channel enhancement mode field effect transistor in a plastic package using TrenchMOS technology. 1.2 Features Low
More informationOctal D-type transparent latch; 3-state
Rev. 02 18 October 2007 Product data sheet 1. General description 2. Features The is an octal -type transparent latch featuring separate -type inputs for each latch and 3-state true outputs for bus-oriented
More information74HC139; 74HCT139. Dual 2-to-4 line decoder/demultiplexer
Rev. 3 28 March 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes two binary weighted address inputs (n0, n1) to four mutually exclusive outputs
More information74HC03-Q100; 74HCT03-Q100
Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable
More information74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate
Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors
More information74LVC374 Octal D-type flip-flop; positive edge-trigger (3-State) INTEGRATED CIRCUITS
INTEGRATE CIRCUITS Octal -type flip-flop; positive edge-trigger (3-State) Supersedes data of February 1996 IC24 ata Handbook 1997 Mar 12 FEATURES Wide supply voltage range of 1.2V to 3.6V In accordance
More information74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.
Rev. 3 8 May 29 Product data sheet 1. General description 2. Features 3. pplications 4. Ordering information The is a high-speed Si-gate CMOS device. The provides three inverting buffers with Schmitt trigger
More informationDATA SHEET. 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger INTEGRATED CIRCUITS
INTEGRTED IRUITS DT SHEET Supersedes data of 1998 pr 28 2004 Mar 18 FETURES 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 to 3.6 V MOS low power consumption Direct
More information74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting
Rev. 5 2 February 2016 Product data sheet 1. General description The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs
More information74AHC373; 74AHCT373. Octal D-type transparant latch; 3-state
Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
More information