74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
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1 Rev May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-. The provides a quad 2-input NOR function. Balanced propagation delays ll inputs have a Schmitt-trigger action Inputs accept voltages higher than V CC Input levels: For 74HC02: CMOS level For 74HCT02: TTL level ESD protection: HBM EI/JESD22-4E exceeds 2000 V MM EI/JESD22-5- exceeds 200 V CDM EI/JESD22-C0C exceeds 000 V Multiple package options Specified from 40 C to +85 C and from 40 C to +25 C Table. Ordering information Type number Package Temperature range Name Description Version 74HC02 74HC02D 40 C to +25 C SO4 plastic small outline package; 4 leads; SOT08- body width 3.9 mm 74HC02PW 40 C to +25 C TSSOP4 plastic thin shrink small outline package; 4 leads; SOT402- body width 4.4 mm 74HC02BQ 40 C to +25 C DHVQFN4 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body mm SOT762-
2 Table. Ordering information continued Type number Package Temperature range Name Description Version 74HCT02 74HCT02D 40 C to +25 C SO4 plastic small outline package; 4 leads; body width 3.9 mm 74HCT02PW 40 C to +25 C TSSOP4 plastic thin shrink small outline package; 4 leads; body width 4.4 mm 74HCT02BQ 40 C to +25 C DHVQFN4 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body mm 4. Functional diagram SOT08- SOT402- SOT B 2 2B Y 2Y B 4 4B 3Y 4Y mna aah084 B Y mna25 Fig. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) Product data sheet Rev May of 4
3 5. Pinning information 5. Pinning terminal index area Y VCC Y Y V CC 4Y B 2Y B 4 B 2Y B 4 3Y 2 2B 5 GND () Y 3B 2B GND B 3 GND 3 00aac920 00aac99 Transparent top view () The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO4 and TSSOP4 Fig 5. Pin configuration DHVQFN4 5.2 Pin description Table 2. Pin description Symbol Pin Description Y data output 2 data input B 3 data input 2Y 4 data output 2 5 data input 2B 6 data input GND 7 ground (0 V) 3 8 data input 3B 9 data input 3Y 0 data output 4 data input 4B 2 data input 4Y 3 data output V CC 4 supply voltage Product data sheet Rev May of 4
4 6. Functional description Table 3. Function table [] Input Output n nb ny L L H X H L H X L [] H = HIGH voltage level; L = LOW voltage level; X = don t care. 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 6034). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V V I input voltage V I IK input clamping current V I < 0.5 V [] 20 - m I OK output clamping current V O < 0.5 V or V O > V CC V [] m I O output current V O = 0.5 V to (V CC V) m I CC supply current m I GND ground current 75 - m T stg storage temperature C P tot total power dissipation T amb = 40 C to +25 C [2] mw [] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO4 packages: above 70 C the value of P tot derates linearly at 8 mw/k. For TSSOP4 packages: above 60 C the value of P tot derates linearly at 5.5 mw/k. For DHVQFN4 packages: above 60 C the value of P tot derates linearly at 4.5 mw/k. 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 74HC02 V CC supply voltage V V I input voltage V V O output voltage 0 - V CC V T amb ambient temperature C t/ V input transition rise and fall rate V CC = 3.0 V to 3.6 V ns/v V CC = 4.5 V to 5.5 V ns/v Product data sheet Rev May of 4
5 Table 5. Operating conditions continued Symbol Parameter Conditions Min Typ Max Unit 74HCT02 V CC supply voltage V V I input voltage V V O output voltage 0 - V CC V T amb ambient temperature C t/ V input transition rise and fall rate V CC = 4.5 V to 5.5 V ns/v 9. Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ Max Min Max Min Max 74HC02 V IH HIGH-level V CC = 2.0 V V input voltage V CC = 3.0 V V V CC = 5.5 V V V IL LOW-level V CC = 2.0 V V input voltage V CC = 3.0 V V V CC = 5.5 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 50 µ; V CC = 2.0 V V I O = 50 µ; V CC = 3.0 V V I O = 50 µ; V CC = 4.5 V V I O = 4.0 m; V CC = 3.0 V V I O = 8.0 m; V CC = 4.5 V V V OL LOW-level output voltage V I = V IH or V IL I O = 50 µ; V CC = 2.0 V V I O = 50 µ; V CC = 3.0 V V I O = 50 µ; V CC = 4.5 V V I O = 4.0 m; V CC = 3.0 V V I O = 8.0 m; V CC = 4.5 V V I I input leakage current V I = 5.5 V or GND; V CC = 0 V to 5.5 V µ I CC supply current V I =V CC or GND; I O = 0 ; µ V CC = 5.5 V C I input capacitance pf Product data sheet Rev May of 4
6 Table 6. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ Max Min Max Min Max 74HCT02 V IH HIGH-level V CC = 4.5 V to 5.5 V V input voltage V IL LOW-level V CC = 4.5 V to 5.5 V V input voltage V OH HIGH-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 50 µ V I O = 8.0 m V V OL LOW-level output voltage V I = V IH or V IL ; V CC = 4.5 V I O = 50 µ V I O = 8.0 m V I I input leakage current V I = 5.5 V or GND; V CC = 0 V to 5.5 V µ I CC supply current V I =V CC or GND; I O = 0 ; V CC = 5.5 V µ I CC C I additional supply current input capacitance per input pin; V I =V CC 2. V; other pins at V CC or GND; I O = 0 ; V CC = 4.5 V to 5.5 V 0. Dynamic characteristics m pf Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max Min Max 74HC02 t pd propagation n, nb to ny; see Figure 6 [2] delay V CC = 3.0 V to 3.6 V C L = 5 pf ns C L = 50 pf ns V CC = 4.5 V to 5.5 V C L = 5 pf ns C L = 50 pf ns C PD power dissipation capacitance C L = 50 pf; f i = MHz; V I = GND to V CC [3] pf Product data sheet Rev May of 4
7 Table 7. Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +25 C Unit Min Typ [] Max Min Max Min Max 74HCT02; V CC = 4.5 V to 5.5 V t pd propagation n, nb to ny; see Figure 6 [2] delay C L = 5 pf ns C L = 50 pf ns C PD power dissipation capacitance C L = 50 pf; f i = MHz; V I = GND to V CC [3] pf [] Typical values are measured at nominal supply voltage (V CC = 3.3 V and V CC = 5.0 V). [2] t pd is the same as t PLH and t PHL. [3] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V CC 2 f i N+Σ(C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; Σ(C L V 2 CC f o ) = sum of the outputs.. Waveforms V I n, nb input GND t PLH t PHL V OH ny output V OL 00aah085 Fig 6. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Input to output propagation delays Table 8. Measurement points Type Input Output 74HC V CC 0.5 V CC 74HCT02.5 V 0.5 V CC Product data sheet Rev May of 4
8 V I 90 % negative pulse GND 0 % t f t W t r V I positive pulse 0 % GND t r 90 % t W t f V CC G VI DUT VO RT CL 00aah768 Fig 7. Test data is given in Table 9. Definitions test circuit: R T = termination resistance should be equal to output impedance Z o of the pulse generator. C L = load capacitance including jig and probe capacitance. Load circuitry for measuring switching times Table 9. Test data Type Input Load Test V I t r, t f C L 74HC02 V CC 3.0 ns 5 pf, 50 pf t PLH, t PHL 74HCT V 3.0 ns 5 pf, 50 pf t PLH, t PHL Product data sheet Rev May of 4
9 2. Package outline SO4: plastic small outline package; 4 leads; body width 3.9 mm SOT08- D E X c y H E v M Z 4 8 Q pin index 2 ( ) 3 θ L p 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D () E () e H () E L L p Q v w y Z Note. Plastic or metal protrusions of 0.5 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT08-076E06 MS Fig 8. Package outline SOT08- (SO4) Product data sheet Rev May of 4
10 TSSOP4: plastic thin shrink small outline package; 4 leads; body width 4.4 mm SOT402- D E X c y H E v M Z 4 8 pin index 2 Q ( ) 3 θ 7 e b p w M detail X L p L mm scale DIMENSIONS (mm are the original dimensions) UNIT 2 3 b p c D () E (2) e H () E L L p Q v w y Z max. mm θ o 8 o 0 Notes. Plastic or metal protrusions of 0.5 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402- MO-53 EUROPEN PROJECTION ISSUE DTE Fig 9. Package outline SOT402- (TSSOP4) Product data sheet Rev May of 4
11 DHVQFN4: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 4 terminals; body 2.5 x 3 x 0.85 mm SOT762- D B E c terminal index area detail X terminal index area e e b 2 6 v M w M C C B y C C y L 7 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT () max. b c D () D h E () E h e e L v w y y mm Note. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 0. Package outline SOT762- (DHVQFN4) Product data sheet Rev May 2008 of 4
12 3. bbreviations Table 0. cronym CDM CMOS DUT ESD HBM LSTTL MM bbreviations Description Charged Device Model Complementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-power Schottky Transistor-Transistor Logic Machine Model 4. Revision history Table. Revision history Document ID Release date Data sheet status Change notice Supersedes Product data sheet - 74HC_HCT02_3 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 6: the conditions for input leakage current have been changed. 74HC_HCT02_ Product data sheet - 74HC_HCT02_2 74HC_HCT02_ Product specification - 74HC_HCT02_ 74HC_HCT02_ Product specification - - Product data sheet Rev May of 4
13 5. Legal information 5. Data sheet status Document status [][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 5.3 Disclaimers General Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Nexperia products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia accepts no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 6034) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Nexperia. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 5.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 6. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Product data sheet Rev May of 4
14 7. Contents General description Features Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents For more information, please visit: For sales office addresses, please send an to: salesaddresses@nexperia.com Date of release: 2 May 2008
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Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).
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More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 07 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and
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