INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.
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1 INTEGRATED CIRCUITS Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Jun 23
2 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for low voltage applications: 1.0V to 3.6V Accepts TTL input levels between V CC = 2.7V and V CC = 3.6V Typical V OLP (output ground bounce) < 0.8V at V CC = 3.3V, T amb = 25 C Typical V OHV (output V OH undershoot) > 2V at V CC = 3.3V, T amb =25 C Compare two 8-bit words Output capability: standard I CC category: MSI DESCRIPTION The is a high-speed Si-gate CMOS device, pin compatible with the 74HC/HCT688 The is an. It performs comparisons of two 8-bit binary or BCD words. The output provides P = Q (equal-to). QUICK REFERENCE DATA t PHL /t PLH SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay P n, Q n to P=Q C L = 15pF V CC = 3.3V 17 ns C I Input capacitance 3.5 pf C PD Power dissipation capacitance per gate V I = GND to V CC 1 22 pf NOTE: 1. C PD is used to determine the dynamic power dissipation (P D in W): P D = C PD V CC 2 f i + (C L V CC 2 f o ) where: f i = input frequency in MHz; C L = output load capacity in pf; f o = output frequency in MHz; V CC = supply voltage in V; (C L V CC 2 f o ) = sum of outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 20-Pin Plastic DIL 40 C to +125 C N N SOT Pin Plastic SO 40 C to +125 C D D SOT Pin Plastic SSOP Type II 40 C to +125 C DB DB SOT Pin Plastic TSSOP Type I 40 C to +125 C PW PW DH SOT360-1 PIN CONFIGURATION PIN DESCRIPTION PIN NO. SYMBOL FUNCTION E P0 Q V CC P = Q Q7 1 E Enable input (active LOW) 2, 4, 6, 8, 11, P0 to P7 Word inputs 13, 15, 17 P1 Q1 P P7 Q6 P6 3, 5, 7, 9, 12, 14, 16, 18 Q0 to Q7 Word inputs 10 GND Ground (0V) Q Q5 19 P=Q Equal to output P P5 20 V CC Positive Supply Voltage Q Q4 GND P4 SY Jun
3 LOGIC SYMBOL LOGIC DIAGRAM P0 P1 P2 P3 P4 P5 P6 P7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 P = Q E 19 P7 Q7 P6 Q6 P5 Q5 P4 Q4 P3 Q3 P = Q 1 SY00055 P2 Q2 LOGIC SYMBOL (IEEE/IEC) P1 Q G P 19 (P = Q) 1 Q SY00056 P0 Q0 E FUNCTION TABLE DATA Pn, Qn INPUTS ENABLE E SY00057 OUTPUT P = Q P = Q L L X H H P > Q L H P < Q L H NOTES: H = HIGH voltage level L = LOW voltage level X = Don t care 1998 Jun 23 3
4 ABSOLUTE MAXIMUM RATINGS 1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL PARAMETER CONDITIONS MIN MAX UNIT V CC DC supply voltage V I IK DC input diode current V I < 0.5 V or V 1 > V CC + 0.5V ± 20 ma I OK DC output diode current V O < 0.5 V or V 0 > V CC + 0.5V ± 50 ma I O DC output source or sink current standard outputs 0.5V < V O < V CC +0.5V ± 25 ma DC V ± I CC or GND current for types with GND, standard outputs ± I CC ± 50 ma T stg Storage temperature range C P tot power dissipation per package plastic DIL plastic mini-pack (SO) plastic medium-shrink SO (SSOP and TSSOP) for temperature range: 40 to +125 C above +70 C derate linearly with 12 mw/k above +70 C derate linearly with 8 mw/k above +60 C derate linearly with 5.5 mw/k NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolutemaximumrated conditions for extended periods may affect device reliability. 2. The performance capability of a highperformance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed mw RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V CC DC supply voltage see note V V I DC Input voltage 0 V CC V V O DC output voltage 0 V CC V T amb Operating ambient temperature range in freeair See DC and AC characteristics C t r, t f ( t/ v) Input rise and fall times V CC = 1.0V to 2.0V V CC = 2.0V to 2.7V V CC = 2.7V to 3.6V V CC = 3.6V to 5.5V NOTE: 1. The LV is guaranteed to function down to V CC = 1.0V (input levels GND or V CC ); DC characteristics are guaranteed from V CC = 1.2V to V CC = 5.5V ns/v 1998 Jun 23 4
5 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0V). LIMITS SYMBOL PARAMETER TEST CONDITIONS -40 C to +85 C -40 C to +125 C UNIT MIN TYP 1 MAX MIN MAX V CC = 1.2V HIGH level Input V CC = 2.0V V IH voltage V CC = 2.7 to 3.6V V V CC = 4.5 to 5.5V 0.7 V CC 0.7 V CC V CC = 1.2V LOW level Input V CC = 2.0V V IL voltage V CC = 2.7 to 3.6V V CC = 4.5 to V CC 0.3 V CC V CC = 1.2V; V I = V IH or V IL; I O = 100µA 1.2 V CC = 2.0V; V I = V IH or V IL; I O = 100µA HIGH level output voltage; all outputs uts V CC = 2.7V; V I = V IH or V IL; I O = 100µA V CC = 3.0V; V I = V IH or V IL; I O = 100µA V OH V CC = 4.5V; V I = V IH or V IL; I O = 100µA HIGH level output voltage; V CC = 3.0V; V I = V IH or V IL; I O = 6mA STANDARD outputs V CC = 4.5V; V I = V IH or V IL; I O = 12mA V CC = 1.2V; V I = V IH or V IL; I O = 100µA 0 V CC = 2.0V; V I = V IH or V IL; I O = 100µA LOW level output voltage; all outputs uts V CC = 2.7V; V I = V IH or V IL; I O = 100µA V CC = 3.0V; V I = V IH or V IL; I O = 100µA V OL V CC = 4.5V; V I = V IH or V IL; I O = 100µA V V V I I I CC LOW level output voltage; V CC = 3.0V; V I = V IH or V IL; I O = 6mA STANDARD outputs V CC = 4.5V; V I = V IH or V IL; I O = 12mA Input leakage current Quiescent supply current; MSI V CC = 5.5V; V I = V CC or GND µa V CC = 5.5V; V I = V CC or GND; I O = µa I CC Additional quiescent supply V CC = 2.7V to 3.6V; V I = V CC 0.6V µa current NOTE: 1. All typical values are measured at T amb = 25 C Jun 23 5
6 AC CHARACTERISTICS GND = 0V; t r = t f = 2.5ns; C L = 50pF; R L = 1KΩ SYMBOL PARAMETER WAVEFORM t PHL /t PLH t PHL /t PLH Propagation delay P n,q n to P=Q Propagation delay E to P=Q NOTES: 1. Unless otherwise stated, all typical values are at T amb = 25 C. 2. Typical value measured at V CC = 3.3V. 3. Typical value measured at V CC = 5.0V. CONDITION LIMITS 40 to +85 C 40 to +125 C UNIT V CC (V) MIN TYP 1 MAX MIN MAX ns 3.0 to to ns 3.0 to to AC WAVEFORMS V M = 1.5V at V CC 2.7V; V M = 0.5 V CC at V CC 2.7V. V OL and V OH are the typical output voltage drop that occur with the output load. TEST CIRCUIT V cc V I V l V O E INPUT GND V M PULSE GENERATOR R T D.U.T. C L 50pF R L = 1k t PLH t PHL V OH P = Q OUTPUT V OL Waveform 1. V M SV00195 Propagation delays from the enable input (E) to the equal-to output (P = Q). Test Circuit for Outputs DEFINITIONS R L = Load resistor C L = Load capacitance includes jig and probe capacitiance R T = Termination resistance should be equal to Z OUT of pulse generators. TEST V CC V I t PLH/ t PHL < 2.7V V V CC 2.7V P n, Q n INPUT V M V M Waveform V V CC SV00902 Load circuitry for switching times t PHL t PLH P = Q OUTPUT V M V M SV00194 Waveform 2. Propagation delays from the inputs (P n, Q n ) to the equal-to output (P = Q) Jun 23 6
7 APPLICATION INFORMATION Two or more 688 s may be cascaded to compare binary or BCD numbers of more than 8 bits. A n 688 A n A A = B A = B A = B OUTPUT B n 8 MSB B n-1 B 0 8 LSB ENABLE INPUT ENABLE INPUT ENABLE INPUT SV00196 Waveform 4. Binary or BCD comparator 1998 Jun 23 7
8 DIP20: plastic dual in-line package; 20 leads (300 mil) SOT Jun 23 8
9 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT Jun 23 9
10 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT Jun 23 10
11 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT Jun 23 11
12 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Preliminary Specification Product Specification Formative or in Design Preproduction Product Full Production This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California Telephone Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: Document order number: Jun 23 12
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Rev. 03 14 September 2005 Product data sheet 1. General description 2. Features 3. pplications 4. uick reference data he are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series.
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Rev. 06 25 November 2009 Product data sheet 1. General description 2. Features 3. Applications The is a 4-bit, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer.
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Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
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Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input
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Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device
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Rev. 3 4 July 2018 Product data sheet 1 General description 2 Features and benefits The is an. It performs comparisons of two 8-bit binary or BCD words. Inputs include clamp diodes. This enables the use
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Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use
More information74AHC1G00; 74AHCT1G00
74HC1G00; 74HCT1G00 Rev. 06 30 May 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G00 and 74HCT1G00 are high-speed Si-gate CMOS devices. They provide a 2-input
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Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders
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Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This
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74LV9 Rev. 04 December 007 Product data sheet. General description. Features. Ordering information The 74LV9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC9 and 74HCT9.
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Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
More information3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state
with 30 Ω termination resistors; 3-state Rev. 03 17 January 2005 Product data sheet 1. General description 2. Features The is a high performance BiCMOS product designed for V CC operation at 3.3 V. The
More information74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state
Rev. 03 20 January 2006 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with
More information74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.
Rev. 03 September 200 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin compatible
More information74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:
Rev. 02 15 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
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Rev. 02 5 November 2007 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
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Rev. 04 27 pril 2009 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC2G126 and 74HCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line
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Rev. 4 1 March 2016 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC244 and 74HCT244. The is an octal non-inverting buffer/line
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Rev. 5 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
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Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has four identical 2-input multiplexers with
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Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard
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Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
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Rev. 06 20 December 2007 Product data sheet. General description 2. Features 3. pplications The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HCU04. The is a general purpose
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Rev. 3 15 September 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a 9-bit parity generator or checker. Both even and odd parity outputs are available.
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Rev. 03 16 July 2007 Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238
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Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).
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with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer
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Rev. 02 7 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive
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Rev. 03 21 pril 2009 Product data sheet 1. General description 2. Features 3. pplications The is an 8 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage
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Rev. 06 4 June 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (P) inputs, set (SD)
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Rev. 3 5 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current
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Rev. 4 31 August 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number Package The is a low-voltage Si-gate CMOS device
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Rev. 03 12 November 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state
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Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate
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Rev. 3 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
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INTEGRTED IRUITS DT SHEET Supersedes data of 1998 pr 28 2004 Mar 18 FETURES 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 to 3.6 V MOS low power consumption Direct
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Rev. 03 20 December 2006 Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The is
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Rev. 4 9 December 2015 Product data sheet 1. General description The is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164. The is an 8-bit edge-triggered
More information74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state
Rev. 06 6 March 2006 Product data sheet. General description 2. Features 3. Quick reference data The is a high-performance BiCMOS product designed for V CC operation at 3.3 V. This device combines low
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Rev. 06 2 February 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The
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Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
More information74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.
Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state
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