The 74LVC1G11 provides a single 3-input AND gate.
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1 Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input can be driven from either. V or 5 V devices. This feature allows the use of this device in a mixed. V and 5 V environment. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall time. This device is fully specified for partial power-down applications using I OFF. The I OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The provides a single -input ND gate. Wide supply voltage range from 1.5 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.5 V to 1.95 V) JESD8-5 (2. V to 2.7 V) JESD8-/JESD (2.7 V to. V). ±24 m output drive (V CC =.0 V) ESD protection: HM JESD D exceeds 2000 V MM JESD exceeds 200 V CMOS low power consumption Latch-up performance exceeds 250 m Direct interface with TTL levels Multiple package options Specified from 40 C to+85 C and 40 C to +125 C
2 . Ordering information Table 1. Type number 4. Marking Ordering information Package Temperature range Name Description Version GW 40 C to +125 C SC-88 plastic surface-mounted package; leads SOT GV 40 C to +125 C SC-74 plastic surface-mounted package; leads SOT457 GM 40 C to +125 C XSON plastic extremely thin small outline package; SOT88 no leads; terminals; body mm GF 40 C to +125 C XSON plastic extremely thin small outline package; no leads; terminals; body mm SOT891 Table 2. Marking Type number GW GV GM GF Marking code VU V11 VU VU 5. Functional diagram 1 Y 4 C 1 & 4 Y 001aac0 001aac029 C 001aac00 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig. Logic diagram _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
3 . Pinning information.1 Pinning 1 C 1 C GND 2 5 V CC 1 C GND 2 5 V CC GND 2 5 V CC 4 Y 4 Y 001aac849 4 Y 001aaf aac02 Transparent top view Transparent top view Fig 4. Pin configuration SOT and SOT457 Fig 5. Pin configuration SOT88 Fig. Pin configuration SOT891.2 Pin description Table. Pin description Symbol Pin Description 1 data input GND 2 ground (0 V) data input Y 4 data output V CC 5 supply voltage C data input 7. Functional description Table 4. Function table [1] Input Output C Y H H H H L X X L X L X L X X L L [1] H = HIGH voltage level; L = LOW voltage level; X = don t care. _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September 200 of 15
4 8. Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IEC 014). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0 V - 50 m V I input voltage [1] V I OK output clamping current V O > V CC or V O < 0 V - ±50 m V O output voltage ctive mode [1][2] 0.5 V CC V Power-down mode [1][2] V I O output current V O = 0 V to V CC - ±50 m I CC supply current m I GND ground current m P tot total power dissipation T amb = 40 C to +125 C [] mw T stg storage temperature C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When V CC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [] For SC-88 and SC-74 packages: above 87.5 C the value of P tot derates linearly with 4.0 mw/k. For XSON packages: above 45 C the value of P tot derates linearly with 2.4 mw/k. 9. Recommended operating conditions Table. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage V V I input voltage V V O output voltage ctive mode 0 - V CC V Power-down mode; V CC = 0 V V T amb ambient temperature C t/ V input transition rise and fall rate V CC = 1.5 V to 2.7 V 0-20 ns/v V CC = 2.7 V to 5.5 V 0-10 ns/v _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
5 10. Static characteristics Table 7. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ [1] Max Unit T amb = 40 C to +85 C V IH HIGH-level input voltage V CC = 1.5 V to 1.95 V 0.5 V CC - - V V CC = 2. V to 2.7 V V V CC = 2.7 V to. V V V CC = 4.5 V to 5.5 V 0.7 V CC - - V V IL LOW-level input voltage V CC = 1.5 V to 1.95 V V CC V V CC = 2. V to 2.7 V V V CC = 2.7 V to. V V V CC = 4.5 V to 5.5 V V CC V V OH HIGH-level output voltage V I = V IH or V IL I O = 100 µ; V CC = 1.5 V to 5.5 V V CC V I O = 4 m; V CC = 1.5 V V I O = 8 m; V CC = 2. V V I O = 12 m; V CC = 2.7 V V I O = 24 m; V CC =.0 V V I O = 2 m; V CC = 4.5 V V V OL LOW-level output voltage V I = V IH or V IL I O = 100 µ; V CC = 1.5 V to 5.5 V V I O = 4 m; V CC = 1.5 V V I O = 8 m; V CC = 2. V V I O = 12 m; V CC = 2.7 V V I O = 24 m; V CC =.0 V V I O = 2 m; V CC = 4.5 V V I I input leakage current V I = 5.5 V or GND; V CC = 5.5 V - ±0.1 ±5 µ I OFF power-off leakage current V I or V O = 5.5 V; V CC = 0 V - ±0.1 ±10 µ I CC supply current V I = V CC or GND; I O = 0 ; µ V CC = 5.5 V I CC additional supply current V I = V CC 0. V; I O = 0 ; µ V CC = 2. V to 5.5 V; per pin C I input capacitance pf T amb = 40 C to +125 C V IH HIGH-level input voltage V CC = 1.5 V to 1.95 V 0.5 V CC - - V V CC = 2. V to 2.7 V V V CC = 2.7 V to. V V V CC = 4.5 V to 5.5 V 0.7 V CC - - V V IL LOW-level input voltage V CC = 1.5 V to 1.95 V V CC V V CC = 2. V to 2.7 V V V CC = 2.7 V to. V V V CC = 4.5 V to 5.5 V V CC V _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
6 Table 7. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ [1] Max Unit V OH HIGH-level output voltage V I = V IH or V IL I O = 100 µ; V CC = 1.5 V to 5.5 V V CC V I O = 4 m; V CC = 1.5 V V I O = 8 m; V CC = 2. V V I O = 12 m; V CC = 2.7 V V I O = 24 m; V CC =.0 V V I O = 2 m; V CC = 4.5 V V V OL LOW-level output voltage V I = V IH or V IL I O = 100 µ; V CC = 1.5 V to 5.5 V V I O = 4 m; V CC = 1.5 V V I O = 8 m; V CC = 2. V V I O = 12 m; V CC = 2.7 V V I O = 24 m; V CC =.0 V V I O = 2 m; V CC = 4.5 V V I I input leakage current V I = 5.5 V or GND; V CC = 5.5 V - - ±100 µ I OFF power-off leakage current V I or V O = 5.5 V; V CC = 0 V - - ±200 µ I CC supply current V I = V CC or GND; I O = 0 ; µ V CC = 5.5 V I CC additional supply current V I = V CC 0. V; I O = 0 ; V CC = 2. V to 5.5 V; per pin µ [1] ll typical values are measured at T amb = 25 C. 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max t pd propagation delay, and C to Y; see Figure 7 [2] V CC = 1.5 V to 1.95 V ns V CC = 2. V to 2.7 V ns V CC = 2.7 V ns V CC =.0 V to. V ns V CC = 4.5 V to 5.5 V ns _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September 200 of 15
7 Table 8. Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 8. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit C PD power dissipation capacitance [1] Typical values are measured at T amb =25 C and V CC = 1.8 V, 2.5 V, 2.7 V,. V and 5.0 V respectively. [2] t pd is the same as t PLH and t PHL. [] C PD is used to determine the dynamic power dissipation (P D in µw). P D =C PD V 2 CC f i N+Σ(C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; Σ(C L V 2 CC f o ) = sum of the outputs. 12. Waveforms Min Typ [1] Max Min Max V I = GND to V CC ; V CC =. V [] pf,, C input V I GND V M V OH t PHL t PLH Y output V M V OL t THL 001aac01 Fig 7. Measurement points are given in Table 9. V OL and V OH are typical output voltage drop that occur with the output load. The input (,, C) to output (Y) propagation delays Table 9. Measurement points Supply voltage Input Output V CC V M V M 1.5 V to 1.95 V 0.5 V CC 0.5 V CC 2. V to 2.7 V 0.5 V CC 0.5 V CC 2.7 V 1.5 V 1.5 V.0 V to. V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 V CC 0.5 V CC _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
8 V EXT V CC PULSE GENERTOR V I DUT V O RL RT CL RL mna1 Fig 8. Test data is given in Table 10. Definitions for test circuit: R L = Load resistance. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Z o of the pulse generator. V EXT = External voltage for measuring switching times. Load circuitry for switching times Table 10. Test data Supply voltage Input Load V EXT V CC V I t r =t f C L R L t PLH, t PHL 1.5 V to 1.95 V V CC 2.0 ns 0 pf 1 kω open 2. V to 2.7 V V CC 2.0 ns 0 pf 500 Ω open 2.7 V 2.7 V 2.5 ns 50 pf 500 Ω open.0 V to. V 2.7 V 2.5 ns 50 pf 500 Ω open 4.5 V to 5.5 V V CC 2.5 ns 50 pf 500 Ω open _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
9 1. Package outline Plastic surface-mounted package; leads SOT D E X y H E v M 5 4 Q pin 1 index c e1 bp w M Lp e detail X mm scale DIMENSIONS (mm are the original dimensions) UNIT 1 max mm bp c D E e e 1 H E L p Q v w y OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT SC Fig 9. Package outline SOT (SC-88) _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
10 Plastic surface-mounted package (TSOP); leads SOT457 D E X y H E v M 5 4 Q pin 1 index c Lp e bp w M detail X mm scale DIMENSIONS (mm are the original dimensions) UNIT 1 bp c D E e H E L p Q v w y mm OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT457 SC Fig 10. Package outline SOT457 (SC-74) _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
11 XSON: plastic extremely thin small outline package; no leads; terminals; body 1 x 1.45 x 0.5 mm SOT b L 1 L 4 (2) e 5 4 e 1 e 1 (2) 1 D E terminal 1 index area mm DIMENSIONS (mm are the original dimensions) UNIT mm (1) max 1 max Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. b D E e e 1 L scale L OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT88 MO Fig 11. Package outline SOT88 (XSON) _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
12 XSON: plastic extremely thin small outline package; no leads; terminals; body 1 x 1 x 0.5 mm SOT b L 1 L e 5 4 e 1 e 1 1 D E terminal 1 index area mm scale DIMENSIONS (mm are the original dimensions) UNIT max 1 max b D E e e 1 L L 1 mm OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT Fig 12. Package outline SOT891 (XSON) _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
13 14. bbreviations Table 11. cronym CMOS DUT ESD HM MM TTL bbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human ody Model Machine Model Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes _ Product data sheet - _2 Modifications: dded type number GF (XSON/SOT891 package) _ Product data sheet - _1 Modifications: Package outline and marking code added _ Product data sheet - - _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
14 1. Legal information 1.1 Data sheet status Document status [1][2] Product status [] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 1. Disclaimers General Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 014) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 1.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ _ Koninklijke Philips Electronics N.V ll rights reserved. Product data sheet Rev. 0 September of 15
15 18. Contents 1 General description Features Ordering information Marking Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. Koninklijke Philips Electronics N.V ll rights reserved. For more information, please visit: For sales office addresses, to: sales.addresses@ Date of release: September 200 Document identifier: _
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Rev. 6 27 June 2012 Product data sheet 1. General description The provides the single 2-input NND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
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Rev. 1 22 August 2012 Product data sheet 1. General description The is a single buffer and single inverter. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
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Rev. 12 5 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH
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Rev. 6 17 September 2015 Product data sheet 1. General description The provides two low-power, low-voltage buffers. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise
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Rev. 12 8 June 2018 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number The provides a buffer function with Schmitt trigger
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Rev. 12 22 May 2018 Product data sheet 1 General description 2 Features and benefits The provides the inverting buffer. Input can be driven from either 3.3 V or 5 V devices. These features allow the use
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Rev. 2 12 December 2016 Product data sheet 1. General description The provides a single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q-output on the LOW-to-HIGH
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Rev. 14 8 June 2018 Product data sheet 1 General description 2 Features and benefits The provides the non-inverting buffer. The output of this device is an open drain and can be connected to other open-drain
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Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
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Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 9 8 June 2018 Product data sheet 1 General description 2 Features and benefits The provides the single inverting buffer. Schmitt trigger action at all inputs makes the circuit tolerant to slower input
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Rev. 1 28 November 2017 Product data sheet 1 General description 2 Features and benefits The provides the single buffer function. This device ensures a very low static and dynamic power consumption across
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Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in
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Rev. 3 28 January 2019 Product data sheet 1. General description 2. Features and benefits 3. Ordering information Table 1. Ordering information Type number Package The provides a buffer function with Schmitt
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Rev. 03 21 pril 2009 Product data sheet 1. General description 2. Features 3. pplications The is an 8 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage
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Rev. 12 2 December 2016 Product data sheet 1. General description The provides one non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).
More informationThe 74LVC2G32 provides a 2-input OR gate function.
Rev. 11 8 pril 2013 Product data sheet 1. General description The provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
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Rev. 06 2 February 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The
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Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current
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Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
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Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 2 8 June 26 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. 1.2
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Rev. 5 8 October 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 2-input ND gate. Inputs include clamp diodes. This enables the use of current
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Rev. 5 29 September 2017 Product data sheet 1 General description 2 Features and benefits The provides the single 2-input ND gate with an open-drain output. The output of the device is an open-drain and
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Rev. 6 15 ugust 2012 Product data sheet 1. General description The provides a single non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE).
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Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW
More informationThe 74AXP1G04 is a single inverting buffer.
Rev. 1 25 August 2014 Product data sheet 1. General description The is a single inverting buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This
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Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
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Rev. 2 8 May 2013 Product data sheet 1. General description The is a high-speed Si-gate CMOS devices. This device provides a dual non-inverting buffer/line driver with 3-state output. The 3-state output
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Rev. 8 12 February 2018 Product data sheet 1 General description 2 Features and benefits The provides the single inverting buffer with open-drain output. The output of the device is an open drain and can
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Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance
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Rev. 11 10 ugust 2018 Product data sheet 1. General description 2. Features and benefits 3. pplications The provides two inverting buffers with Schmitt-trigger input. It is capable of transforming slowly
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Rev. 06 19 February 2008 Product data sheet 1. General description The is a single positive edge triggered -type flip-flop with individual data () inputs, clock (P) inputs, set (S) and reset (R) inputs,
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Rev. 1 9 October 2014 Product data sheet 1. General description The is a dual inverter with Schmitt-trigger inputs. It transforms slowly changing input signals into sharply defined, jitter-free output
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Rev. 1 22 November 2017 Product data sheet 1 General description 2 Features and benefits 3 pplications The is a single, level translating 2-input NND gate. The low threshold inputs support 1.8 V input
More informationNXP 74HC_HCT1G00 2-input NAND gate datasheet
NXP 74HC_HCT1G00 datasheet http://www.manuallib.com/nxp/74hc-hct1g00-2-input-nand-gate-datasheet.html The is a single. Inputs include clamp diodes that enable the use of current limiting resistors to interface
More informationThe 74LVC10A provides three 3-input NAND functions.
Triple 3-input NND gate Rev. 5 7 November 20 Product data sheet. General description The provides three 3-input NND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows
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Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.
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Rev. 04 17 March 2009 Product data sheet 1. General description The is a for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE), an active HIGH
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Rev. 04 16 June 2006 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
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Rev. 7 28 June 2012 Product data sheet 1. General description The provides the single inverting buffer with open-drain output. The output of the device is an open drain and can be connected to other open-drain
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Rev. 2 16 September 2015 Product data sheet 1. General description The is a configurable multiple function gate with Schmitt-trigger inputs. The device can be configured as any of the following logic functions
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Rev. 10 15 December 2016 Product data sheet 1. General description The provides two inverting buffers with Schmitt-trigger input. It is capable of transforming slowly changing input signals into sharply
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Rev. 13 20 pril 2018 Product data sheet 1 General description 2 Features and benefits The provides a 2-input NOR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows
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Rev. 5 29 June 2012 Product data sheet 1. General description The provides the single unbuffered inverting gate. This device ensures a very low static and dynamic power consumption across the entire V
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