74LVC1G General description. 2. Features. Single D-type flip-flop with set and reset; positive edge trigger

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1 Rev February 2008 Product data sheet 1. General description The is a single positive edge triggered -type flip-flop with individual data () inputs, clock (P) inputs, set (S) and reset (R) inputs, and complementary and outputs. 2. Features This device is fully specified for partial power-down applications using I OFF. The I OFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the output on the LOW-to-HIGH transition of the clock pulse. The inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity omplies with JEE standard: JES8-7 (1.65 V to 1.95 V) JES8-5 (2.3 V to 2.7 V) JES8-B/JES36 (2.7 V to 3.6 V) ±24 m output drive (V = 3.0 V) ES protection: HBM EI/JES22-114E exceeds 2000 V MM EI/JES exceeds 200 V MOS low power consumption Latch-up performance exceeds 250 m irect interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from 40 to+85 and 40 to +125

2 3. Ordering information Table 1. Type number 4. Marking Ordering information Package Temperature range Name escription Version P 40 to +125 TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-2 body width 3 mm; lead length 0.5 mm 40 to +125 VSSOP8 plastic very thin shrink small outline package; SOT leads; body width 2.3 mm GT 40 to +125 XSON8 plastic extremely thin small outline package; SOT833-1 no leads; 8 terminals; body mm GM 40 to +125 XFN8U plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body mm SOT902-1 Table 2. Marking codes Type number P GT GM Marking code V74 V74 V74 V74 5. Functional diagram S S P P FF R R 001aah757 S 1 1 R 001aah758 Fig 1. Logic symbol Fig 2. IE logic symbol _6 Product data sheet Rev February of 19

3 R S mna421 P Fig 3. Logic diagram 6. Pinning information 6.1 Pinning P 1 8 V 2 7 S 3 6 R GN aab659 Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) terminal 1 index area V P 1 8 V S P 2 7 S R R GN aab658 Transparent top view GN Transparent top view 001aaf641 Fig 5. Pin configuration SOT833-1 (XSON8) Fig 6. Pin configuration SOT902-1 (XFN8U) _6 Product data sheet Rev February of 19

4 6.2 Pin description Table 3. Pin description Symbol Pin escription SOT505-2, SOT765-1, SOT902-1 SOT833-1 P 1 7 clock input (LOW-to-HIGH, edge-triggered) 2 6 data input 3 5 complement output GN 4 4 ground (0 V) 5 3 true output R 6 2 asynchronous reset-direct input (active LOW) S 7 1 asynchronous set-direct input (active LOW) V 8 8 supply voltage 7. Functional description Table 4. Function table for asynchronous operation [1] Input Output S R P L H X X H L H L X X L H L L X X H H [1] H = HIGH voltage level; L = LOW voltage level; X = don t care. Table 5. Function table for synchronous operation [1] Input Output S R P n+1 n+1 H H L L H H H H H L [1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH P transition; n+1 = state after the next LOW-to-HIGH P transition. _6 Product data sheet Rev February of 19

5 8. Limiting values Table 6. Limiting values In accordance with the bsolute Maximum Rating System (IE 60134). Voltages are referenced to GN (ground = 0 V). Symbol Parameter onditions Min Max Unit V supply voltage V I IK input clamping current V I <0V 50 - m V I input voltage [1] V I OK output clamping current V O >V or V O <0V - ±50 m V O output voltage ctive mode [1] 0.5 V V Power-down mode [1][2] V I O output current V O =0 VtoV - ±50 m I supply current m I GN ground current m P tot total power dissipation T amb = 40 to +125 [3] mw T stg storage temperature [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When V = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. [3] For TSSOP8 packages: above 55 the value of P tot derates linearly with 2.5 mw/k. For VSSOP8 packages: above 110 the value of P tot derates linearly with 8.0 mw/k. For XSON8 and XFN8U packages: above 45 the value of P tot derates linearly with 2.4 mw/k. 9. Recommended operating conditions Table 7. Operating conditions Symbol Parameter onditions Min Max Unit V supply voltage V V I input voltage V V O output voltage ctive mode 0 V V Power-down mode; V = 0 V V T amb ambient temperature t/ V input transition rise and fall rate V = 1.65 V to 2.7 V - 20 ns/v V = 2.7 V to 5.5 V - 10 ns/v _6 Product data sheet Rev February of 19

6 10. Static characteristics Table 8. Static characteristics t recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter onditions Min Typ [1] Max Unit T amb = 40 to +85 V IH HIGH-level input voltage V = 1.65 V to 1.95 V 0.65 V - - V V = 2.3 V to 2.7 V V V = 2.7 V to 3.6 V V V = 4.5 V to 5.5 V 0.7 V - - V V IL LOW-level input voltage V = 1.65 V to 1.95 V V V V = 2.3 V to 2.7 V V V = 2.7 V to 3.6 V V V = 4.5 V to 5.5 V V V V OH HIGH-level output voltage V I = V IH or V IL I O = 100 µ; V = 1.65 V to 5.5 V V V I O = 4 m; V = 1.65 V V I O = 8 m; V = 2.3 V V I O = 12 m; V = 2.7 V V I O = 24 m; V = 3.0 V V I O = 32 m; V = 4.5 V V V OL LOW-level output voltage V I = V IH or V IL I O = 100 µ; V = 1.65 V to 5.5 V V I O = 4 m; V = 1.65 V V I O = 8 m; V = 2.3 V V I O = 12 m; V = 2.7 V V I O = 24 m; V = 3.0 V V I O = 32 m; V = 4.5 V V I I input leakage current V I = 5.5 V or GN; - ±0.1 ±5 µ V = 0 V to 5.5 V I OFF power-off leakage current V I or V O = 5.5 V; V = 0 V - ±0.1 ±10 µ I supply current V I = 5.5 V or GN; µ V = 1.65 V to 5.5 V; I O =0 I additional supply current per pin; V I = V 0.6 V; I O = 0 ; µ V = 2.3 V to 5.5 V I input capacitance pf _6 Product data sheet Rev February of 19

7 Table 8. Static characteristics continued t recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter onditions Min Typ [1] Max Unit T amb = 40 to +125 V IH HIGH-level input voltage V = 1.65 V to 1.95 V 0.65 V - - V V = 2.3 V to 2.7 V V V = 2.7 V to 3.6 V V V = 4.5 V to 5.5 V 0.7 V - - V V IL LOW-level input voltage V = 1.65 V to 1.95 V V V V = 2.3 V to 2.7 V V V = 2.7 V to 3.6 V V V = 4.5 V to 5.5 V V V V OH HIGH-level output voltage V I = V IH or V IL I O = 100 µ; V = 1.65 V to 5.5 V V V I O = 4 m; V = 1.65 V V I O = 8 m; V = 2.3 V V I O = 12 m; V = 2.7 V V I O = 24 m; V = 3.0 V V I O = 32 m; V = 4.5 V V V OL LOW-level output voltage V I = V IH or V IL I O = 100 µ; V = 1.65 V to 5.5 V V I O = 4 m; V = 1.65 V V I O = 8 m; V = 2.3 V V I O = 12 m; V = 2.7 V V I O = 24 m; V = 3.0 V V I O = 32 m; V = 4.5 V V I I input leakage current V I = 5.5 V or GN; - - ±20 µ V = 0 V to 5.5 V I OFF power-off leakage current V I or V O = 5.5 V; V = 0 V - - ±20 µ I supply current V I = 5.5 V or GN; µ V = 1.65 V to 5.5 V; I O =0 I additional supply current per pin; V I = V 0.6 V; I O = 0 ; V = 2.3 V to 5.5 V µ [1] ll typical values are measured at T amb = 25. _6 Product data sheet Rev February of 19

8 11. ynamic characteristics Table 9. ynamic characteristics Voltages are referenced to GN (ground = 0 V); for test circuit see Figure 9. Symbol Parameter onditions 40 to to +125 Unit Min Typ [1] Max Min Max t pd propagation delay P to, ; see Figure 7 [2] V = 1.65 V to 1.95 V ns V = 2.3 V to 2.7 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns V = 4.5 V to 5.5 V ns S to, ; see Figure 8 [2] V = 1.65 V to 1.95 V ns V = 2.3 V to 2.7 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns V = 4.5 V to 5.5 V ns R to, ; see Figure 8 [2] V = 1.65 V to 1.95 V ns V = 2.3 V to 2.7 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns V = 4.5 V to 5.5 V ns t W pulse width P HIGH or LOW; see Figure 7 V = 1.65 V to 1.95 V ns V = 2.3 V to 2.7 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns V = 4.5 V to 5.5 V ns S and R LOW; see Figure 8 V = 1.65 V to 1.95 V ns V = 2.3 V to 2.7 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns V = 4.5 V to 5.5 V ns _6 Product data sheet Rev February of 19

9 Table 9. ynamic characteristics continued Voltages are referenced to GN (ground = 0 V); for test circuit see Figure 9. Symbol Parameter onditions 40 to to +125 Unit Min Typ [1] Max Min Max t rec recovery time S or R; see Figure 8 V = 1.65 V to 1.95 V ns V = 2.3 V to 2.7 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns V = 4.5 V to 5.5 V ns t su set-up time to P; see Figure 7 V = 1.65 V to 1.95 V ns V = 2.3 V to 2.7 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns V = 4.5 V to 5.5 V ns t h hold time to P; see Figure 7 V = 1.65 V to 1.95 V ns V = 2.3 V to 2.7 V ns V = 2.7 V ns V = 3.0 V to 3.6 V ns V = 4.5 V to 5.5 V ns f max maximum P; see Figure 7 frequency V = 1.65 V to 1.95 V MHz V = 2.3 V to 2.7 V MHz V = 2.7 V MHz V = 3.0 V to 3.6 V MHz V = 4.5 V to 5.5 V MHz P power dissipation capacitance V I = GN to V ; V = 3.3 V [3] pf [1] Typical values are measured at T amb =25 and V = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. [2] t pd is the same as t PLH and t PHL. [3] P is used to determine the dynamic power dissipation (P in µw). P = P V 2 f i N+Σ( L V 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; L = output load capacitance in pf; V = supply voltage in V; N = number of inputs switching; Σ( L V 2 f o ) = sum of outputs. _6 Product data sheet Rev February of 19

10 12. Waveforms V I t W P input V M GN 1/f max V I input V M GN V OH t su t h t PHL t su t h t PLH output V M V OL V OH output V M V OL t PLH t PHL mnb141 Fig 7. Measurement points are given in Table 10. The shaded areas indicate when the input is permitted to change for predictable output performance. V OL and V OH are typical output voltage levels that occur with the output load. The clock input (P) to output (, ) propagation delays, the clock pulse width, the to P set-up, the P to hold times and the maximum frequency Table 10. Measurement points Supply voltage Input Output V V M V M 1.65 V to 1.95 V 0.5 V 0.5 V 2.3 V to 2.7 V 0.5 V 0.5 V 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 V 0.5 V _6 Product data sheet Rev February of 19

11 V I P input V M GN t rec V I S input V M GN V I t W t W t rec R input V M GN t PLH t PHL V OH output V M V OL V OH output V M V OL t PHL t PLH mnb142 Fig 8. Measurement points are given in Table 10. V OL and V OH are typical output voltage levels that occur with the output load. The set (S) and reset (R) input to output (, ) propagation delays, the set and reset pulse widths and the R to P recovery time _6 Product data sheet Rev February of 19

12 V EXT V G V I UT V O RL RT L RL mna616 Fig 9. Test data is given in Table 11. efinitions for test circuit: R L = Load resistance. L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Z o of the pulse generator. V EXT = External voltage for measuring switching times. Load circuitry for switching times Table 11. Test data Supply voltage Input Load V EXT V V I t r, t f L R L t PLH, t PHL t PZH, t PHZ t PZL, t PLZ 1.65 V to 1.95 V V 2.0 ns 30 pf 1 kω open GN 2V 2.3 V to 2.7 V V 2.0 ns 30 pf 500 Ω open GN 2V 2.7 V 2.7 V 2.5 ns 50 pf 500 Ω open GN 6 V 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pf 500 Ω open GN 6 V 4.5 V to 5.5 V V 2.5 ns 50 pf 500 Ω open GN 2V _6 Product data sheet Rev February of 19

13 13. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 E X c y H E v M Z ( 3 ) pin 1 index L p θ L 1 4 detail X e b p w M mm scale IMENSIONS (mm are the original dimensions) UNIT max. 1 mm b p c (1) E (1) e H E L L p v w y Z (1) θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENES IE JEE JEIT EUROPEN PROJETION ISSUE TE SOT Fig 10. Package outline SOT505-2 (TSSOP8) _6 Product data sheet Rev February of 19

14 VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 E X c y H E v M Z pin 1 index ( 3 ) L p θ 1 4 detail X L e b p w M mm scale IMENSIONS (mm are the original dimensions) UNIT max. 1 mm b p c (1) E (2) e H E L L p v w y Z (1) θ Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included OUTLINE VERSION REFERENES IE JEE JEIT EUROPEN PROJETION ISSUE TE SOT765-1 MO Fig 11. Package outline SOT765-1 (VSSOP8) _6 Product data sheet Rev February of 19

15 XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 b L 1 L 4 (2) e e 1 e 1 e 1 8 (2) 1 E terminal 1 index area mm IMENSIONS (mm are the original dimensions) scale UNIT (1) max 1 max b E e e 1 L L 1 mm Notes 1. Including plating thickness. 2. an be visible in some manufacturing processes. OUTLINE VERSION REFERENES IE JEE JEIT EUROPEN PROJETION ISSUE TE SOT MO Fig 12. Package outline SOT833-1 (XSON8) _6 Product data sheet Rev February of 19

16 XFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1 terminal 1 index area B E 1 detail X L 1 e e L 4 v M w M B y 1 y 3 5 metal area not for soldering b e e terminal 1 index area 8 X mm IMENSIONS (mm are the original dimensions) UNIT max mm b E e e 1 L L 1 v scale 0.1 w 0.05 y y OUTLINE VERSION SOT902-1 REFERENES IE JEE JEIT MO EUROPEN PROJETION ISSUE TE Fig 13. Package outline SOT902-1 (XFN8U) _6 Product data sheet Rev February of 19

17 14. bbreviations Table 12. cronym MOS TTL HBM ES MM UT bbreviations escription omplementary Metal-Oxide Semiconductor Transistor-Transistor Logic Human Body Model ElectroStatic ischarge Machine Model evice Under Test 15. Revision history Table 13. Revision history ocument I Release date ata sheet status hange notice Supersedes _ Product data sheet - _5 Modifications: Figure 13: package outline drawing updated to latest version Figure 1 and Figure 2: pin numbers removed from logic symbols _ Product data sheet - _4 _ Product data sheet - _3 _ Product specification - _2 _ Product specification - _1 _ Product specification - - _6 Product data sheet Rev February of 19

18 16. Legal information 16.1 ata sheet status ocument status [1][2] Product status [3] efinition Objective [short] data sheet evelopment This document contains data from the objective specification for product development. Preliminary [short] data sheet ualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section efinitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL efinitions raft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail isclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IE 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the haracteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 17. ontact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com _6 Product data sheet Rev February of 19

19 18. ontents 1 General description Features Ordering information Marking Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics ynamic characteristics Waveforms Package outline bbreviations Revision history Legal information ata sheet status efinitions isclaimers Trademarks ontact information ontents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com ate of release: 19 February 2008 ocument identifier: _6