74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state

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1 Rev January 2006 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with JEEC standard no. 7. The is an octal -type transparent latch featuring separate -type inputs for each latch and 3-state outputs for bus oriented applications. latch enable (LE) input and an output enable (OE) input are common to all latches. The 74HC373; HCT373 consists of eight -type transparent latches with 3-state true outputs. When LE is HIGH, data at the n inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the highimpedance OFF-state. Operation of the OE input does not affect the state of the latches. The is functionally identical to: 74HC533; 74HCT533: but inverted outputs 74HC563; 74HCT563: but inverted outputs and different pin arrangement 74HC573; 74HCT573: but different pin arrangement 3-state non-inverting outputs for bus oriented applications Common 3-state output enable input Functionally identical to the 74HC563; 74HCT563, 74HC573; 74HCT573 and 74HC533; 74HCT533 ES protection: HBM EI/JES C exceeds V MM EI/JES exceeds 200 V Specified from 40 C to+85 C and from 40 C to +125 C

2 3. Quick reference data 4. Ordering information Table 1: Quick reference data GN = 0 V; T amb = 25 C; t r = t f = 6 ns. Symbol Parameter Conditions Min Typ Max Unit 74HC373 t PHL, t PLH propagation delay V CC =5V; C L =15pF n to Qn ns LE to Qn ns C i input capacitance pf C P power dissipation capacitance per latch; V I = GN to V CC [1] pf 74HCT373 t PHL, t PLH propagation delay V CC =5V; C L =15pF n to Qn ns LE to Qn ns C i input capacitance pf C P power dissipation capacitance per latch; V I = GN to (V CC 1.5 V) [1] C P is used to determine the dynamic power dissipation (P in µw). P =C P V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. [1] pf Table 2: Ordering information Type number Package Temperature range Name escription Version 74HC373 74HC373N 40 C to +125 C IP20 plastic dual in-line package; 20 leads (300 mil) SOT HC C to +125 C SO20 plastic small outline package; 20 leads; SOT163-1 body width 7.5 mm 74HC373B 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; SOT339-1 body width 5.3 mm 74HC373PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm 74HC373BQ 40 C to +125 C HVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body mm SOT764-1 Product data sheet Rev January of 26

3 Table 2: Type number Ordering information continued Package Temperature range Name escription Version 74HCT373 74HCT373N 40 C to +125 C IP20 plastic dual in-line package; 20 leads (300 mil) SOT HCT C to +125 C SO20 plastic small outline package; 20 leads; SOT163-1 body width 7.5 mm 74HCT373B 40 C to +125 C SSOP20 plastic shrink small outline package; 20 leads; body width 5.3 mm SOT HCT373PW 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT HCT373BQ 40 C to +125 C HVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body mm SOT Functional diagram LTCH 1 TO 8 3-STTE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q LE OE 001aae050 Fig 1. Functional diagram OE 1 EN LE 11 C LE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q aae aae049 Fig 2. Logic symbol Fig 3. IEC logic symbol Product data sheet Rev January of 26

4 LE LE LE Q LE 001aae051 Fig 4. Logic diagram (one latch) Q Q Q Q Q Q Q Q LTCH 1 LTCH 2 LTCH 3 LTCH 4 LTCH 5 LTCH 6 LTCH 7 LTCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aae052 Fig 5. Logic diagram Product data sheet Rev January of 26

5 6. Pinning information 6.1 Pinning 74HC373 74HCT373 74HC373 74HCT373 OE Q V CC Q7 7 6 terminal 1 index area Q0 0 1 OE VCC Q7 7 6 Q Q6 Q Q6 Q Q5 Q Q5 2 3 Q Q4 2 3 Q GN (1) Q4 GN LE GN LE 001aae aae046 Transparent top view Fig 6. Pin configuration IP20, SO20, SSOP20 and TSSOP20 Fig 7. (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as supply pin or input. Pin configuration HVQFN Pin description Table 3: Pin description Symbol Pin escription OE 1 3-state output enable input (active LOW) Q0 2 3-state latch output data input data input 1 Q1 5 3-state latch output 1 Q2 6 3-state latch output data input data input 3 Q3 9 3-state latch output 3 GN 10 ground (0 V) LE 11 latch enable input (active HIGH) Q state latch output data input data input 5 Product data sheet Rev January of 26

6 7. Functional description Table 3: Pin description continued Symbol Pin escription Q state latch output 5 Q state latch output data input data input 7 Q state latch output 7 V CC 20 supply voltage 7.1 Function table Table 4: Function table [1] Operating mode Control Input Internal Output OE LE n latches Qn Enable and L H L L L read register (transparent mode) H H H Latch and L L l L L read register h H H Latch register and disable outputs H X X X Z [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = don t care; Z = high-impedance OFF-state. Product data sheet Rev January of 26

7 8. Limiting values Table 5: Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC V - ±20 m I OK output clamping current V O < 0.5 V or - ±20 m V O >V CC V I O output current V O = 0.5 V to (V CC V) - ±35 m I CC quiescent supply current m I GN ground current - 70 m T stg storage temperature C P tot total power dissipation IP20 package [1] mw SO20 package [2] mw SSOP20 package [3] 500 mw TSSOP20 package [3] 500 mw HVQFN20 package [4] mw [1] For IP20 package: P tot derates linearly with 12 mw/k above 70 C. [2] For SO20: P tot derates linearly with 8 mw/k above 70 C. [3] For SSOP20 and TSSOP20 packages: P tot derates linearly with 5.5 mw/k above 60 C. [4] For HVQFN20 package: P tot derates linearly with 4.5 mw/k above 60 C. 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit 74HC373 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V T amb ambient temperature C t r, t f input rise and fall time V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns 74HCT373 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V T amb ambient temperature C t r, t f input rise and fall time V CC = 4.5 V ns Product data sheet Rev January of 26

8 10. Static characteristics Table 7: Static characteristics 74HC373 t recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb =25 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I = V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V V OL LOW-state output voltage V I = V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V I LI input leakage current V I =V CC or GN; V CC = 6.0 V - - ±0.1 µ I OZ OFF-state output current V I =V IH or V IL ; V CC = 6.0 V; - - ±0.5 µ V O =V CC or GN I CC quiescent supply current V CC = 6.0 V; I O = 0 ; µ V I =V CC or GN C i input capacitance pf T amb = 40 C to +85 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I = V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V Product data sheet Rev January of 26

9 Table 7: Static characteristics 74HC373 continued t recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V OL LOW-state output voltage V I = V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V I LI input leakage current V I =V CC or GN; V CC = 6.0 V - - ±1.0 µ I OZ OFF-state output current V I =V IH or V IL ; V CC = 6.0 V; - - ±5.0 µ V O =V CC or GN I CC quiescent supply current V CC = 6.0 V; I O = 0 ; V I =V CC or GN - 80 µ T amb = 40 C to +125 C V IH HIGH-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-state input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-state output voltage V I = V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V V OL LOW-state output voltage V I = V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 6.0 m; V CC = 4.5 V V I O = 7.8 m; V CC = 6.0 V V I LI input leakage current V I =V CC or GN; V CC = 6.0 V - - ±1.0 µ I OZ OFF-state output current V I =V IH or V IL ; V CC = 6.0 V; - - ±10.0 µ V O =V CC or GN I CC quiescent supply current V CC = 6.0 V; I O = 0 ; V I =V CC or GN µ Product data sheet Rev January of 26

10 Table 8: Static characteristics 74HCT373 t recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb =25 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I =V IH or V IL I O = 20 µ; V CC = 4.5 V V I O = 6.0 m; V CC = 4.5 V V V OL LOW-state output voltage V I =V IH or V IL I O =20µ; V CC = 4.5 V V I O = 6.0 m; V CC = 4.5 V V I LI input leakage current V I =V CC or GN; V CC = 5.5 V - - ±0.1 µ I OZ OFF-state output current V I =V IH or V IL ; V CC = 5.5 V; V O =V CC or GN per input pin; other inputs at V CC or GN; I O =0 - - ±0.5 µ I CC quiescent supply current V I =V CC or GN; I O =0; V CC = 5.5 V I CC additional quiescent supply current V I =V CC 2.1 V; other inputs at V CC or GN; V CC = 4.5 V to 5.5 V; I O = µ n µ LE µ OE µ C i input capacitance pf T amb = 40 C to +85 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I =V IH or V IL I O = 20 µ; V CC = 4.5 V V I O = 6.0 µ; V CC = 4.5 V V V OL LOW-state output voltage V I =V IH or V IL I O =20µ; V CC = 4.5 V V I O = 6.0 m; V CC = 4.5 V V I LI input leakage current V I =V CC or GN; V CC = 5.5 V - - ±1.0 µ I OZ OFF-state output current V I =V IH or V IL ; V CC = 5.5 V; V O =V CC or GN per input pin; other inputs at V CC or GN; I O =0 - - ±5.0 µ I CC quiescent supply current V I =V CC or GN; I O =0; V CC = 5.5 V I CC additional quiescent supply current V I =V CC 2.1 V; other inputs at V CC or GN; V CC = 4.5 V to 5.5 V; I O = µ n µ LE µ OE µ Product data sheet Rev January of 26

11 Table 8: Static characteristics 74HCT373 continued t recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +125 C V IH HIGH-state input voltage V CC = 4.5 V to 5.5 V V V IL LOW-state input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-state output voltage V I =V IH or V IL I O = 20 µ; V CC = 4.5 V V I O = 6.0 m; V CC = 4.5 V V V OL LOW-state output voltage V I =V IH or V IL I O =20µ; V CC = 4.5 V V I O = 6.0 m; V CC = 4.5 V V I LI input leakage current V I =V CC or GN; V CC = 5.5 V - - ±1.0 µ I OZ OFF-state output current V I =V IH or V IL ; V CC = 5.5 V; V O =V CC or GN per input pin; other inputs at V CC or GN; I O =0 - - ±10 µ I CC quiescent supply current V I =V CC or GN; I O =0; V CC = 5.5 V I CC additional quiescent supply current 11. ynamic characteristics V I =V CC 2.1 V; other inputs at V CC or GN; V CC = 4.5 V to 5.5 V; I O = µ n µ LE µ OE µ Table 9: ynamic characteristics 74HC373 Voltages are referenced to GN (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit T amb =25 C t PHL, t PLH propagation delay n to Qn see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC =5V; C L =15pF ns V CC = 6.0 V ns LE to Qn see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC =5V; C L =15pF ns V CC = 6.0 V ns Product data sheet Rev January of 26

12 Table 9: ynamic characteristics 74HC373 continued Voltages are referenced to GN (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit t PZH, t PZL t PHZ, t PLZ 3-state output enable time OE to Qn 3-state output disable time OE to Qn see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width LE HIGH see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time n to LE see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time n to LE see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns C P power dissipation capacitance per latch; V I = GN to V CC [1] pf T amb = 40 C to +85 C t PHL, t PLH propagation delay n to Qn see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns LE to Qn see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PZH, t PZL 3-state output enable time OE to Qn see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev January of 26

13 Table 9: ynamic characteristics 74HC373 continued Voltages are referenced to GN (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit t PHZ, t PLZ 3-state output disable time OE to Qn see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width LE HIGH see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time n to LE see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time n to LE see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns T amb = 40 C to +125 C t PHL, t PLH propagation delay n to Qn see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns LE to Qn see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PZH, t PZL t PHZ, t PLZ 3-state output enable time OE to Qn 3-state output disable time OE to Qn see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev January of 26

14 Table 9: ynamic characteristics 74HC373 continued Voltages are referenced to GN (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit t THL, t TLH output transition time see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width LE HIGH see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time n to LE see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time n to LE see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns [1] C P is used to determine the dynamic power dissipation (P in µw). P =C P V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Table 10: ynamic characteristics 74HCT373 Voltages are referenced to GN (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit T amb =25 C t PHL, t PLH propagation delay n to Qn see Figure 8 V CC = 4.5 V ns V CC =5V; C L =15pF ns LE to Qn see Figure 9 V CC = 4.5 V ns V CC =5V; C L =15pF ns t PZH, 3-state output enable time OE to Qn V CC = 4.5 V; see Figure ns t PZL t PHZ, 3-state output disable time OE to Qn V CC = 4.5 V; see Figure ns t PLZ t THL, output transition time V CC = 4.5 V; see Figure ns t TLH Product data sheet Rev January of 26

15 Table 10: ynamic characteristics 74HCT373 continued Voltages are referenced to GN (ground = 0 V); C L = 50 pf unless otherwise specified; for test circuit see Figure 12. Symbol Parameter Conditions Min Typ Max Unit time OE to Qn time OE to Qn t W pulse width LE HIGH V CC = 4.5 V; see Figure ns t su set-up time n to LE V CC = 4.5 V; see Figure ns t h hold time n to LE V CC = 4.5 V; see Figure ns C P power dissipation capacitance per latch; V I = GN to (V CC 1.5 V) [1] pf T amb = 40 C to +85 C t PHL, t PLH propagation delay n to Qn V CC = 4.5 V; see Figure ns LE to Qn V CC = 4.5 V; see Figure ns t PZH, 3-state output enable V CC = 4.5 V; see Figure ns t PZL t PHZ, 3-state output disable time OE to Qn V CC = 4.5 V; see Figure ns t PLZ t THL, output transition time V CC = 4.5 V; see Figure ns t TLH t W pulse width LE HIGH V CC = 4.5 V; see Figure ns t su set-up time n to LE V CC = 4.5 V; see Figure ns t h hold time n to LE V CC = 4.5 V; see Figure ns T amb = 40 C to +125 C t PHL, t PLH propagation delay n to Qn V CC = 4.5 V; see Figure ns LE to Qn V CC = 4.5 V; see Figure ns t PZH, 3-state output enable V CC = 4.5 V, see Figure ns t PZL t PHZ, 3-state output disable time OE to Qn V CC = 4.5 V; see Figure ns t PLZ t THL, output transition time V CC = 4.5 V; see Figure ns t TLH t W pulse width LE HIGH V CC = 4.5 V; see Figure ns t su set-up time n to LE V CC = 4.5 V; see Figure ns t h hold time n to LE V CC = 4.5 V; see Figure ns [1] C P is used to determine the dynamic power dissipation (P in µw). P =C P V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Product data sheet Rev January of 26

16 12. Waveforms n input t PLH t PHL Qn output 10 % 90 % t TLH t THL 001aae082 Fig 8. Measurement points are given in Table 11. Propagation delay input (n) to output (Qn) and transition time output (Qn) LE input t W t PHL t PLH Qn output 90 % 10 % t THL t TLH 001aae083 Fig 9. Measurement points are given in Table 11. Pulse width latch enable input (LE), propagation delay (LE) to output (Qn) and transition time output (Qn) Product data sheet Rev January of 26

17 V I OE input GN t PLZ t PZL V CC output LOW-to-OFF OFF-to-LOW V OL 10% t PHZ t PZH V OH output HIGH-to-OFF OFF-to-HIGH GN outputs enabled 90% outputs disabled outputs enabled 001aae307 Measurement points are given in Table 11. Fig state enable and disable time LE input t su t su t h t h n input 001aae084 Measurement points are given in Table 11. Fig 11. Set-up and hold time data input (n) to latch enable input (LE) Table 11: Measurement points Type Input Output 74HC V CC 0.5V CC 74HCT V 1.3 V Product data sheet Rev January of 26

18 V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC PULSE GENERTOR VI UT VO RL S1 open RT CL 001aad983 Test data is given in Table 12. efinitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator C L = Load capacitance including jig and probe capacitance R L = Load resistor S1 = Test selection switch Fig 12. Load circuitry for measuring switching times Table 12: Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC373 V CC 6 ns 15 pf, 50 pf 1 kω open GN V CC 74HCT373 3 V 6 ns 15 pf, 50 pf 1 kω open GN V CC Product data sheet Rev January of 26

19 13. Package outline IP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 M E seating plane 2 L 1 Z 20 e b b 1 11 w M c (e ) 1 M H pin 1 index E mm scale IMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEEC JEIT EUROPEN PROJECTION ISSUE TE SOT146-1 MS-001 SC Fig 13. Package outline SOT146-1 (IP20) Product data sheet Rev January of 26

20 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 E X c y H E v M Z Q 2 1 ( ) 3 pin 1 index L L p θ 1 e b p 10 w M detail X mm scale IMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEEC JEIT EUROPEN PROJECTION ISSUE TE SOT E04 MS Fig 14. Package outline SOT163-1 (SO20) Product data sheet Rev January of 26

21 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1 E X c y H E v M Z Q pin 1 index 2 1 ( ) 3 θ L L p 1 10 detail X e b p w M mm scale IMENSIONS (mm are the original dimensions) UNIT b p c (1) E (1) e H E L L p Q v w y Z (1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEEC JEIT SOT339-1 MO-150 EUROPEN PROJECTION ISSUE TE Fig 15. Package outline SOT339-1 (SSOP20) Product data sheet Rev January of 26

22 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E X c y H E v M Z Q pin 1 index 2 1 ( ) 3 θ 1 10 w M e b p L detail X L p mm scale IMENSIONS (mm are the original dimensions) UNIT b p c (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEEC JEIT SOT360-1 MO-153 EUROPEN PROJECTION ISSUE TE Fig 16. Package outline SOT360-1 (TSSOP20) Product data sheet Rev January of 26

23 HVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm SOT764-1 B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 9 v M w M C C B y 1 C C y L 1 10 E h e h X mm scale IMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c (1) h E (1) E h e e 1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEEC JEIT SOT MO EUROPEN PROJECTION ISSUE TE Fig 17. Package outline SOT764-1 (HVQFN20) Product data sheet Rev January of 26

24 14. bbreviations Table 13: cronym CMOS ES HBM MM TTL bbreviations escription Complementary Metal Oxide Semiconductor ElectroStatic ischarge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 14: Revision history ocument I Release date ata sheet status Change notice oc. number Supersedes Product data sheet HC_HCT373_CNV_2 Modifications: The format of this data sheet is redesigned to comply with the current presentation and information standard of Philips Semiconductors. dded type numbers 74HC373BQ and 74HCT373BQ (package HVQFN20). dded family specifications. dded abbreviations list. 74HC_HCT373_CNV_ Product specification Product data sheet Rev January of 26

25 16. ata sheet status Level ata sheet status [1] Product status [2] [3] efinition I Objective data evelopment This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17. efinitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18. isclaimers customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 19. Trademarks Notice ll referenced brands, product names, service names and trademarks are the property of their respective owners. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 20. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ Product data sheet Rev January of 26

26 21. Contents 1 General description Features Quick reference data Ordering information Functional diagram Pinning information Pinning Pin description Functional description Function table Limiting values Recommended operating conditions Static characteristics ynamic characteristics Waveforms Package outline bbreviations Revision history ata sheet status efinitions isclaimers Trademarks Contact information Koninklijke Philips Electronics N.V ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. ate of release: 20 January 2006 ocument number: Published in The Netherlands