74HC594; 74HCT bit shift register with output register
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- Terence Brown
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1 Rev December 2006 Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes. Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register. Synchronous serial input and output Complies with JEDEC standard No.7A 8-bit parallel output Shift and storage registers have independent direct clear and clocks Independent clocks for shift and storage registers 100 MHz (typical) Multiple package options Specified from 40 C to+85 C and from 40 C to +125 C Serial-to parallel data conversion Remote control holding register
2 4. Ordering information Table 1. Type number Ordering information Package Temperature Name Description Version range 74HC594D 40 C to +125 C SO16 plastic small outline package; 16 leads; SOT109-1 body width 3.9 mm 74HC594DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HC594N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT HCT594D 40 C to +125 C SO16 plastic small outline package; 16 leads; SOT109-1 body width 3.9 mm 74HCT594DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HCT594N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT Functional diagram DS SHCP SHR STAGE SHIFT REGISTER 9 Q7S STCP STR BIT STORAGE REGISTER Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mbc320 Fig 1. Functional diagram Product data sheet Rev December of 26
3 DS SHCP STCP Q7S 15 Q0 1 Q1 2 Q Q3 4 Q4 5 Q5 6 Q6 7 Q SHR STR mbc319 STR STCP SHR SHCP DS R1 SRG8 C1/ 1D R2 C2 15 2D mbc322 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q7S Fig 2. Logic symbol Fig 3. IEC logic symbol STAGE 0 STAGES 1 TO 6 STAGE 7 DS D Q FFSH0 D Q D Q FFSH7 Q7S CP R CP R SHCP SHR D Q FFST0 D Q FFST7 CP R CP R STCP STR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mbc321 Fig 4. Logic diagram Product data sheet Rev December of 26
4 SHCP DS STCP SHR STR Q0 Q1 Q6 Q7 Q7S mbc323 Fig 5. Timing diagram 6. Pinning information 6.1 Pinning 74HC594 74HCT594 Q V CC Q Q0 Q DS Q STR Q STCP Q SHCP Q SHR GND 8 9 Q7S 001aaf611 Fig 6. Pin configuration SO16 Product data sheet Rev December of 26
5 74HC594 74HCT594 Q V CC 74HC594 74HCT594 Q Q0 Q1 Q V CC Q0 Q3 Q DS STR Q3 Q4 Q DS STR STCP Q5 Q STCP SHCP Q6 Q7 GND SHCP SHR Q7S Q7 GND SHR Q7S 001aaf aaf614 Fig 7. Pin configuration SSOP16 Fig 8. Pin configuration DIP Pin description Table 2. Pin description Symbol Pin Description Q1 1 parallel data output 1 Q2 2 parallel data output 2 Q3 3 parallel data output 3 Q4 4 parallel data output 4 Q5 5 parallel data output 5 Q6 6 parallel data output 6 Q7 7 parallel data output 7 GND 8 ground (0 V) Q7S 9 serial data output SHR 10 shift register reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input STR 13 storage register reset (active LOW) DS 14 serial data input Q0 15 parallel data output 0 V CC 16 supply voltage Product data sheet Rev December of 26
6 7. Functional description Table 3. Function table [1] Function Input SHR STR SHCP STCP DS Clear shift register L X X X X Clear storage register X L X X X Load DS into shift register stage 0, advance previous stage data to the next stage H X X H or L Transfer shift register data to storage register and outputs Qn X H X X Shift register one count pulse ahead of storage register H H X [1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; X = don t care. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC V [1] - ±20 ma I OK output clamping current V O < 0.5 V or V O > V CC V [1] - ±20 ma I O output current V O = 0.5 V to V CC V - ±25 ma Parallel data output - ±35 ma I CC supply current - 50 ma Parallel data output - 70 ma I GND ground current - 50 ma Parallel data output - 70 ma T stg storage temperature C P tot total power dissipation T amb = 40 C to +125 C [2] mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For DIP16 packages: above 70 C the value of P tot derates linearly with 12 mw/k. For SO16 packages: above 70 C the value of P tot derates linearly with 8 mw/k. For SSOP16 packages: above 60 C the value of P tot derates linearly with 5.5 mw/k. Product data sheet Rev December of 26
7 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit Type 74HC594 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V T amb ambient temperature C t r rise time V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t f fall time V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Type 74HCT594 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V T amb ambient temperature C t r rise time V CC = 4.5 V ns t f fall time V CC = 4.5 V ns 10. Static characteristics Table 6. Static characteristics type 74HC594 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb = 25 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V Product data sheet Rev December of 26
8 Table 6. Static characteristics type 74HC594 continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V OL LOW-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V I I input leakage current V I =V CC or GND; V CC = 6.0 V - - ±0.1 µa I CC supply current V I = V CC or GND; I O = 0 A; µa V CC = 6.0 V C i input capacitance pf T amb = 40 C to +85 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V V OL LOW-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V I I input leakage current V I =V CC or GND; V CC = 6.0 V - - ±1.0 µa I CC supply current V I = V CC or GND; I O = 0 A; V CC = 6.0 V µa T amb = 40 C to +125 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V Product data sheet Rev December of 26
9 Table 6. Static characteristics type 74HC594 continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V V OL LOW-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 5.2 ma; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V I I input leakage current V I =V CC or GND; V CC = 6.0 V - - ±1.0 µa I CC supply current V I = V CC or GND; I O = 0 A; V CC = 6.0 V µa Product data sheet Rev December of 26
10 Table 7. Static characteristics type 74HCT594 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb = 25 C V IH HIGH-level input voltage V CC = 4.5 V to 5.5 V V V IL LOW-level input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 6.0 ma; V CC = 4.5 V V V OL LOW-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 6.0 ma; V CC = 4.5 V V I I input leakage current V I =V CC or GND; V CC = 5.5 V - - ±0.1 µa I CC supply current V I = V CC or GND; I O = 0 A; µa V CC = 5.5 V I CC additional supply current per input pin; V I =V CC 2.1 V and other inputs at V CC or GND; I O = 0 A; V CC = 4.5 V to 5.5 V pins SHR, SHCP, STCP, STR µa pin DS µa C i input capacitance pf T amb = 40 C to +85 C V IH HIGH-level input voltage V CC = 4.5 V to 5.5 V V V IL LOW-level input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 6.0 ma; V CC = 4.5 V V V OL LOW-level output voltage V I = V IH or V IL Serial data output I O = 4.0 ma; V CC = 4.5 V V I O = 6.0 ma; V CC = 4.5 V V I I input leakage current V I =V CC or GND; V CC = 5.5 V - - ±1.0 µa I CC supply current V I = V CC or GND; I O = 0 A; V CC = 5.5 V µa Product data sheet Rev December of 26
11 Table 7. Static characteristics type 74HCT594 continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit I CC additional supply current per input pin; V I =V CC 2.1 V and other inputs at V CC or GND; I O = 0 A; V CC = 4.5 V to 5.5 V pins SHR, SHCP, STCP, STR µa pin DS µa T amb = 40 C to +125 C V IH HIGH-level input voltage V CC = 4.5 V to 5.5 V V V IL LOW-level input voltage V CC = 4.5 V to 5.5 V V V OH HIGH-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 6.0 ma; V CC = 4.5 V V V OL LOW-level output voltage V I = V IH or V IL I O = 4.0 ma; V CC = 4.5 V V I O = 6.0 ma; V CC = 4.5 V V I I input leakage current V I =V CC or GND; V CC = 5.5 V - - ±1.0 µa I CC supply current V I = V CC or GND; I O = 0 A; µa V CC = 5.5 V I CC additional supply current per input pin; V I =V CC 2.1 V and other inputs at V CC or GND; I O = 0 A; V CC = 4.5 V to 5.5 V pins SHR, SHCP, STCP, STR µa pin DS µa Product data sheet Rev December of 26
12 11. Dynamic characteristics Table 8. Dynamic characteristics type 74HC594 GND = 0 V; t r = t f = 6 ns; C L = 50 pf; see Figure 15. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit t pd t PHL t THL propagation delay HIGH to LOW propagation delay HIGH to LOW output transition time [1] Min Typ Max Min Max Min Max SHCP to Q7S; see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5.0 V; ns C L = 15 pf V CC = 6.0 V ns STCP to Qn; see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5.0 V; ns C L = 15 pf V CC = 6.0 V ns SHR to Q7S; see Figure 13 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5.0 V; ns C L = 15 pf V CC = 6.0 V ns STR to Qn; see Figure 14 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5.0 V; ns C L = 15 pf V CC = 6.0 V ns see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev December of 26
13 Table 8. Dynamic characteristics type 74HC594 continued GND = 0 V; t r = t f = 6 ns; C L = 50 pf; see Figure 15. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit t TLH LOW to HIGH output transition time Min Typ Max Min Max Min Max see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width SHCP (HIGH or LOW); see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns STCP (HIGH or LOW); see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns SHR and STR (HIGH or LOW); see Figure 13 and Figure 14 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev December of 26
14 Table 8. Dynamic characteristics type 74HC594 continued GND = 0 V; t r = t f = 6 ns; C L = 50 pf; see Figure 15. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit t su set-up time DS to SHCP; see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns SHR to STCP; see Figure 12 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns SHCP to STCP; see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time DS to SHCP; see Figure 11 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t rec f max recovery time maximum frequency Min Typ Max Min Max Min Max SHR to SHCP and STR to STCP; see Figure 13 and Figure 14 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns SHCP or STCP; see Figure 9 and Figure 10 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 5.0 V; MHz C L = 15 pf V CC = 6.0 V MHz Product data sheet Rev December of 26
15 Table 8. Dynamic characteristics type 74HC594 continued GND = 0 V; t r = t f = 6 ns; C L = 50 pf; see Figure 15. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max [2] pf C PD power dissipation capacitance V I = GND to V CC ; V CC =5V; f i = 1 MHz [1] t pd is the same as t PHL and t PLH. [2] C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Table 9. Dynamic characteristics type 74HCT594 GND = 0 V; V CC = 4.5 V; t r = t f = 6 ns; C L = 50 pf; see Figure 15. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit t pd t PHL t THL t TLH propagation delay HIGH to LOW propagation delay SHCP to Q7S; see Figure 9 V CC = 5.0 V; C L = 15 pf STCP to Qn; see Figure 10 V CC = 5.0 V; C L = 15 pf SHR to Q7S; see Figure 13 V CC = 5.0 V; C L = 15 pf Min Typ Max Min Max Min Max [1] ns ns ns ns ns ns STR to Qn; see ns Figure 14 V CC = 5.0 V; C L = 15 pf ns HIGH to see Figure 9 LOW output transition time V CC = 4.5 V ns V CC = 4.5 V ns LOW to see Figure 9 HIGH output transition time V CC = 4.5 V ns V CC = 4.5 V ns Product data sheet Rev December of 26
16 Table 9. Dynamic characteristics type 74HCT594 continued GND = 0 V; V CC = 4.5 V; t r = t f = 6 ns; C L = 50 pf; see Figure 15. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit t W pulse width SHCP (HIGH or LOW); see Figure 9 STCP (HIGH or LOW); see Figure 10 SHR and STR (HIGH or LOW); see Figure 13 and Figure 14 t su set-up time DS to SHCP; see Figure 11 SHR to STCP; see Figure 12 SHCP to STCP; see Figure 10 t h hold time DS to SHCP; see Figure 11 t rec f max C PD recovery time maximum frequency power dissipation capacitance SHR to SHCP and STR to STCP; see Figure 13 and Figure 14 SHCP or STCP; see Figure 9 and Figure 10 V CC = 5.0 V; C L = 15 pf V I = GND to V CC 1.5 V; V CC =5V; f i = 1 MHz [1] t pd is the same as t PHL and t PLH. [2] C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Min Typ Max Min Max Min Max ns ns ns ns ns ns ns ns MHz MHz [2] pf Product data sheet Rev December of 26
17 12. Waveforms 1/f max SHCP input t W t PLH t PHL Q7S output t TLH t THL 001aae341 Fig 9. Measurement points are given in Table 10. t PLH and t PHL are the same as t pd. t TLH = LOW to HIGH output transition time; t THL = HIGH to LOW output transition time. The shift clock (SHCP) to output (Q7S) propagation delays, the shift clock pulse width, the maximum shift clock frequency, and output transition times SHCP input t su 1/ f max STCP input t W t PLH t PHL Qn outputs mla512 Measurement points are given in Table 10. t PLH and t PHL are the same as t pd. Fig 10. The storage clock (STCP) to output (Qn), propagation delays, the storage clock pulse width, the maximum storage clock pulse frequency and the shift clock to storage clock set-up time Product data sheet Rev December of 26
18 SHCP input t su t su t h th DS input Q7 output 001aae342 Measurement points are given in Table 10. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 11. The data set-up time and hold times for DS input to SHCP SHR input t su STCP input Qn outputs mbc326 Measurement points are given in Table 10. Fig 12. The set-up time shift reset (SHR) to storage clock (STCP) Product data sheet Rev December of 26
19 SHR input t W t rec SHCP input t PHL Q7S output mbc324 Measurement points are given in Table 10. t PLH and t PHL are the same as t pd. Fig 13. The shift reset (SHR) pulse width, the shift reset to output (Q7S) propagation delay and the shift reset to shift clock (SHCP) recovery time STR input t W t rec STCP input t PHL Qn outputs mbc325 Measurement points are given in Table 10. t PLH and t PHL are the same as t pd. Fig 14. The storage reset (STR) pulse width, the storage reset to output (Qn) propagation delay and the storage reset to storage clock (STCP) recovery time Table 10. Measurement points Type Input Output 74HC V CC 0.5 V CC 74HCT V 1.3 V Product data sheet Rev December of 26
20 V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC PULSE GENERATOR VI DUT VO RL S1 open RT CL 001aad983 Test data is given in Table 11. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator C L = Load capacitance including jig and probe capacitance R L = Load resistor S1 = Test selection switch Fig 15. Load circuitry for measuring switching times Table 11. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC594 V CC 6 ns 15 pf, 50 pf 1 kω open GND V CC 74HCT594 3 V 6 ns 15 pf, 50 pf 1 kω open GND V CC Product data sheet Rev December of 26
21 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y H E v M A Z 16 9 Q A 2 A 1 (A ) 3 A pin 1 index θ L p 1 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max A 1 A 2 A 3 b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT E07 MS Fig 16. Package outline SOT109-1 (SO16) Product data sheet Rev December of 26
22 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E A X c y H E v M A Z 16 9 Q A 2 A 1 (A ) 3 A pin 1 index 1 8 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) A UNIT A 1 A 2 A 3 b p c D (1) E (1) e H E L L p Q v w y Z(1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT338-1 MO Fig 17. Package outline SOT338-1 (SSOP16) Product data sheet Rev December of 26
23 DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D M E seating plane A 2 A L A 1 Z 16 e b b 1 9 b 2 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A A UNIT 1 A 2 (1) (1) (1) max. b 1 b 2 c D E e L M Z min. max. b e 1 M E H w max mm inches Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT Fig 18. Package outline SOT38-4 (DIP16) Product data sheet Rev December of 26
24 14. Abbreviations Table 12. Acronym CMOS DUT ESD HBM LSTTL MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Low-Power Schottky Transistor-Transistor Logic Machine Model Transistor-Transistor Logic 15. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes Product data sheet - 74HC_HCT594_CNV_2 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 1 Ordering information updated. 74HC_HCT594_CNV_ Product specification - 74HC_HCT594_CNV_1 Product data sheet Rev December of 26
25 16. Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: For sales office addresses, send an to: salesaddresses@nxp.com Product data sheet Rev December of 26
26 18. Contents 1 General description Features Applications Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 20 December 2006 Document identifier:
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Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.
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Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
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Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output
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Rev. 02 15 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
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Rev. 03 9 November 2007 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC32 and 74HCT32.
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Rev. 04 2 May 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
More informationTemperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.
Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance
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Rev. 01 7 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input EXCLUSIVE-OR function. Symmetrical output
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Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
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Rev. 06 5 November 2009 Product data sheet 1. General description The is a with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9),
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Rev. 0 30 June 2009 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
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Rev. 02 5 November 2007 Product data sheet. General description 2. Features 3. Ordering information The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They
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Rev. 03 2 January 2008 Product data sheet. General description 2. Features The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC259 and 74HCT259. The is a high-speed designed
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Rev. 06 2 February 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The
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Rev. 03 8 January 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4017. The is a 5-stage Johnson decade counter with
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Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
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Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state
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Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
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Rev. 03 12 November 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state
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Rev. 04 17 March 2009 Product data sheet 1. General description The is a for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE), an active HIGH
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Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input
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Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
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Rev. 04 19 March 2008 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate MOS device that complies with JEDE standard no. 7. It is pin compatible with
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Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance
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Rev. 02 7 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive
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Rev. 5 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
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Rev. 03 24 January 2006 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
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Rev. 4 12 May 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and
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Rev. 06 4 June 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (P) inputs, set (SD)
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Rev. 1 26 May 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit
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74LV9 Rev. 04 December 007 Product data sheet. General description. Features. Ordering information The 74LV9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC9 and 74HCT9.
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Rev. 4 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
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Rev. 3 22 September 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad buffer/line driver with 3-state outputs controlled by the output enable
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Rev. 03 22 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
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Rev. 3 21 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit inverting buffer/line driver with 3-state outputs. The device features
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Rev. 3 5 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current
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Rev. 3 15 September 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a 9-bit parity generator or checker. Both even and odd parity outputs are available.
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Rev. 3 8 May 29 Product data sheet 1. General description 2. Features 3. pplications 4. Ordering information The is a high-speed Si-gate CMOS device. The provides three inverting buffers with Schmitt trigger
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Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It
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Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
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Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance
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Rev. 4 17 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use
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Rev. 2 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
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Rev. 4 3 March 2016 Product data sheet 1. General description 2. Features and benefits The is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output enables (OE1
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Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).
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Rev. 6 21 November 2011 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a that compares two 4-bit words, A and B, and determines whether A is greater than
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Rev. 4 27 January 2016 Product data sheet 1. General description 2. Features and benefits The is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn
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Rev. 3 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
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Rev. 6 1 February 2016 Product data sheet 1. General description The is a dual 4-bit multiplexer, each with four binary inputs (ni0 to ni3), an output enable input (noe) and shared select inputs (S0 and
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Rev. 5 2 February 2016 Product data sheet 1. General description The is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn causes the outputs
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Rev. 05 23 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed, Si-gate CMOS device. The provides one non-inverting buffer/line driver with 3-state
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Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 02 28 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is
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Rev. 4 8 December 2015 Product data sheet 1. General description The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC08 and 74HCT08. The provides a quad 2-input AND function.
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Rev. 05 13 July 2009 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
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Rev. 03 6 September 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
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Rev. 3 16 August 2016 Product data sheet 1. General description The is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two
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Rev. 1 2 November 2015 Product data sheet 1. General description The is a high-speed Si-gate CMOS device. The provides two buffers. 2. Features and benefits 3. Ordering information Wide supply voltage
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Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable
More informationIn data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.
Important notice Dear Customer, On 7 February 07 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and
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Quad 2-input NND gate Rev. 5 25 November 200 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard
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Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).
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Rev. 04 16 June 2006 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
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Rev. 4 8 pril 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and
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Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 3 28 March 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes two binary weighted address inputs (n0, n1) to four mutually exclusive outputs
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Rev. 4 3 ugust 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The is a hex inverter. The inputs include clamp diodes that enable the use of current limiting
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Rev. 1 28 September 2016 Product data sheet 1. General description The is a dual positive edge triggered JK flip-flop featuring individual nj and nk inputs. It has clock (ncp) inputs, set (nsd) and reset
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Rev. 4 4 September 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
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Rev. 8 2 November 20 Product data sheet. General description 2. Features and benefits 3. pplications The is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP),
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