74HC4017; 74HCT4017. Johnson decade counter with 10 decoded outputs
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1 Rev January 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4017. The is a 5-stage Johnson decade counter with 10 decoded active HIGH outputs (Q0 to Q9), an active LOW output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see Table 3). When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). utomatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses. Multiple package options Complies with JEDEC standard no. 7 ESD protection: HBM JESD22-114E exceeds 2000 V MM JESD exceeds 200 V Specified from 40 C to+85 C and from 40 C to +125 C
2 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC HC4017N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT HC4017D 40 C to +125 C SO16 plastic small outline package; 16 leads; SOT109-1 body width 3.9 mm 74HC4017DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; SOT338-1 body width 5.3 mm 74HC4017PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74HC4017BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal-enhanced very thin quad flat package; no leads; 16 terminals; body mm SOT HCT HCT4017N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT HCT4017D 40 C to +125 C SO16 plastic small outline package; 16 leads; SOT109-1 body width 3.9 mm 74HCT4017BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal-enhanced very thin quad flat package; no leads; 16 terminals; body mm SOT Functional diagram CP1 CP0 MR 5-STGE JOHNSON COUNTER DECODING ND OUTPUT CIRCUITRY Q Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q aah242 Fig 1. Functional diagram Product data sheet Rev January of 23
3 CP1 CP0 MR Q0 3 Q1 2 Q2 4 Q3 7 Q4 10 Q5 1 Q6 5 Q7 6 Q8 9 Q9 Q CTRDIV10/DEC 0 & 1 CT = CT aah aah240 Fig 2. Logic symbol Fig 3. IEC logic symbol CP1 CP0 D Q FF 1 CP Q RD D Q FF 2 CP Q RD D Q FF 3 CP Q RD D Q FF 4 CP Q RD D Q FF 5 CP Q RD MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q aah243 Fig 4. Logic diagram Product data sheet Rev January of 23
4 CP0 INPUT CP1 INPUT MR INPUT Q0 OUTPUT Q1 OUTPUT Q2 OUTPUT Q3 OUTPUT Q4 OUTPUT Q5 OUTPUT Q6 OUTPUT Q7 OUTPUT Q8 OUTPUT Q9 OUTPUT Q5-9 OUTPUT 001aah244 Fig 5. Timing diagram Product data sheet Rev January of 23
5 5. Pinning information 5.1 Pinning 74HC HCT HC HCT4017 Q V CC Q MR Q CP0 Q CP1 Q Q5-9 Q Q9 Q Q4 GND 8 9 Q8 001aah238 terminal 1 index area Q1 Q0 Q2 Q5 1 MR CP0 CP1 Q Q5-9 Q7 6 GND (1) 11 Q9 Q Q4 GND VCC Q8 Transparent top view 001aah241 Fig 6. Pin configuration DIP16, SO16 and (T)SSOP16 Fig 7. Pin configuration DHVQFN Pin description Table 2. Pin description Symbol Pin Description Q[0:9] 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output GND 8 ground (0 V) Q carry output (active LOW) CP1 13 clock input (HIGH-to-LOW edge-triggered) CP0 14 clock input (LOW-to-HIGH edge-triggered) MR 15 master reset input (active HIGH) V CC 16 supply voltage Product data sheet Rev January of 23
6 6. Functional description Table 3. Function table [1] MR CP0 CP1 Operation H X X Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW L H counter advances L L counter advances L L X no change L X H no change L H no change L L no change [1] H = HIGH voltage level; L = LOW voltage level; X = don t care; = LOW-to-HIGH transition; = HIGH-to-LOW transition; 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input clamping current V I < 0.5 V or V I >V CC V [1] - ±20 m I OK output clamping current V O < 0.5 V or V O >V CC V [1] - ±20 m I O output current 0.5 V < V O < V CC V - ±25 m I CC supply current - 50 m I GND ground current 50 - m T stg storage temperature C P tot total power dissipation T amb = 40 C to +125 C DIP16 package [2] mw SO16 package [3] mw (T)SSOP16 package [4] mw DHVQFN16 package [5] mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] P tot derates linearly with 12 mw/k above 70 C. [3] P tot derates linearly with 8 mw/k above 70 C. [4] P tot derates linearly with 5.5 mw/k above 60 C. [5] P tot derates linearly with 4.5 mw/k above 60 C. Product data sheet Rev January of 23
7 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit 74HC4017 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V t/ V input transition rise and fall rate V CC = 2.0 V ns/v V CC = 4.5 V ns/v V CC = 6.0 V ns/v T amb ambient temperature C 74HCT4017 V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V t/ V input transition rise and fall rate V CC = 4.5 V ns/v T amb ambient temperature C 9. Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit 74HC4017 V IH HIGH-level input voltage V IL V OH LOW-level input voltage HIGH-level output voltage Min Typ Max Min Max Min Max V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V I =V IH or V IL I O = 20 µ; V CC = 2.0 V V I O = 20 µ; V CC = 4.5 V V I O = 20 µ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V Product data sheet Rev January of 23
8 Table 6. Static characteristics continued t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit V OL I I LOW-level output voltage input leakage current V I =V IH or V IL I O =20µ; V CC = 2.0 V V I O =20µ; V CC = 4.5 V V I O =20µ; V CC = 6.0 V V I O = 4.0 m; V CC = 4.5 V V I O = 5.2 m; V CC = 6.0 V V V I =V CC or GND; V CC = 6.0 V - - ±0.1 - ±1.0 - ±1.0 µ I CC supply current V I =V CC or GND; I O =0; µ V CC = 6.0 V C I input capacitance pf 74HCT4017 V IH HIGH-level V CC = 4.5 V to 5.5 V V input voltage V IL LOW-level V CC = 4.5 V to 5.5 V V input voltage V OH HIGH-level output voltage V I =V IH or V IL ; V CC = 4.5 V I O = 20 µ V I O = 4 m V V OL LOW-level output voltage V I =V IH or V IL ; V CC = 4.5 V I O =20µ V I O = 4.0 m V I I input leakage current V I =V CC or GND; V CC = 5.5 V I CC supply current V I =V CC or GND; V CC = 5.5 V; I O =0 I CC C I additional supply current input capacitance Min Typ Max Min Max Min Max - - ±0.1 - ±1.0 - ±1.0 µ µ per input pin; V I =V CC 2.1 V; other inputs at V CC or GND; V CC = 4.5 V to 5.5 V; I O =0 CP0 input µ CP1 input µ MR input µ pf Product data sheet Rev January of 23
9 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; t r = t f = 6 ns; C L = 50 pf; see Figure 11. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit 74HC4017 t pd propagation delay t PHL t PLH HIGH to LOW propagation delay LOW to HIGH propagation delay [1] Min Typ Max Min Max Min Max CP0 to Qn; CP0 to Q5-9; see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5.0 V; ns C L =15pF V CC = 6.0 V ns CP1 to Qn; CP1 to Q5-9; see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 5.0 V; ns C L =15pF V CC = 6.0 V ns MR to Q[1:9]; see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns MR to Q5-9, Q0; see Figure 10 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t t transition time see Figure 10 [2] V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W pulse width CP0 and CP1 (HIGH or LOW); see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns MR (HIGH); see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns Product data sheet Rev January of 23
10 Table 7. Dynamic characteristics continued GND = 0 V; t r = t f = 6 ns; C L = 50 pf; see Figure 11. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit t su set-up time CP1 to CP0; CP0 to CP1; see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time CP1 to CP0; CP0 to CP1; see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t rec recovery time MR to CP0 and MR to CP1; see Figure 9 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum CP0 or CP1; see Figure 9 frequency V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 5.0 V; MHz C L =15pF V CC = 6.0 V MHz C PD power dissipation capacitance 74HCT4017 t pd propagation delay t PHL t PLH HIGH to LOW propagation delay LOW to HIGH propagation delay V I = GND to V CC ; V CC =5V; f i = 1 MHz [3] pf [1] Min Typ Max Min Max Min Max CP0 to Qn; CP0 to Q5-9; see Figure 10 V CC = 4.5 V ns V CC = 5.0 V; ns C L =15pF CP1 to Qn; CP1 to Q5-9; see Figure 10 V CC = 4.5 V ns V CC = 5.0 V; C L =15pF ns MR to Q[1:9]; see Figure 10 V CC = 4.5 V ns MR to Q5-9, Q0; see Figure 10 V CC = 4.5 V ns Product data sheet Rev January of 23
11 Table 7. Dynamic characteristics continued GND = 0 V; t r = t f = 6 ns; C L = 50 pf; see Figure 11. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max t t transition time see Figure 10 [2] V CC = 4.5 V ns t W pulse width CP0 and CP1 (HIGH or LOW); see Figure 9 V CC = 4.5 V ns MR (HIGH); see Figure 9 V CC = 4.5 V ns t su set-up time CP1 to CP0; CP0 to CP1; see Figure 8 V CC = 4.5 V ns t h hold time CP1 to CP0; CP0 to CP1; see Figure 8 V CC = 4.5 V ns t rec recovery time MR to CP0 and MR to CP1; see Figure 9 V CC = 4.5 V ns f max maximum CP0 or CP1; see Figure 9 frequency V CC = 4.5 V MHz V CC = 5.0 V; MHz C L =15pF C PD power dissipation capacitance V I = GND to V CC 1.5 V; V CC =5V; f i = 1 MHz [3] pf [1] t pd is the same as t PHL and t PLH. [2] t t is the same as t THL and t TLH. [3] C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Product data sheet Rev January of 23
12 t W t rec NXP Semiconductors 11. Waveforms V I CP0 input GND t su t h t su t h V I CP1 input GND 001aah245 Fig 8. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Waveforms showing the set-up and hold times for CP0 to CP1 and CP1 to CP0 1/f max t W V I CP0 input GND V I CP1 input 1/f max GND V I MR input GND V OH Q1 - Q9 output V OL V OH Q0, Q5 - Q9 output V OL t W t PHL t PLH 001aah246 Fig 9. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays Product data sheet Rev January of 23
13 V I CP0 input GND V I CP1 input GND V OH Q1 - Q9 output V OL V OH Q0, Q5 - Q9 output V OL t PHL t PLH t TLH t PLH t PHL t THL 001aah247 Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Conditions: CP1 = LOW while CP0 is triggered on a LOW-to-HIGH transition and CP0 = HIGH, while CP1 is triggered on a HIGH-to-LOW transition. Fig 10. Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition times Table 8. Measurement points Type Input Output 74HC V CC 0.5 V CC 74HCT V 1.3 V Product data sheet Rev January of 23
14 V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V CC V CC PULSE GENERTOR VI DUT VO RL S1 open RT CL 001aad983 Test data is given in Table 9. Definitions test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S1 = Test selection switch. Fig 11. Load circuitry for measuring switching times Table 9. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH t PZH, t PHZ t PZL, t PLZ 74HC4017 V CC 6 ns 15 pf, 50 pf 1 kω open GND V CC 74HCT V 6 ns 15 pf, 50 pf 1 kω open GND V CC 12. pplication information Some examples of applications for the are: Decade counter with decimal decoding 1 out of n decoding counter (when cascaded) Sequential controller Timer Figure 12 shows a technique for extending the number of decoded output states for the. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay). Product data sheet Rev January of 23
15 CP0 MR 74HC HCT4017 CP1 Q0 Q Q8 Q9 CP0 MR 74HC HCT4017 CP1 Q0 Q Q8 Q9 CP0 MR 74HC HCT4017 CP1 Q Q8 Q9 9 decoded outputs 8 decoded outputs 8 decoded outputs clock first stage intermediate stages last stage 001aah248 Fig 12. Counter expansion Remark: It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, as this would cause an extra count. Figure 13 shows an example of a divide-by 2 through divide-by 10 circuit using one. Since the has an asynchronous reset, the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output pulse widths can be enlarged by inserting an RC network at the MR input. 74HC HCT4017 divide - by 5 Q5 V CC V CC Q1 MR Q0 CP0 fin divide - by 2 Q2 CP1 divide - by 6 divide - by 7 Q6 Q7 Q5-9 divide - by 10 Q9 divide - by 9 divide - by 3 Q3 Q4 divide - by 4 GND Q8 divide - by 8 fout 001aah249 Fig 13. Divide-by 2 through divide-by 10 Product data sheet Rev January of 23
16 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 D M E seating plane 2 L 1 Z 16 e b b 1 9 b 2 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT 1 2 (1) (1) (1) max. b 1 b 2 c D E e L M Z min. max. b e 1 M E H w max mm inches Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT Fig 14. Package outline SOT38-4 (DIP16) Product data sheet Rev January of 23
17 SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E X c y H E v M Z 16 9 Q 2 1 ( ) 3 pin 1 index θ L p 1 8 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT E07 MS Fig 15. Package outline SOT109-1 (SO16) Product data sheet Rev January of 23
18 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 D E X c y H E v M Z 16 9 Q 2 1 ( ) 3 pin 1 index 1 8 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p Q v w y Z(1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT338-1 MO Fig 16. Package outline SOT338-1 (SSOP16) Product data sheet Rev January of 23
19 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E X c y H E v M Z 16 9 pin 1 index 2 1 Q ( ) 3 θ 1 8 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT403-1 MO-153 EUROPEN PROJECTION ISSUE DTE Fig 17. Package outline SOT403-1 (TSSOP16) Product data sheet Rev January of 23
20 DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm SOT763-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 7 v M w M C C B y 1 C C y L 1 8 E h e D h X mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) E h e e 1 L v w y y 1 mm Note 1. Plastic or metal protrusions of mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT MO EUROPEN PROJECTION ISSUE DTE Fig 18. Package outline SOT763-1 (DHVQFN16) Product data sheet Rev January of 23
21 14. bbreviations Table 10. cronym CMOS DUT ESD HBM MM TTL bbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes Product data sheet - 74HC_HCT4017_CNV_2 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN16 package added. Section 7: derating values added for DHVQFN16 package. Section 13: outline drawing added for DHVQFN16 package. 74HC_HCT4017_CNV_ Product specification - - Product data sheet Rev January of 23
22 16. Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: For sales office addresses, send an to: salesaddresses@nxp.com Product data sheet Rev January of 23
23 18. Contents 1 General description Features Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms pplication information Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 8 January 2008 Document identifier:
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Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state
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Rev. 01 31 ugust 2009 Product data sheet 1. General description 2. Features 3. pplications is a high-speed Si-gate CMOS device. It provides an inverting buffer function with Schmitt trigger action. This
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Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
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Rev. 05 4 May 2009 Product data sheet. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
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Rev. 06 5 November 2009 Product data sheet 1. General description The is a with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9),
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Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use
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Rev. 5 1 July 27 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. It provides an inverting single stage function. The standard output
More information74HC154; 74HCT to-16 line decoder/demultiplexer
Rev. 06 2 February 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The
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74LV9 Rev. 04 December 007 Product data sheet. General description. Features. Ordering information The 74LV9 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC9 and 74HCT9.
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Rev. 04 27 pril 2009 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC2G126 and 74HCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line
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Rev. 03 24 January 2006 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
More informationTemperature range Name Description Version 74LVC74AD 40 C to +125 C SO14 plastic small outline package; 14 leads;
Rev. 06 4 June 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (P) inputs, set (SD)
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Rev. 02 7 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive
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Rev. 03 21 pril 2009 Product data sheet 1. General description 2. Features 3. pplications The is an 8 stage serial shift register with a storage register and 3-state outputs. Both the shift and storage
More information74HC594; 74HCT bit shift register with output register
Rev. 03 20 December 2006 Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The is
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Rev. 03 6 September 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
More informationThe 74LVC1G11 provides a single 3-input AND gate.
Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input
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Rev. 6 18 May 29 Product data sheet 1. General description 2. Features 3. pplications 74HC1G14 and 74HCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt
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Rev. 04 19 March 2008 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate MOS device that complies with JEDE standard no. 7. It is pin compatible with
More informationHEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder
Rev. 06 25 November 2009 Product data sheet 1. General description 2. Features 3. Applications The is a 4-bit, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer.
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Rev. 03 22 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
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Rev. 3 8 May 29 Product data sheet 1. General description 2. Features 3. pplications 4. Ordering information The is a high-speed Si-gate CMOS device. The provides three inverting buffers with Schmitt trigger
More information74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.
Quad 2-input NND gate Rev. 5 25 November 200 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard
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Rev. 02 15 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
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Rev. 06 20 December 2007 Product data sheet. General description 2. Features 3. pplications The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HCU04. The is a general purpose
More informationThe 74HC21 provide the 4-input AND function.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
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Rev. 06 6 March 2006 Product data sheet. General description 2. Features 3. Quick reference data The is a high-performance BiCMOS product designed for V CC operation at 3.3 V. This device combines low
More information74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate
Rev. 4 17 September 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual 4-input NOR gate. Inputs also include clamp diodes that enable the use
More information74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.
Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).
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Rev. 3 27 ugust 2012 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
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Rev. 02 28 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It is
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with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer
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Rev. 3 3 September 2012 Product data sheet 1. General description 2. Features and benefits The is a dual 4-input NND gate. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 4 8 pril 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and
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Rev. 4 4 September 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7. They are pin
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Rev. 05 13 July 2009 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
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Rev. 4 3 ugust 202 Product data sheet. General description 2. Features and benefits 3. Ordering information The is a hex inverter. The inputs include clamp diodes that enable the use of current limiting
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Rev. 4 12 May 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and
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Rev. 3 21 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit inverting buffer/line driver with 3-state outputs. The device features
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Rev. 05 23 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed, Si-gate CMOS device. The provides one non-inverting buffer/line driver with 3-state
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Rev. 1 30 January 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 1 4 July 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad 2-input NND gate with open-drain outputs. Inputs include clamp diodes that enable
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Rev. 02 18 October 2007 Product data sheet 1. General description 2. Features The is an octal -type transparent latch featuring separate -type inputs for each latch and 3-state true outputs for bus-oriented
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Rev. 7 2 December 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. Inputs include clamp diodes. This enables the use of current limiting resistors
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Rev. 3 28 March 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The decodes two binary weighted address inputs (n0, n1) to four mutually exclusive outputs
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Rev. 1 1 ugust 2012 Product data sheet 1. General description The is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages
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Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The is specified in compliance
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Rev. 4 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
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Rev. 6 20 November 2012 Product data sheet 1. General description The has eight edge-triggered D-type flip-flops with individual inputs (D) and outputs (Q). common clock input (CP) loads all flip-flops
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Rev. 04 16 June 2006 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
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Rev. 3 22 September 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a quad buffer/line driver with 3-state outputs controlled by the output enable
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Rev. 5 1 pril 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The 74HC393; 7474HCT393 is a dual 4-stage binary ripple counter. Each counter features a clock
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Rev. 8 2 November 20 Product data sheet. General description 2. Features and benefits 3. pplications The is a quad edge-triggered D-type flip-flop with four data inputs (D0 to D3), a clock input (CP),
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Rev. 1 30 January 2013 Product data sheet 1. General description The is a hex buffer with over-voltage tolerant inputs. Inputs are overvoltage tolerant to 15 V which enables the device to be used in HIGH-to-LOW
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3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible
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Rev. 2 26 January 2015 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a dual negative edge triggered JK flip-flop featuring individual J and K inputs,
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Rev. 03 20 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
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Rev. 03 4 February 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a low-voltage, Si-gate CMOS device and is pin and function compatible with the 74HC164 and 74HCT164.
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Rev. 03 14 September 2005 Product data sheet 1. General description 2. Features 3. pplications 4. uick reference data he are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series.
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Rev. 1 20 November 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky
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Rev. 04 17 March 2009 Product data sheet 1. General description The is a for liquid crystal and LED displays. It has four address inputs (D0 to D3), an active LOW latch enable input (LE), an active HIGH
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Rev. 5 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
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Rev. 2 11 February 2013 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The are 8-bit multiplexer with eight binary inputs (I0 to I7), three select inputs (S0
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Rev. 3 5 August 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is a triple 3-input NAND gate. Inputs include clamp diodes that enable the use of current
More information74HC08; 74HCT08. Temperature range Name Description Version. -40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.
Rev. 6 13 June 2017 Product data sheet 1 General description 2 Features and benefits 3 Ordering information Table 1. Ordering information Type number Package The is a quad 2-input ND gate. Inputs include
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Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It
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Rev. 03 20 January 2006 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL. It is specified in compliance with
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Rev. 6 0 November 20 Product data sheet. General description The provides six inverting buffers. The outputs are open-drain and can be connected to other open-drain outputs to implement active-low wired-or
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Rev. 9 July 202 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
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Rev. 3 16 August 2016 Product data sheet 1. General description The is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two
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Rev. 9 28 April 2016 Product data sheet 1. General description The is a with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).
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Rev. 7 4 March 2016 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device
More information74HC153-Q100; 74HCT153-Q100
Rev. 3 23 January 2014 Product data sheet 1. General description The is a dual 4-input multiplexer. The device features independent enable inputs (ne) and common data select inputs (S0 and S1). For each
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Rev. 6 3 ugust 0 Product data sheet. General description The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEDEC standard
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Rev. 01 29 November 2005 Product data sheet 1. General description 2. Features 3. pplications he is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HC4020.
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Rev. 1 11 November 2013 Product data sheet 1. General description The is a dual 2-input ND gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to s in
More information74HC365; 74HCT365. Hex buffer/line driver; 3-state
Rev. 4 27 January 2016 Product data sheet 1. General description 2. Features and benefits The is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (OEn). A HIGH on OEn
More information74HC259; 74HCT259. The 74HC259; 74HCT259 has four modes of operation:
Rev. 5 7 ugust 202 Product data sheet. General description The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
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Product data sheet 1. General description 2. Features 74HC238 and 74HCT238 are high-speed Si-gate CMOS devices and are pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC238/74HCT238 decoders
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Rev. 1 26 May 2014 Product data sheet 1. General description 2. Features and benefits 3. Ordering information The is an. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit
More information74HC541; 74HCT541. Octal buffer/line driver; 3-state
Rev. 4 3 March 2016 Product data sheet 1. General description 2. Features and benefits The is an octal non-inverting buffer/line driver with 3-state outputs. The device features two output enables (OE1
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