Dual JK flip-flop with reset; negative-edge trigger

Transcription

1 Rev March 2008 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate MOS device that complies with JEDE standard no. 7. It is pin compatible with Low-power Schottky TTL (LSTTL). The is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (np) and reset (nr) inputs; also complementary n and n outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. The reset (nr) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the n output LOW and the n output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Low-power dissipation omplies with JEDE standard no. 7 ESD protection: HBM JESD22-114E exceeds 2000 V MM JESD exceeds 200 V Multiple package options Specified from 40 to+80 and from 40 to +125 Table 1. Type number Ordering information Package Temperature range Name Description Version N 40 to +125 DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 D 40 to +125 SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 DB 40 to +125 SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 PW 40 to +125 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

2 4. Functional diagram 14 1J J P FF1 P 3 1K K 1 13 R 2 1R 7 2J J P FF2 P 10 2K K 2 8 R 6 2R 001aab981 Fig 1. Functional diagram J 2J 1P 2P 1K 2K J P K FF R 1R 2R aab J 1 1K R 1J 1 1K R 001aab Fig 2. Logic symbol Fig 3. IE logic symbol _4 Product data sheet Rev March of 16

3 K J R P 001aab982 Fig 4. Logic diagram (one flip-flop) 5. Pinning information 5.1 Pinning 1P J 1R K V 4 11 GND 2P K 2R J aab978 2 Fig 5. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description 1P, 2P 1, 5 clock input (HIGH-to-LOW edge-triggered); also referred to as np 1R, 2R 2, 6 asynchronous reset input (active LOW); also referred to as nr 1K, 2K 3, 10 synchronous K input; also referred to as nk V 4 positive supply voltage GND 11 ground (0 V) 1, 2 12, 9 true output; also referred to as n 1, 2 13, 8 complement output; also referred to as n 1J, 2J 14, 7 synchronous J input; also referred to as nj _4 Product data sheet Rev March of 16

4 6. Functional description Table 3. Function table [1] Input Output Operating mode nr np nj nk n n L X X X L H asynchronous reset H h h q q toggle H l h L H load 0 (reset) H h l H L load 1 (set) H l l q q hold (no change) [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition; q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition; X = don t care; = HIGH-to-LOW clock transition. 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IE 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions Min Max Unit V supply voltage V I IK input clamping current V I < 0.5 V or V I >V V [1] - ±20 m I OK output clamping current V O < 0.5 V or V O >V V [1] - ±20 m I O output current V O = 0.5 V to V V - ±25 m I supply current - 50 m I GND ground current 50 - m T stg storage temperature P tot total power dissipation T amb = 40 to +125 DIP14 package [2] mw SO14 package [3] mw (T)SSOP14 package [4] mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] P tot derates linearly with 12 mw/k above 70. [3] P tot derates linearly with 8 mw/k above 70. [4] P tot derates linearly with 5.5 mw/k above 60. _4 Product data sheet Rev March of 16

5 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter onditions Min Typ Max Unit V supply voltage V V I input voltage 0 - V V V O output voltage 0 - V V T amb ambient temperature t/ V input transition rise and fall rate V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns 9. Static characteristics Table 6. Static characteristics t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter onditions to to +125 Unit V IH V IL V OH V OL I I HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current Min Typ Max Min Max Min Max V = 2.0 V V V = 4.5 V V V = 6.0 V V V = 2.0 V V V = 4.5 V V V = 6.0 V V V I =V IH or V IL I O = 20 µ; V = 2.0 V V I O = 20 µ; V = 4.5 V V I O = 20 µ; V = 6.0 V V I O = 4 m; V = 4.5 V V I O = 5.2 m; V = 6.0 V V V I =V IH or V IL I O =20µ; V = 2.0 V V I O =20µ; V = 4.5 V V I O =20µ; V = 6.0 V V I O = 4 m; V = 4.5 V V I O = 5.2 m; V = 6.0 V V V I =V or GND; V = 6.0 V I supply current V I =V or GND; I O =0; V = 6.0 V I input capacitance - - ±0.1 - ±1.0 - ±1.0 µ µ pf _4 Product data sheet Rev March of 16

6 10. Dynamic characteristics Table 7. Dynamic characteristics GND (ground = 0 V); L = 50 pf unless otherwise specified; for test circuit, see Figure 8 Symbol Parameter onditions to to +125 Unit Min Typ Max Min Max Min Max t pd propagation np to n; see Figure 6 [1] delay V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns V = 5.0 V; L = 15 pf ns np to n; see Figure 6 V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns V = 5.0 V; L = 15 pf ns nr to n, n; see Figure 7 V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns V = 5.0 V; L = 15 pf ns t t transition time n, n; see Figure 6 [2] V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns t W pulse width np input, HIGH or LOW; see Figure 6 V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns nr input, HIGH or LOW; see Figure 7 V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns t rec recovery time nr to np; see Figure 7 V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns t su set-up time nj, nk to np; see Figure 6 V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns _4 Product data sheet Rev March of 16

7 Table 7. Dynamic characteristics continued GND (ground = 0 V); L = 50 pf unless otherwise specified; for test circuit, see Figure 8 Symbol Parameter onditions to to +125 Unit Min Typ Max Min Max Min Max t h hold time nj, nk to np; see Figure 6 V = 2.0 V ns V = 4.5 V ns V = 6.0 V ns f max maximum np input; see Figure 6 frequency V = 2.0 V MHz V = 4.5 V MHz V = 6.0 V MHz V = 5.0 V; L = 15 pf MHz PD power dissipation capacitance per flip-flop; V I = GND to V [3] pf [1] t pd is the same as t PHL, t PLH. [2] t t is the same as t THL, t TLH. [3] PD is used to determine the dynamic power dissipation (P D in µw). P D = PD V 2 f i N+ ( L V 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; L = output load capacitance in pf; V = supply voltage in V; N = number of inputs switching; ( L V 2 f o ) = sum of outputs. _4 Product data sheet Rev March of 16

8 11. Waveforms V I nj, nk input GND V I t su t h 1/f max t su t h np input GND t W V OH n output V OL V OH n output V OL t PHL t PLH 90 % 90 % 10 % 10 % t THL t TLH 90 % 90 % 10 % 10 % t TLH t THL t PLH t PHL 001aab983 Fig 6. The shaded areas indicate when the input is permitted to change for predictable output performance. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Waveforms showing the clock (np) to output (n, n) propagation delays, the clock pulse width, the J and K to np set-up and hold times, the output transition times and the maximum clock frequency V I np input GND t rec V I t W nr input GND t PHL V OH n output V OL V OH n output V OL t PLH 001aab984 Fig 7. Measurement points are given in Table 8. V OL and V OH are typical voltage output levels that occur with the output load. Waveforms showing the reset (nr) input to output (n, n) propagation delays and the reset pulse width and the nr to np removal time _4 Product data sheet Rev March of 16

9 Table 8. Measurement points Type Input Output V I V 0.5V 0.5V V I 90 % negative pulse GND 10 % t f t W t r V I positive pulse GND 10 % t r 90 % t W t f V G VI DUT VO RT L 001aah768 Fig 8. Test data is given in Table 9. Definitions for test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. L = Load capacitance including jig and probe capacitance. Test circuit for measuring switching times Table 9. Test data Type Input Load V I t r, t f L V 6 ns 15 pf, 50 pf _4 Product data sheet Rev March of 16

10 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D M E seating plane 2 L 1 Z 14 e b b 1 8 w M c (e ) 1 M H pin 1 index E mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENES IE JEDE JEIT EUROPEN PROJETION ISSUE DTE SOT G04 MO-001 S Fig 9. Package outline SOT27-1 (DIP14) _4 Product data sheet Rev March of 16

11 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E X c y H E v M Z 14 8 pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max b p c D (1) E (1) e H (1) E L L p v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENES IE JEDE JEIT EUROPEN PROJETION ISSUE DTE SOT E06 MS Fig 10. Package outline SOT108-1 (SO14) _4 Product data sheet Rev March of 16

12 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 D E X c y H E v M Z ( ) 3 pin 1 index 1 7 L detail X L p θ e b p w M mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (1) e H E L L p v w y Z(1) max. mm θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENES IE JEDE JEIT EUROPEN PROJETION ISSUE DTE SOT337-1 MO Fig 11. Package outline SOT337-1 (SSOP14) _4 Product data sheet Rev March of 16

13 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E X c y H E v M Z 14 8 pin 1 index 2 1 ( ) 3 θ 1 7 e b p w M L detail X L p mm scale DIMENSIONS (mm are the original dimensions) UNIT b p c D (1) E (2) e H (1) E L L p v w y Z max. mm θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENES IE JEDE JEIT SOT402-1 MO-153 EUROPEN PROJETION ISSUE DTE Fig 12. Package outline SOT402-1 (TSSOP14) _4 Product data sheet Rev March of 16

14 13. bbreviations Table 10. cronym MOS DUT ESD HBM MM TTL bbreviations Description omplementary Metal-Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status hange notice Supersedes _ Product data sheet - _3 Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. uick reference data incorporated into Section 9 and 10. Section 8 Recommended operating conditions t r, t f converted to t/ V. _ Product data sheet - 74H_HT73_NV_2 74H_HT73_NV_2 December 1990 Product specification - - _4 Product data sheet Rev March of 16

15 15. Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet ualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IE 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the haracteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 16. ontact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com _4 Product data sheet Rev March of 16

16 17. ontents 1 General description Features Ordering information Functional diagram Pinning information Pinning Pin description Functional description Limiting values Recommended operating conditions Static characteristics Dynamic characteristics Waveforms Package outline bbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks ontact information ontents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 19 March 2008 Document identifier: _4

17 Mouser Electronics uthorized Distributor lick to View Pricing, Inventory, Delivery & Lifecycle Information: Nexperia: D,652 DB,112 DB,118 D,653 PW,112 PW,118 NXP: D DB-T PW PW-T