74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting
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1 Rev November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL). The is specified in compliance with JEEC standard no. 7A. The is a octal -type flip-flop featuring separate -type inputs for each flip-flop and inverting 3-state outputs for bus oriented applications. A clock () and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual -inputs that meet the set-up and hold times requirements on the LOW-to-HIGH transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The is functionally identical to the 74HC574 but has inverting outputs. The is functionally identical to the 74HC534, but has a different pinning. 3-state inverting outputs for bus oriented applications 8-bit positive-edge triggered register Common 3-state output enable input Independent register and 3-state buffer operation Low-power dissipation Complies with JEEC standard no. 7A ES protection: HBM EIA/JES22-A114-B exceeds 2000 V MM EIA/JES22-A115-A exceeds 200 V. Multiple package options Specified from 40 C to+80 C and from 40 C to +125 C.
2 3. Quick reference data 4. Ordering information Table 1: Quick reference data GN = 0 V; T amb =25 C; t r =t f = 6 ns. Symbol Parameter Conditions Min Typ Max Unit t PHL, t PLH propagation delay to Qn C L = 15 pf; V CC =5 V ns f max maximum clock frequency C L = 15 pf; V CC =5 V [1] C P is used to determine the dynamic power dissipation (P in µw). P =C P V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs MHz C I input capacitance pf C P power dissipation capacitance per flip-flop V I = GN to V CC [1] pf Table 2: Type number Ordering information Package Temperature range Name escription Version N 40 C to +125 C IP20 plastic dual in-line package; 20 leads (300 mil) SOT C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 Product data sheet Rev November of 18
3 5. Functional diagram FF1 TO FF8 3 STATE OUTPUTS Q0 19 Q1 18 Q2 17 Q3 16 Q4 15 Q Q Q OE 001aab936 Fig 1. Functional diagram Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE EN C aab aab935 Fig 2. Logic symbol Fig 3. IEC logic symbol Product data sheet Rev November of 18
4 Q Q Q Q Q Q Q Q FF 1 FF 2 FF 3 FF 4 FF 5 FF 6 FF 7 FF 8 OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aab937 Fig 4. Logic diagram 6. Pinning information 6.1 Pinning OE 1 20 V CC Q Q Q Q3 Q Q Q Q7 GN aab844 Fig 5. Pin configuration Product data sheet Rev November of 18
5 6.2 Pin description 7. Functional description Table 3: Pin description Symbol Pin escription OE 1 3-state output enable input (active LOW) 0 2 data input data input data input data input data input data input data input data input 7 GN 10 ground (0 V) 11 clock input (LOW-to-HIGH, edge-triggered) Q state flip-flop output 7 Q state flip-flop output 6 Q state flip-flop output 5 Q state flip-flop output 4 Q state flip-flop output 3 Q state flip-flop output 2 Q state flip-flop output 1 Q state flip-flop output 0 V CC 20 positive supply voltage 7.1 Function table Table 4: Function table [1] Operating mode Input Internal Output OE n flip-flop Qn Load and read L l L H register h H L Load register and H l L Z disable output h H Z [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH transition; Z = high-impedance OFF-state; = LOW-to-HIGH clock transition. Product data sheet Rev November of 18
6 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage V I IK input diode current V I < 0.5 V or V I >V CC V - ±20 ma I OK output diode current V O < 0.5 V or - ±20 ma V O >V CC V I O output source or sink V O = 0.5 V to V CC V - ±35 ma current I CC, I GN V CC or GN current - ±70 ma T stg storage temperature C P tot power dissipation IP20 package [1] mw SO20 package [2] mw [1] Above 70 C: P tot derates linearly with 12 mw/k. [2] Above 70 C: P tot derates linearly with 8 mw/k. 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage V V I input voltage 0 - V CC V V O output voltage 0 - V CC V t r, t f input rise and fall times V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns T amb ambient temperature C Product data sheet Rev November of 18
7 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit T amb =25 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µa; V CC = 2.0 V V I O = 20 µa; V CC = 4.5 V V I O = 20 µa; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL I O =20µA; V CC = 2.0 V V I O =20µA; V CC = 4.5 V V I O =20µA; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V I LI input leakage current V I =V CC or GN; V CC = 6.0 V - - ±0.1 µa I OZ 3-state OFF-state current V I =V IH or V IL ; V CC = 6.0 V; V O =V CC or GN - - ±0.5 µa I CC quiescent supply current V I =V CC or GN; I O = 0 A; V CC = 6.0 V µa C I input capacitance pf T amb = 40 C to +85 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL I O = 20 µa; V CC = 2.0 V V I O = 20 µa; V CC = 4.5 V V I O = 20 µa; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V Product data sheet Rev November of 18
8 Table 7: Static characteristics continued At recommended operating conditions; voltages are referenced to GN (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit V OL LOW-level output voltage V I =V IH or V IL I O =20µA; V CC = 2.0 V V I O =20µA; V CC = 4.5 V V I O =20µA; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V I LI input leakage current V I =V CC or GN; V CC = 6.0 V - - ±1.0 µa I OZ 3-state OFF-state current V I =V IH or V IL ; V CC = 6.0 V; V O =V CC or GN - - ±5.0 µa I CC quiescent supply current V I =V CC or GN; I O = 0 A; V CC = 6.0 V µa T amb = 40 C to +125 C V IH HIGH-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V IL LOW-level input voltage V CC = 2.0 V V V CC = 4.5 V V V CC = 6.0 V V V OH HIGH-level output voltage V I =V IH or V IL - I O = 20 µa; V CC = 2.0 V V I O = 20 µa; V CC = 4.5 V V I O = 20 µa; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V V OL LOW-level output voltage V I =V IH or V IL - I O =20µA; V CC = 2.0 V V I O =20µA; V CC = 4.5 V V I O =20µA; V CC = 6.0 V V I O = 6.0 ma; V CC = 4.5 V V I O = 7.8 ma; V CC = 6.0 V V I LI input leakage current V I =V CC or GN; V CC = 6.0 V - - ±1.0 µa I OZ 3-state OFF-state current V I =V IH or V IL ; V CC = 6.0 V; V O =V CC or GN - - ±10.0 µa I CC quiescent supply current V I =V CC or GN; I O = 0 A; V CC = 6.0 V µa Product data sheet Rev November of 18
9 11. ynamic characteristics Table 8: ynamic characteristics GN = 0 V; t r =t f = 6 ns; C L = 50 pf; see Figure 9. Symbol Parameter Conditions Min Typ Max Unit T amb = 25 C t PHL, t PLH propagation delay to Qn see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns V CC = 5.0 V; C L =15pF ns t PZH, t PZL 3-state output enable time OE to Qn see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PHZ, t PLZ 3-state output disable time OE to Qn see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W clock pulse width HIGH or LOW see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time n to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time n to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum clock frequency see Figure 6 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz V CC = 5.0 V; C L = 15 pf MHz C P power dissipation capacitance per flip-flop V I = GN to V CC [1] pf Product data sheet Rev November of 18
10 Table 8: ynamic characteristics continued GN = 0 V; t r =t f = 6 ns; C L = 50 pf; see Figure 9. Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +85 C t PHL, t PLH propagation delay to Qn see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PZH, t PZL 3-state output enable time OE to Qn see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PHZ, t PLZ 3-state output disable time OE to Qn see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W clock pulse width HIGH or LOW see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time n to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time n to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum clock frequency see Figure 6 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz Product data sheet Rev November of 18
11 Table 8: ynamic characteristics continued GN = 0 V; t r =t f = 6 ns; C L = 50 pf; see Figure 9. Symbol Parameter Conditions Min Typ Max Unit T amb = 40 C to +125 C t PHL, t PLH propagation delay to Qn see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PZH, t PZL 3-state output enable time OE to Qn see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t PHZ, t PLZ 3-state output disable time OE to Qn see Figure 7 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t THL, t TLH output transition time see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t W clock pulse width HIGH or LOW see Figure 6 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t su set-up time n to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns t h hold time n to see Figure 8 V CC = 2.0 V ns V CC = 4.5 V ns V CC = 6.0 V ns f max maximum clock frequency see Figure 6 V CC = 2.0 V MHz V CC = 4.5 V MHz V CC = 6.0 V MHz [1] C P is used to determine the dynamic power dissipation (P in µw). P =C P V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of outputs. Product data sheet Rev November of 18
12 12. Waveforms 1/f max input V M t W t PHL t PLH Qn output V M t THL t TLH 001aab938 Fig 6. V M = 0.5 V I. Waveforms showing the clock () to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency t r t f OE input 10 % 90 % V M t PLZ t PZL output LOW to OFF OFF to LOW 10 % V M output HIGH to OFF OFF to HIGH t PHZ 90 % t PZH V M outputs enabled outputs disabled outputs enabled 001aab940 Fig 7. V M = 0.5 V I. Waveforms showing the 3-state enable and disable times Product data sheet Rev November of 18
13 input V M t su t su t h t h n input V M Qn input V M 001aab939 Fig 8. The shaded areas indicate when the input is permitted to change for predictable output performance. V M = 0.5 V I. Waveforms showing the data set-up and hold times for the data input (n) PULSE GENERATOR V I V CC.U.T. V O S 1 RL = 1000 Ω V CC open GN RT C L mna232 Fig 9. Test data is given in Table 9. efinitions for test circuit: R L = Load resistor. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to the output impedance Z o of the pulse generator. Load circuitry for switching times Table 9: Test data Supply Input Load S 1 V CC V I t r = t f C L R L t PZL, t PLZ t PZH, t PHZ t PHL, t PLH 2.0 V V CC 6 ns 50 pf 1 kω V CC GN open 4.5 V V CC 6 ns 50 pf 1 kω V CC GN open 6.0 V V CC 6 ns 50 pf 1 kω V CC GN open 5.0 V V CC 6 ns 15 pf 1 kω V CC GN open Product data sheet Rev November of 18
14 13. Package outline IP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 M E seating plane A 2 A L A 1 Z 20 e b b 1 11 w M c (e ) 1 M H pin 1 index E mm scale IMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. A 1 A 2 (1) (1) min. max. b b 1 c E e e 1 L M E M H w (1) Z max Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEEC JEITA EUROPEAN PROJECTION ISSUE ATE SOT146-1 MS-001 SC Fig 10. Package outline SOT146-1 (IP20) Product data sheet Rev November of 18
15 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 E A X c y H E v M A Z Q A 2 A 1 (A ) 3 A pin 1 index L L p θ 1 e b p 10 w M detail X mm scale IMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max A 1 A 2 A 3 b p c (1) E (1) e H (1) E L L p Q v w y Z Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included θ o 8 o OUTLINE VERSION REFERENCES IEC JEEC JEITA EUROPEAN PROJECTION ISSUE ATE SOT E04 MS Fig 11. Package outline SOT163-1 (SO20) Product data sheet Rev November of 18
16 14. Revision history Table 10: Revision history ocument I Release ata sheet status Change notice oc. number Supersedes date _ Product data sheet HC_HCT564_CNV_2 Modifications: The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. Removed type number 74HCT564. Inserted family specification. 74HC_HCT564_CNV_ Product specification HC_HCT564_1 74HC_HCT564_ Product specification Product data sheet Rev November of 18
17 15. ata sheet status Level ata sheet status [1] Product status [2] [3] efinition I Objective data evelopment This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. efinitions 17. isclaimers Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Life support These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Contact information For additional information, please visit: For sales office addresses, send an to: sales.addresses@ Product data sheet Rev November of 18
18 19. Contents 1 General description Features Quick reference data Ordering information Functional diagram Pinning information Pinning Pin description Functional description Function table Limiting values Recommended operating conditions Static characteristics ynamic characteristics Waveforms Package outline Revision history ata sheet status efinitions isclaimers Contact information Koninklijke Philips Electronics N.V All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. ate of release: 11 November 2004 ocument number: Published in The Netherlands
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